JP5695538B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a circuit that operates at a plurality of different voltages, and more particularly to a semiconductor device including an I / O (Input / Output) circuit.

  In recent years, semiconductor devices have become more sophisticated and multifunctional, and accordingly, higher integration (miniaturization of manufacturing methods) is also progressing. In such a semiconductor device, an I / O circuit connected to an external device or the like is mounted.

  The I / O circuit has not only basic I / O functions for input and output, but also a resistance pull-up function and a resistance pull-down function for external terminals, and when the internal core circuit is powered off, Adds a function to fix the output to the level conversion circuit arranged between the O voltage and suppresses the through current when the core voltage is indefinite, or has a circuit that keeps the terminal state when the internal core circuit is powered off As a result, higher functionality is progressing.

  Here, a low-potential voltage that operates a highly integrated transistor is called a core voltage, and a circuit that operates at such a low potential is called an internal core circuit. In addition, a high potential for operating a low-integration transistor for performing an external interface, for example, a voltage of 3.3 V or 5 V is referred to as an I / O voltage.

  Transistors that can withstand voltages such as 3.3 V and 5 V, which are external interface (I / F) voltages, are being used in I / O circuits, whereas circuits that operate at core voltages are becoming increasingly finer. Since it is necessary to obtain the characteristics, the gate oxide film of the transistor is not thinned, and the miniaturization of the manufacturing method is delayed.

  For example, the gate length of a transistor operating at a core voltage is 0.16 μm, while the gate length of a transistor in an I / O circuit is 1 μm. As a technology related to this, there is an invention disclosed in Patent Document 1 below.

  An integrated circuit for use in a disk drive disclosed in Patent Document 1 includes a core logic module connected to a core voltage, and an input / output buffer module connected to an input / output voltage. An input / output buffer module with connected input / output buffer control lines and an I / O that can operate so that the I / O buffer does not perform output operations whenever the core voltage is below a safe operating level A mode switch input of the buffer module. One embodiment comprises a core logic module that determines when a safe operating level is satisfied. Another embodiment is a separate connected operably connected to the core voltage and the input / output voltage to determine when a safe operating level is met and the output is connected to the mode switch input of the I / O buffer module. Level detection circuit module.

Special table 2003-530733 gazette

  As described above, since the degree of integration of the I / O circuit cannot be increased, the ratio of the area of the I / O circuit in the semiconductor device increases, which hinders the reduction of the area of the semiconductor device, that is, the cost reduction. It was a factor.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of reducing the area and cost.

  According to an embodiment of the present invention, a semiconductor device including a VDD system circuit that operates at a VDD voltage and an I / O circuit that operates at a VCC voltage higher than the VDD voltage is provided. The VDD circuit includes a pull-up permission register storing a first value for setting whether or not to permit connection of a pull-up resistor to an electrode to which an external device is connected, and an I / O circuit An I / O direction register storing a second value for setting the input / output direction of the I / O, and an I / O storing a third value to be output to the electrode when the I / O circuit is in an output state A register and a control circuit that selects either the first value or the third value in accordance with the second value and outputs the selected value as the fourth value are included.

  The semiconductor device further includes a power supply control unit that outputs a fifth value indicating whether or not the VDD voltage is cut off.

  The I / O circuit masks the second value and converts it to the VCC voltage level when the fifth value indicates the interruption of the VDD voltage, and when the fifth value does not indicate the interruption of the VDD voltage A first level conversion circuit that converts the second value into a VCC voltage level and outputs the same, and when the fifth value indicates the interruption of the VDD voltage, the fourth value is masked to the VCC voltage level. A second level conversion circuit that converts and outputs the fourth value to the VCC voltage level when the fifth value does not indicate the interruption of the VDD voltage, and is output from the first level conversion circuit. A tristate buffer for driving an external device connected to the electrode is included according to the value and the value output from the second level conversion circuit.

  According to one embodiment of the present invention, the control circuit selects either the first value or the third value according to the second value, and outputs it as the fourth value. The number of circuits can be reduced, and the semiconductor device can be reduced in area and cost.

It is a figure which shows the structural example of the semiconductor device carrying a general I / O circuit. 4 is a timing chart for explaining the operation of the power supply control unit 20 shown in FIG. 1. It is a figure which shows the other structural example of the semiconductor device carrying a general I / O circuit. 4 is a timing chart for explaining the operation of the power supply control unit 20 shown in FIG. 3. It is a figure which shows the structural example of the semiconductor device carrying the I / O circuit in the 1st Embodiment of this invention. FIG. 6 is a diagram illustrating a configuration example of a control circuit 50 illustrated in FIG. 5. It is a figure which shows the truth table of the control circuit 50 shown in FIG. 6 is a timing chart for explaining the operation of the power supply control unit 20 shown in FIG. 5. It is a figure which shows the structural example of the semiconductor device carrying the I / O circuit in the 2nd Embodiment of this invention. It is a timing chart for demonstrating operation | movement of the power supply control part 20 shown in FIG. 6 is a timing chart for explaining a delay at the time of output of the I / O circuit 60 in the first and second embodiments. It is a figure which shows the example of arrangement | positioning of the internal circuit of the semiconductor device in the 3rd Embodiment of this invention. It is a figure which shows the other example of arrangement | positioning of the internal circuit of the semiconductor device in the 3rd Embodiment of this invention.

  FIG. 1 is a diagram illustrating a configuration example of a semiconductor device on which a general I / O circuit is mounted. This semiconductor device is a low-potential circuit (hereinafter referred to as a VDD circuit) 1 composed of highly integrated transistors and a low-integration transistor for external interface such as 3.3V or 5V. A configured circuit (hereinafter referred to as a VCC system circuit) 11 and a power supply control unit 20 are included.

  The VDD system circuit 1 includes a CPU 2, a pull-up permission register 4, an I / O direction register 5, an I / O register 6, a serial I / O 7, a serial I / O terminal selection register 8, a selector 9 and 10 and AND circuits 12 to 14 and a part of the buffer 15.

  VCC system circuit 11 includes a tristate buffer 16, a NAND circuit 17, a P-channel MOS transistor (hereinafter abbreviated as a PMOS transistor) 18, AND circuits 12 to 14, and a part of the buffer 15. The tri-state buffer 16 includes a NAND circuit 22, a NOR circuit 23, a PMOS transistor 24, and an N-channel MOS transistor (hereinafter abbreviated as an NMOS transistor) 25.

  The I / O circuit 60 includes AND circuits 12 to 14, a buffer 15, a tristate buffer 16, a NAND circuit 17, and a PMOS transistor 18. The AND circuits 12 to 14 have a level conversion function for converting a VDD signal into a VCC signal, and the buffer 15 has a level conversion function for converting a VCC signal into a VDD signal.

  The CPU 2 is connected to the pull-up permission register 4, the I / O direction register 5, the I / O register 6, the serial I / O 7 and the serial I / O terminal selection register 8 via the internal bus 3. The entire semiconductor device is controlled by writing a value in the register.

  The pull-up enable register 4 is a register for permitting connection of a pull-up resistor in the I / O circuit 60. When “0”, connection of the pull-up resistor is prohibited, and when “1”, the pull-up resistor is disabled. Connection of up resistor is allowed.

  The I / O direction register 5 is a register for setting the input / output direction of the I / O circuit 60. When it is “0”, the I / O circuit 60 is set to the input state, and when it is “1”. The I / O circuit 60 is set to the output state.

  The I / O register 6 is a register for setting the output level when the I / O circuit 60 is set to the output state. When the I / O register 60 is “0”, the I / O register 6 has a low level (hereinafter referred to as L level). Abbreviated), and when it is “1”, a high level (hereinafter abbreviated as H level) is output to the electrode 19.

  The serial I / O 7 converts the parallel data received from the CPU 2 into serial data and outputs it as a signal 7b, and converts the serial data received from the buffer 15 in the I / O circuit 60 into parallel data and outputs it to the CPU 2. . The serial I / O 7 outputs “0” to the signal 7a when serial data is input, and outputs “1” to the signal 7a when serial data is output.

  The serial I / O terminal selection register 8 is a register for setting which of the I / O register 6 and the serial I / O 7 is to be selected, and when it is “0”, the I / O direction register 5 and the I / O register The output of the O register 6 is selected. When “1”, the output of the serial I / O 7 is selected.

  The selectors 9 and 10 are a signal 5 a output from the I / O direction register 5 and a signal output from the I / O register 6 when the signal 8 a output from the serial I / O terminal selection register 8 is “0”. 6a is selected and output.

  The selectors 9 and 10 select and output the signals 7a and 7b output from the serial I / O 7 when the signal 8a output from the serial I / O terminal selection register 8 is “1”.

  The power supply control unit 20 controls the VCC voltage and the VDD voltage, and outputs a signal 21 for uniquely fixing the polarity of the level shifter to the AND circuits 12 to 14. When the power supply control unit 20 outputs “0” to the signal 21, the output signals 12 a to 14 a of the AND circuits 12 to 14 are fixed to “0”, and the electrode 19 that connects the semiconductor device and an external device is high. It becomes an impedance state.

  When the power supply control unit 20 outputs “1” to the signal 21, the AND circuits 12 to 14 output the pull-up control signal 4 a and the output permission signal 9 a output from the pull-up permission register 4 and the selectors 9 and 10. And the same value as the output data signal 10a is output.

  In the NAND circuit 17, when the signal 12a output from the AND circuit 12 is "1" and the signal 13a output from the AND circuit 13 is "0", that is, the connection of the pull-up resistor is permitted. When the / O circuit 60 is in the input state, “0” is output to the signal 17a to turn on the PMOS transistor 18 and connect the pull-up resistor. In other cases, the NAND circuit 17 outputs “1” to the signal 17a to turn off the PMOS transistor 18 and disconnect the pull-up resistor.

  In the NAND circuit 22, when the signals 13a and 14a output from the AND circuits 13 and 14 are “1”, that is, the value output from the I / O register 6 or the serial I / O 7 is “1”. When the / O circuit 60 is in the output state, “0” is output to turn on the PMOS transistor 24. As a result, the H level is output to the electrode 19. At this time, since the NOR circuit 23 outputs “0”, the NMOS transistor 25 is off.

  In the NOR circuit 23, when the signal 13a output from the AND circuit 13 is "1" and the signal 14a output from the AND circuit 14 is "0", that is, output from the I / O register 6 or the serial I / O7. When the value to be set is “0” and the I / O circuit 60 is in the output state, “1” is output and the NMOS transistor 25 is turned on. As a result, the L level is output to the electrode 19. At this time, since the NAND circuit 22 outputs “1”, the PMOS transistor 24 is off.

  FIG. 2 is a timing chart for explaining the operation of the power supply control unit 20 shown in FIG. At T1, the power supply control unit 20 starts supplying the VCC voltage, and further starts supplying the VDD voltage. At T2, the power supply control unit 20 changes the signal 21 from “0” to “1”. Thus, when power is turned on, unintended I / O output is prohibited until the VDD potential generated by stepping down the VCC voltage is stabilized.

  Further, at T3, the VDD voltage is cut off to shift to the low power consumption mode, and at T4, the supply of the VDD voltage is resumed to return to the normal mode. During the period from T3 to T4, the power supply control unit 20 outputs “0” to the signal 21 to prevent a through current of the level conversion circuits (AND circuits) 12 to 14 due to indefinite VDD voltage.

  FIG. 3 is a diagram illustrating another configuration example of a semiconductor device on which a general I / O circuit is mounted. Compared to the configuration example of the semiconductor device shown in FIG. 1, only the point that latch circuits 31 to 33 are added to the VCC circuit 11 and the function is added to the power supply control unit 20 are different. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  The latch circuits 31 to 33 pass through the signals 12 a, 13 a and 14 a output from the AND circuits 12 to 14 when the signal 30 output from the power supply control unit 20 is “1”, and AND at the falling edge of the signal 30. The values of the signals 12a, 13a and 14a output from the circuits 12 to 14 are held.

  FIG. 4 is a timing chart for explaining the operation of the power supply control unit 20 shown in FIG. In T1, the power supply control unit 20 starts supplying the VCC voltage, and further starts supplying the VDD voltage. In T2, the signal control unit 20 changes the signal 21 from “0” to “1”.

  Further, when the power supply control unit 20 cuts off the VDD voltage and shifts to the low power consumption mode, the signal 30 is set to “0” and output from the AND circuits 12 to 13 to the latch circuits 31 to 33 at T3. The states of the signals 12a, 13a and 14a are maintained. At T4, the supply of the VDD voltage is interrupted and “0” is output to the signal 21.

  Further, when the power supply control unit 20 resumes the supply of the VDD voltage and returns to the normal mode at T5, the signal 30 is set to “1” and is output from the AND circuits 12 to 14 to the latch circuits 31 to 33 at T6. The values of the signals 12a, 13a and 14a to be transmitted are passed.

(First embodiment)
FIG. 5 is a diagram illustrating a configuration example of the semiconductor device on which the I / O circuit according to the first embodiment of the present invention is mounted. Compared to the configuration example of the semiconductor device shown in FIG. 1, a control circuit 50 is added in the VDD system circuit 1, the AND circuit 12 in the VCC system circuit 11 is deleted, and the connection of the NAND circuit 17 is changed. Only the point is different. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  FIG. 6 is a diagram showing a configuration example of the control circuit 50 shown in FIG. The control circuit 50 includes a selector 53, and outputs the output permission signal 9a output from the selector 9 as it is as the signal 50a. The selector 53 selects the pull-up control signal 4a output from the pull-up permission register 4 when the output permission signal 9a output from the selector 9 is “0”, and outputs it to the AND circuit 13 as a signal 50b. Further, the selector 53 selects the output data signal 10a output from the selector 10 when the output permission signal 9a output from the selector 9 is “1”, and outputs it to the AND circuit 14 as a signal 50b.

  FIG. 7 is a diagram showing a truth table of the control circuit 50 shown in FIG. The pull-up control signal 4a output from the pull-up enable register 4 is “0”, the output enable signal 9a output from the selector 9 is “0”, and the output data signal 10a output from the selector 10 is “0” or “ In the case of “1”, the control circuit 50 outputs “0” to the signal 50a and “0” to the signal 50b. At this time, the NAND circuit 17 outputs “1” to the signal 17a to turn off the PMOS transistor 18, the NAND circuit 22 outputs “1” to turn off the PMOS transistor 24, and the NOR circuit 23 sets “0”. The NMOS transistor 25 is turned off by outputting. As a result, the electrode 19 enters a high impedance state.

  When the pull-up control signal 4a output from the pull-up enable register 4 is "0", the output enable signal 9a output from the selector 9 is "1", and the output data signal 10a output from the selector 10 is "0" The control circuit 50 outputs “1” as the signal 50a and “0” as the signal 50b. At this time, the NAND circuit 17 outputs “1” to the signal 17a to turn off the PMOS transistor 18, the NAND circuit 22 outputs “1” to turn off the PMOS transistor 24, and the NOR circuit 23 sets “1”. The NMOS transistor 25 is turned on by outputting. As a result, the L level is output from the electrode 19.

  Control is performed when the pull-up control signal 4a output from the pull-up enable register 4 is "0", the signal 9a output from the selector 9 is "1", and the output data signal 10a output from the selector 10 is "1". The circuit 50 outputs “1” to the signal 50a and outputs “1” to the signal 50b. At this time, the NAND circuit 17 outputs “1” to the signal 17a to turn off the PMOS transistor 18, the NAND circuit 22 outputs “0” to turn on the PMOS transistor 24, and the NOR circuit 23 sets “0”. The NMOS transistor 25 is turned off by outputting. As a result, the H level is output from the electrode 19.

  The pull-up control signal 4a output from the pull-up enable register 4 is “1”, the output enable signal 9a output from the selector 9 is “0”, and the output data signal 10a output from the selector 10 is “0” or “ In the case of “1”, the control circuit 50 outputs “0” to the signal 50a and “1” to the signal 50b. At this time, the NAND circuit 17 outputs “0” to the signal 17 a to turn on the PMOS transistor 18, the NAND circuit 22 outputs “1” to turn off the PMOS transistor 24, and the NOR circuit 23 sets “0”. The NMOS transistor 25 is turned off by outputting. As a result, a pull-up resistor is connected to the electrode 19.

  When the pull-up control signal 4a output from the pull-up enable register 4 is "1", the output enable signal 9a output from the selector 9 is "1", and the output data signal 10a output from the selector 10 is "0" The control circuit 50 outputs “1” as the signal 50a and “0” as the signal 50b. At this time, the NAND circuit 17 outputs “1” to the signal 17a to turn off the PMOS transistor 18, the NAND circuit 22 outputs “1” to turn off the PMOS transistor 24, and the NOR circuit 23 sets “1”. The NMOS transistor 25 is turned on by outputting. As a result, the L level is output from the electrode 19.

  When the pull-up control signal 4a output from the pull-up enable register 4 is "1", the output enable signal 9a output from the selector 9 is "1", and the output data signal 10a output from the selector 10 is "1" The control circuit 50 outputs “1” as the signal 50a and “1” as the signal 50b. At this time, the NAND circuit 17 outputs “1” to the signal 17a to turn off the PMOS transistor 18, the NAND circuit 22 outputs “0” to turn on the PMOS transistor 24, and the NOR circuit 23 sets “0”. The NMOS transistor 25 is turned off by outputting. As a result, the H level is output from the electrode 19.

  FIG. 8 is a timing chart for explaining the operation of the power supply control unit 20 shown in FIG. At T1, the power supply control unit 20 starts supplying the VCC voltage, and further starts supplying the VDD voltage. At T2, the power supply control unit 20 changes the signal 21 from “0” to “1”. Thus, when power is turned on, unintended I / O output is prohibited until the VDD potential generated by stepping down the VCC voltage is stabilized.

  Further, at T3, the VDD voltage is cut off to shift to the low power consumption mode, and at T4, the supply of the VDD voltage is resumed to return to the normal mode. During the period from T3 to T4, the power supply control unit 20 outputs “0” to the signal 21 to prevent a through current of the level conversion circuits (AND circuits) 13 to 14 due to indefinite VDD voltage.

  As described above, according to the semiconductor device of the present embodiment, the control circuit 50 has the pull-up control signal 4a output from the pull-up permission register 4, the output permission signal 9a output from the selector 9, and the selector 10. The 3-bit information of the output data signal 10a output from is encoded into 2-bit information. As a result, the number of level conversion circuits composed of transistors with low integration in the I / O circuit 60 can be reduced, and the area of the semiconductor device can be reduced and the cost can be reduced.

(Second Embodiment)
FIG. 9 is a diagram illustrating a configuration example of a semiconductor device on which an I / O circuit according to the second embodiment of the present invention is mounted. Compared to the configuration example of the semiconductor device according to the first embodiment shown in FIG. 5, latch circuits 32 to 33 are added to the VCC circuit 11 and a function is added to the power supply control unit 20. Only the point is different. Compared with the configuration example of the semiconductor device shown in FIG. 3, the control circuit 50 is added in the VDD system circuit 1, the AND circuit 12 and the latch circuit 31 in the VCC system circuit 11 are deleted, and the NAND circuit 17 The only difference is that the connection has changed. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  The latch circuits 32 to 33 pass through the signals 13 a and 14 a output from the AND circuits 13 to 14 when the signal 30 output from the power supply control unit 20 is “1”, and the AND circuit 13 at the falling edge of the signal 30. The values of the signals 13a and 14a output from -14 are held.

  FIG. 10 is a timing chart for explaining the operation of the power supply control unit 20 shown in FIG. In T1, the power supply control unit 20 starts supplying the VCC voltage, and further starts supplying the VDD voltage. In T2, the signal control unit 20 changes the signal 21 from “0” to “1”.

  Further, when the power supply control unit 20 cuts off the VDD voltage and shifts to the low power consumption mode, the signal 30 is set to “0” and is output from the AND circuits 13 to 13 to the latch circuits 32 to 33 at T3. The states of the signals 13a and 14a are maintained. At T4, the supply of the VDD voltage is interrupted and “0” is output to the signal 21.

  Further, when the power supply control unit 20 resumes the supply of the VDD voltage and returns to the normal mode at T5, the signal 30 is set to “1” and is output from the AND circuits 13 to 14 to the latch circuits 32 to 33 at T6. The values of the signals 13a and 14a are passed through.

  As described above, according to the semiconductor device of the present embodiment, the control circuit 50 has the pull-up control signal 4a output from the pull-up permission register 4, the output permission signal 9a output from the selector 9, and the selector 10. The 3-bit information of the output data signal 10a output from is encoded into 2-bit information. As a result, the number of level conversion circuits and latch circuits configured by transistors with low integration in the I / O circuit 60 can be reduced, and the semiconductor device can be reduced in area and cost. became.

(Third embodiment)
FIG. 11 is a timing chart for explaining a delay at the time of output of the I / O circuit 60 in the first and second embodiments. When the output permission signal 9a output from the selector 9 becomes “1” at T1, the control circuit 50 outputs “1” to the signal 50a. At this time, since the output data signal 10a output from the selector 10 is “0”, the control circuit 50 outputs “0” to the signal 50b. As a result, the tristate buffer 16 outputs an L level to the electrode 19.

  When the output permission signal 9a output from the selector 9 becomes “0” at T2, the control circuit 50 outputs “0” to the signal 50a. At this time, since the pull-up control signal 4a output from the pull-up permission register 4 is “0”, the control circuit 50 outputs “0” to the signal 50b. As a result, the tristate buffer 16 makes the electrode 19 high impedance.

  When the output permission signal 9a output from the selector 9 becomes “1” at T3, the control circuit 50 outputs “1” to the signal 50a. At this time, since the output data signal 10a output from the selector 10 is “1”, the control circuit 50 outputs “1” to the signal 50b. Normally, the output data signal 10a is determined before the output is permitted by the output permission signal 9a. However, since it is encoded into a 2-bit signal by the control circuit 50, the output from the control circuit 50 is determined after the output permission signal 9a is confirmed. The output signal 50b is determined.

  At this time, since the signal 50b has a delay, the L level is output to the electrode 19 corresponding to the delay time. Depending on the positional relationship of the circuit from the control circuit 50 to the electrode 19, this delay time may be increased.

  In the third embodiment of the present invention, this delay time is shortened to prevent malfunction of an external device connected to the electrode 19.

  FIG. 12 is a diagram showing an arrangement example of internal circuits of the semiconductor device according to the third embodiment of the present invention. The region 63 is a region where components of the VDD system circuit 1 other than the control circuit 50 are arranged, and an I / O circuit 60 including the control circuit 50 is arranged around the region 63.

  The power supply line 51 and the ground line 52 of the control circuit 50 are arranged so as to go around the region 63, and the power supply line 61 and the ground line 62 of the tristate buffer 16 are arranged on the outer periphery thereof. As a result, the components of the I / O circuit 60 can be arranged so that the distance from the control circuit 50 and the level conversion circuits 13 and 14 to the tristate buffer 16 is minimized, and the delay time can be shortened.

  FIG. 13 is a diagram showing another arrangement example of the internal circuit of the semiconductor device according to the third embodiment of the present invention. A power supply 51 and a ground 52 of the control circuit 50 are arranged around the semiconductor device at the boundary between an IP (Intellectual Property) 64 such as the CPU 2 and memory and the I / O circuit 60.

  As described above, according to the semiconductor device of the present embodiment, power supply line 61 and ground line 62 of tristate buffer 16 are arranged on the outer periphery of power supply line 51 and ground line 52 of control circuit 50. Thus, the delay time from the control circuit 50 to the tristate buffer 16 can be shortened, and malfunction of an external device connected to the electrode 19 can be prevented.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 VDD system circuit, 2 CPU, 3 internal bus, 4 pull-up enable register, 5 I / O direction register, 6 I / O register, 7 serial I / O, 8 serial I / O terminal selection register, 9, 10 selector 11 VCC circuit, 12-14 AND circuit, 15 buffer, 16 tristate buffer, 17, 22 NAND circuit, 18, 24 PMOS transistor, 20 power control unit, 23 NOR circuit, 25 NMOS transistor, 31-33 latch circuit 50 Control circuit.

Claims (5)

A semiconductor device including a circuit group operating at a first voltage and an input / output circuit operating at a second voltage higher than the first voltage,
The circuit group includes a first storage unit that stores a first value for setting whether to permit connection of a pull-up resistor to an electrode to which an external device is connected;
Second storage means for storing a second value for setting the input / output direction of the input / output circuit;
Third storage means for storing a third value to be output to the electrode when the input / output circuit is in an output state;
Selecting means for selecting one of the first value and the third value according to the second value and outputting the selected value as a fourth value;
The semiconductor device further includes power control means for outputting a fifth value indicating whether or not the first voltage is cut off,
The input / output circuit masks the second value and converts it to the second voltage level when the fifth value indicates an interruption of the first voltage, and the fifth value is First conversion means for converting the second value into the second voltage level and outputting the second value when not indicating the interruption of the first voltage;
When the fifth value indicates an interruption of the first voltage, the fourth value is masked and converted to the second voltage level, and the fifth value is equal to the first voltage. Second conversion means for converting the fourth value to the second voltage level and outputting the second value when not indicating an interruption;
A semiconductor device comprising: buffer means for driving the external device connected to the electrode in accordance with a value output from the first conversion means and a value output from the second conversion means.   The input / output circuit further includes a transistor that switches connection and disconnection of the pull-up resistor according to a value output from the first conversion unit and a value output from the second conversion unit. Item 14. A semiconductor device according to Item 1.   A plurality of the input / output circuits are arranged around the circuit group, the power supply line of the selection unit is arranged to circulate around the circuit group, and the power supply line of the buffer unit is arranged on the outer periphery thereof. 3. The semiconductor device according to 1 or 2. A semiconductor device including a circuit group operating at a first voltage and an input / output circuit operating at a second voltage higher than the first voltage,
The circuit group includes a first storage unit that stores a first value for setting whether to permit connection of a pull-up resistor to an electrode to which an external device is connected;
Second storage means for storing a second value for setting the input / output direction of the input / output circuit;
Third storage means for storing a third value to be output to the electrode when the input / output circuit is in an output state;
Selecting means for selecting one of the first value and the third value according to the second value and outputting the selected value as a fourth value;
The semiconductor device further includes a fifth value indicating whether or not the first voltage is cut off, and a sixth value indicating whether or not the input / output circuit holds the value output to the electrode. Power supply control means for outputting
The input / output circuit masks the second value and converts it to the second voltage level when the fifth value indicates an interruption of the first voltage, and the fifth value is First conversion means for converting the second value into the second voltage level and outputting the second value when not indicating the interruption of the first voltage;
When the fifth value indicates an interruption of the first voltage, the fourth value is masked and converted to the second voltage level, and the fifth value is equal to the first voltage. Second conversion means for converting the fourth value to the second voltage level and outputting the second value when not indicating an interruption;
First holding means for holding and outputting the value output from the first conversion means according to the sixth value output from the power supply control means;
Second holding means for holding and outputting the value output from the second conversion means according to the sixth value output from the power supply control means;
A semiconductor device comprising: buffer means for driving the external device connected to the electrode according to a value output from the first holding means and a value output from the second holding means.   The input / output circuit further includes a transistor that switches connection and disconnection of the pull-up resistor according to a value output from the first holding unit and a value output from the second holding unit. Item 5. The semiconductor device according to Item 4.

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