JP2012222614A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set a state of an external terminal in a programmable way according to a condition after an operation start such as a type of a program to execute and a type of abnormality occurring.SOLUTION: Control data for controlling terminal states of input/output terminals at the time of abnormality occurrence with respect to each state of data processing executed by a program processing circuit, each type of program or each type of data processing executed by the program processing circuit, or each type of abnormality caused by data processing is preliminarily stored in a nonvolatile storage part (140). A search key for identifying the control data stored in the nonvolatile storage part is successively set before program execution or at the time of program execution. In the case where abnormality occurs, the state of each of the input/output terminals is set at a state of pull-up, pull-down, high-impedance or holding previous value in accordance with the control data referred based on the search key.

Description

  The present invention relates to an initial setting or preset for an external terminal of a semiconductor device, and relates to a technique effective when applied to an initialization function for an external terminal when an abnormality occurs in a data processing device such as a microcomputer or a data processor.

  In Patent Document 1, as part of the initialization operation at the time of power-on, the input state of the input / output port is selectively set to the pull-up or pull-down state using a switch that is switch-controlled by the control data of the nonvolatile memory. A semiconductor device is described. Thereby, it is not necessary to attach a pull-up circuit or a pull-down circuit to the semiconductor device. Further, the initial state of the input / output port can be variably set by changing the control data.

JP 2010-147606 A

  The technique described in Patent Document 1 determines an initial state of an input / output port in an initialization operation when power is turned on. Once the state is determined, the state is maintained until the power is turned off. No particular consideration is given to changes after the initial setting. The present inventor not only performs initialization at power-on, but also generates an interrupt or exception, an event such as an undesired decrease in power supply voltage occurs during data processing, and accordingly, a mode terminal, a control terminal, etc. We studied how to control the input / output states of external terminals in a programmable manner. In other words, it is possible to fix the state of the desired external terminal according to the situation, such as the type of program executed by the semiconductor device, and also the type of abnormality that has occurred. Recognized that it would be possible to increase. Patent Document 1 does not focus on such a viewpoint at all.

  An object of the present invention is to provide a semiconductor device in which the state of an external terminal can be set in a programmable manner in accordance with the situation after the start of operation, such as the type of program to be executed or the type of abnormality that occurs.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, for each data processing state by the program processing circuit, a type of program or data processing executed by the program processing circuit, or for each type of abnormality due to data processing, control data for controlling the terminal state of the input / output terminals when an abnormality occurs A search key is stored in advance in the non-volatile storage unit, and a search key for specifying the control data is sequentially set in the non-volatile storage unit before or during execution of the program. When an abnormality occurs, the state of the input / output terminal is set to a pull-up, pull-down, high impedance, or previous value holding state in accordance with the control data referred to based on the search key.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the state of the external terminal can be fixed in a programmable manner according to the situation after the start of operation, such as the type of program to be executed or the type of abnormality that occurs. Therefore, depending on the abnormality recognized by the semiconductor device and the program currently being executed by the semiconductor device, the state of the peripheral circuit connected to the external terminal of the semiconductor device, and further the state of the semiconductor device itself is a required state. Can be controlled.

FIG. 1 is a block diagram illustrating a semiconductor device according to the first embodiment of the invention. FIG. 2 is a timing chart illustrating the operation timing of the nonvolatile memory unit accompanying the data processing operation of the semiconductor device of FIG. FIG. 3 is a block diagram illustrating a data processing system using the semiconductor device of FIG. FIG. 4 is a timing chart illustrating the operation timing of the data processing system of FIG. FIG. 5 is a block diagram showing another example of a data processing system using the semiconductor device of FIG. FIG. 6 is a timing chart illustrating the operation timing of the data processing system of FIG. FIG. 7 is a block diagram illustrating a semiconductor device according to the second embodiment of the invention. FIG. 8 is a timing chart illustrating the operation timing using the nonvolatile memory portion accompanying the data processing operation of the semiconductor device of FIG. FIG. 9 is a block diagram illustrating a data processing system using the semiconductor device of FIG. FIG. 10 is an explanatory diagram illustrating information stored in the first lookup table 244 used in the data processing system of FIG. FIG. 11 is an explanatory diagram illustrating information stored in the second lookup table used in the data processing system of FIG. FIG. 12 is a block diagram illustrating a semiconductor device according to the third embodiment of the invention. FIG. 13 is a block diagram illustrating a semiconductor device according to the fourth embodiment of the invention.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <External terminal setting according to the internal state when a predetermined event occurs, depending on hardware>
A semiconductor device (100) according to a representative embodiment of the present invention includes a plurality of external terminals (106), an interface unit (105) connected to the external terminals, and interface control for controlling the interface unit. Part (132). Further, the semiconductor device is connected to the data processing unit and a data processing unit (101) for processing an input signal input from the interface control unit, generating an output signal output from the interface unit, and other data processing A non-volatile storage unit (140). The interface unit includes a tristate output buffer circuit (110) having an output terminal connected to the predetermined external terminal, an input buffer circuit (111) having an input terminal connected to the predetermined external terminal, and the predetermined A terminal state setting circuit (112) that is connected to the external terminal and selectively sets the external terminal to a pull-up, pull-down, open, or previous value holding state; The non-volatile storage unit has an area for storing a control data look-up table (141) using a state specification code for specifying the state of the external terminal as a search key, and according to data processing by the data processing unit The state designation code is stored in advance, and when the occurrence of a predetermined event is notified from the data processing unit, control data is read from the lookup table using the state designation code stored in advance according to the data processing. The interface control unit controls the tristate output buffer circuit and the terminal state setting circuit according to the read control data to determine the state of the predetermined external terminal.

  As a result, a lookup table is prepared, the state designation code is stored in advance according to the data processing by the data processing unit, and when the abnormality occurs, the lookup table is referenced using the state designation code. The state of the external terminal can be set in a programmable manner according to the situation. In particular, the non-volatile storage unit autonomously searches the lookup table using the search key and supplies the retrieved control data to the input / output control circuit. It is not necessary to secure sex. Therefore, depending on the abnormality recognized by the semiconductor device and the program currently being executed by the semiconductor device, the state of the peripheral circuit connected to the external terminal of the semiconductor device, and further the state of the semiconductor device itself is a required state. Can be controlled.

[2] <Use state designation code stored in nonvolatile register in advance when an abnormality occurs>
2. The semiconductor device according to item 1, wherein the nonvolatile storage unit includes a nonvolatile state designation code register (143) in which the state designation code can be written by the data processing unit, and a predetermined event is generated from the data processing unit. Is notified, the control data retrieved from the lookup table using the state designation code of the state designation code register is output to the interface unit.

  According to this, since the state designation code corresponding to the occurrence of the predetermined event corresponding to each type of data processing has only to be written in the nonvolatile state designation code register in advance, the preset state designation code is used when the predetermined event occurs. It is possible to prevent the occurrence of a situation that is lost or changed by this.

[3] <Data processing unit sets control code in nonvolatile register as part of data processing>
In the semiconductor device according to Item 2, the data processing unit writes a required status designation code in the status designation code register in advance at the beginning of the data processing as part of the data processing.

  According to this, the data processing part should just bear operation which writes the state designation | designated code at the time of the predetermined event corresponding to each classification of data processing in a non-volatile memory | storage part.

[4] <Set tristate output buffer to HiZ and set pin state>
In the semiconductor device according to Item 3, the interface control unit sets the terminal state setting circuit in a pull-up, pull-down, open, or previous value holding state by setting the tristate output buffer to high impedance according to the control data. The state of a predetermined external terminal is determined.

  Regardless of the state of the tristate output buffer when a predetermined event occurs, it becomes easy to stabilize the external input / output terminal to the state indicated by the control data.

[5] <Pin state setting according to power supply voltage drop>
In the semiconductor device according to Item 3, when the predetermined event is a change of a power supply voltage detected by a power supply detector (152) to a predetermined voltage or less, the nonvolatile memory unit receives the power supply voltage from the data processing unit. When the change to the predetermined voltage or lower is notified, the control data retrieved from the look-up table using the state designation code stored in the state designation code register is output to the interface unit.

  The state of the predetermined external terminal can be set as desired in response to the change of the power supply voltage to a predetermined voltage or less.

[6] <Pin state setting according to a predetermined interrupt factor or exception factor>
In the semiconductor device according to Item 3, when the predetermined event is a predetermined interrupt factor or exception factor, the nonvolatile storage unit is notified of the occurrence of the predetermined interrupt factor or exception factor from the data processing unit. Thus, the control data retrieved from the lookup table using the state designation code held in the state designation code register is output to the interface unit.

  The state of the predetermined external terminal can be set as desired in response to occurrence of a predetermined interrupt factor or exception factor.

[7] <Instruction execution address when a predetermined event occurs and external terminal setting based on the event occurrence factor, hardware-dependent>
A semiconductor device (200) according to another embodiment of the present invention includes a plurality of external terminals (106), an interface unit (105) connected to the external terminals, and an interface control unit that controls the interface unit. (132). Further, the semiconductor device includes a data processing unit (201) that performs processing of an input signal input from the interface control unit, generation of an output signal output from the interface unit, program processing for executing an instruction, and other data processing; A nonvolatile storage unit (240) connected to the data processing unit. The interface unit includes a tristate output buffer circuit (110) having an output terminal connected to the predetermined external terminal, an input buffer circuit (111) having an input terminal connected to the predetermined external terminal, and the predetermined A terminal state setting circuit (112) that is connected to the external terminal and selectively sets the external terminal to a pull-up, pull-down, open, or previous value holding state; The non-volatile storage unit has an area for storing a non-volatile execution address register (243) that sequentially holds instruction address information for capturing a current execution instruction address by the data processing unit. Further, the nonvolatile storage unit is configured to associate a state designation code of an external terminal with a cause of occurrence of a predetermined event assumed during execution of a program in the range for each program address range executed by the data processing unit. It has an area for storing a lookup table (244) and a second lookup table (241) of control data using the state designation code as a search key. Further, when the occurrence of a predetermined event is notified from the data processing unit, the non-volatile storage unit receives a state designation code from the first lookup table based on the instruction address information of the execution address register and the occurrence factor of the predetermined event. And the control data is read from the second look-up table using the acquired state designation code and provided to the interface control unit. The interface control unit controls the tristate output buffer circuit and the terminal state setting circuit according to the given control data to determine the state of the predetermined external terminal.

  As a result, the first and second look-up tables are prepared in the non-volatile memory portion in advance, and the information in the execution address register is rewritten with the address information of the execution address as the data processing proceeds. Since the first and second lookup tables are referred to based on the address information, the state of the external terminal can be set in a programmable manner according to the data processing status to be executed. In particular, the non-volatile storage unit autonomously searches for control data using the first and second look-up tables and supplies the retrieved control data to the input / output control circuit. There is no need to ensure the soundness of the data processing department. Therefore, depending on the abnormality recognized by the semiconductor device and the program currently being executed by the semiconductor device, the state of the peripheral circuit connected to the external terminal of the semiconductor device, and further the state of the semiconductor device itself is a required state. Can be controlled.

[8] <Execution address register configured with MRAM>
In the semiconductor device of item 7, the execution address register is an MRAM (Magnetoresistive Random Access Memory).

  The instruction address can be rewritten at high speed in synchronization with the instruction execution cycle.

[9] <Set the terminal state by setting the tristate output buffer to HiZ>
In the semiconductor device according to Item 7, the interface control unit sets the terminal state setting circuit in a pull-up, pull-down, open, or previous value holding state by setting the tristate output buffer to high impedance according to the control data. The state of a predetermined external terminal is determined.

  It is possible to easily stabilize the external input / output terminal to the state indicated by the control data regardless of the state of the tristate output buffer when a predetermined event occurs.

[10] <Setting of terminal state according to power supply voltage drop>
In the semiconductor device according to Item 7, when the generation factor of the predetermined event is a change of a power supply voltage detected by a power supply detector to a predetermined voltage or less, the nonvolatile memory unit is caused by a change to the predetermined voltage or less. When the occurrence of the interrupt factor is notified from the data processing unit, the state designation code corresponding to the value of the execution address register and the factor is acquired from the first lookup table. Then, the control data is acquired from the second look-up table using the acquired state designation code and output to the interface unit.

  The state of the predetermined external terminal can be set as desired in response to the change of the power supply voltage to a predetermined voltage or less.

[11] <Pin state setting according to predetermined interrupt factor or exception factor>
In the semiconductor device according to Item 7, when the occurrence factor of the predetermined event is a predetermined interrupt factor or an exception factor, the nonvolatile memory unit notifies the data processing unit of the occurrence of the predetermined interrupt factor or the exception factor. Then, the state designation code corresponding to the value of the execution address register and the factor at that time is acquired from the first lookup table. Then, the control data is read from the second look-up table using the acquired state designation code and output to the interface unit.

  The state of the predetermined external terminal can be set as desired in response to occurrence of a predetermined interrupt factor or exception factor.

[12] <External terminal setting according to internal state when a predetermined event occurs, software dependent>
A semiconductor device (300) according to still another embodiment of the present invention includes a plurality of external terminals, an interface unit connected to the external terminals, an interface control unit that controls the interface unit, and the interface control unit. A data processing unit (101A) that performs processing of input signals, generation of output signals output from the interface unit, and other data processing; a non-volatile storage unit (140A) connected to the data processing unit; Have The interface unit includes a tristate output buffer circuit having an output terminal connected to the predetermined external terminal, an input buffer circuit having an input terminal connected to the predetermined external terminal, and a predetermined external terminal connected to the interface unit. And a terminal state setting circuit for selectively setting the external terminal to a pull-up, pull-down, open, or previous value holding state. The nonvolatile storage unit has an area for storing a control data look-up table using a state designation code for designating the state of the external terminal as a search key. The data processing unit stores the state designation code in the nonvolatile storage unit in advance according to data processing, and when the occurrence of a predetermined event is notified, the state designation code stored in the nonvolatile storage unit is stored in advance. To read control data from the lookup table. The interface control unit controls the tristate output buffer circuit and the terminal state setting circuit according to the read control data to determine the state of the predetermined external terminal.

  The semiconductor device according to item 12 is different from the semiconductor device according to item 1 in that the data processing unit searches the lookup table using the state designation code. Therefore, the nonvolatile storage unit does not need to have a lookup table search function based on the state designation code, and can deal with software processing by using the data processing unit. Therefore, it is premised that the soundness of the data processing unit is ensured even when a predetermined event occurs, and it is possible to cope with the occurrence of an event where the data processing of the data processing unit becomes impossible to return due to the occurrence of the predetermined event. Can not. About the other point, there exists an effect similar to item 1.

[13] <Use state designation code stored in advance in nonvolatile register when abnormality occurs>
In the semiconductor device according to item 12, the nonvolatile storage unit includes a nonvolatile state designation code register (143) into which the state designation code can be written by the data processing unit. When the occurrence of a predetermined event is detected, the data processing unit outputs the control data retrieved from the lookup table using the state designation code of the state designation code register to the interface unit.

  According to this, since the state designation code corresponding to the occurrence of the predetermined event corresponding to each type of data processing has only to be written in the nonvolatile state designation code register in advance, the preset state designation code is used when the predetermined event occurs. It is possible to prevent the occurrence of a situation that is lost or changed by this.

[14] <Data processing unit sets control code in nonvolatile register as part of data processing>
In the semiconductor device according to Item 13, the data processing unit writes a required state designation code in the state designation code register in advance at the beginning of the data processing as part of the data processing.

  According to this, the data processing part should just bear operation which writes the state designation | designated code at the time of the predetermined event corresponding to each classification of data processing in a non-volatile memory | storage part.

[15] <Set the terminal state by setting the tristate output buffer to HiZ>
14. The semiconductor device according to item 14, wherein the interface control unit sets the terminal state setting circuit in a pull-up, pull-down, open, or previous value holding state by setting the tri-state output buffer to high impedance according to the control data. The state of a predetermined external terminal is determined.

  Regardless of the state of the tristate output buffer when a predetermined event occurs, it becomes easy to stabilize the external input / output terminal to the state indicated by the control data.

[16] <Setting of terminal state according to power supply voltage drop>
14. In the semiconductor device according to Item 14, when the predetermined event is a change of a power supply voltage detected by a power supply detector to a predetermined voltage or less, the data processing unit outputs the power supply detector below a predetermined voltage of the power supply voltage or less. The control data retrieved from the look-up table using the state designation code stored in the state designation code register is output to the interface unit.

  The state of the predetermined external terminal can be set as desired in response to the change of the power supply voltage to a predetermined voltage or less.

[17] <Pin state setting according to predetermined interrupt factor or exception factor>
14. In the semiconductor device according to Item 14, when the predetermined event is a predetermined interrupt factor or an exception factor, the data processing unit performs the state designation code by an interrupt process using the predetermined interrupt factor or an exception process using a predetermined exception factor. The control data retrieved from the lookup table using the state designation code held by the register is output to the interface unit.

  The state of the predetermined external terminal can be set as desired in response to occurrence of a predetermined interrupt factor or exception factor.

[18] <Execution execution address when a predetermined event occurs and external terminal setting based on the event occurrence factor, software dependency>
A semiconductor device (400) according to still another embodiment of the present invention includes a plurality of external terminals, an interface unit connected to the external terminals, and an interface control unit that controls the interface unit. Further, the semiconductor device includes a data processing unit (201A) that performs processing of an input signal input from the interface control unit, generation of an output signal output from the interface unit, program processing for executing an instruction, and other data processing, A nonvolatile storage unit (240A) connected to the data processing unit. The interface unit includes a tristate output buffer circuit having an output terminal connected to the predetermined external terminal, an input buffer circuit having an input terminal connected to the predetermined external terminal, and a predetermined external terminal connected to the interface unit. And a terminal state setting circuit for selectively setting the external terminal to a pull-up, pull-down, open, or previous value holding state. The non-volatile storage unit has an area for storing a non-volatile execution address register (243) that sequentially holds instruction address information for capturing a current execution instruction address by the data processing unit. Further, the nonvolatile storage unit is configured to associate a state designation code of an external terminal with a cause of occurrence of a predetermined event assumed during execution of a program in the range for each program address range executed by the data processing unit. It has an area for storing a lookup table (244) and a second lookup table (241) of control data using the state designation code as a search key. The data processing unit acquires a state designation code from the first lookup table based on instruction address information of the execution address register and a cause of occurrence of the predetermined event when a predetermined event occurs, and the obtained state designation code Is used to read control data from the second look-up table. The interface control unit controls the tri-state output buffer circuit and the terminal state setting circuit according to the read control data to determine the state of the predetermined external terminal.

  The semiconductor device according to item 18 is different from the semiconductor device according to item 7 in that the data processing unit searches the first and second lookup tables based on the instruction address. Therefore, the nonvolatile storage unit does not need to have a search function of the first lookup table by the instruction address and a search function of the second lookup table by the state designation code, and can deal with the software processing by diverting the data processing unit. I can do it. Therefore, it is assumed that the soundness of the data processing unit is ensured even when a predetermined event occurs, and it is not possible to deal with the occurrence of an event that makes the data processing of the data processing unit completely impossible due to the occurrence of the predetermined event. . About the other point, there exists an effect similar to item 7.

[19] <Execution address register configured with MRAM>
In the semiconductor device of item 18, the execution address register is MRAM.

  The instruction address can be rewritten at high speed in synchronization with the instruction execution cycle.

[20] <Set the terminal state by setting the tristate output buffer to HiZ>
In the semiconductor device according to Item 18, the interface control unit sets the terminal state setting circuit in a pull-up, pull-down, open, or previous value holding state by setting the tristate output buffer to high impedance according to the control data. The state of a predetermined external terminal is determined.

  In any state of the tri-state output buffer when a predetermined event occurs, the external input / output terminal can be readily stabilized to the state indicated by the control data.

[21] <Setting of terminal state according to power supply voltage drop>
In the semiconductor device according to Item 18, when the generation factor of the predetermined event is a change of a power supply voltage detected by a power supply detector to a predetermined voltage or less, the data processing unit causes the change to the predetermined voltage or less. The state designation code corresponding to the value of the execution address register and the factor at that time is acquired from the first look-up table. Then, the control data is read from the second look-up table using the acquired state designation code and output to the interface unit.

  The state of the predetermined external terminal can be set as desired in response to the change of the power supply voltage to a predetermined voltage or less.

[22] <Pin state setting according to predetermined interrupt factor or exception factor>
In the semiconductor device according to Item 18, when the generation factor of the predetermined event is a predetermined interrupt factor or an exception factor, the data processing unit performs the interrupt processing by the predetermined interrupt factor or the exception processing by the predetermined exception factor. The state designation code corresponding to the execution address register value and the factor is obtained from the first lookup table. Then, the control data is acquired from the second look-up table using the acquired state designation code and output to the interface unit.

  The state of the predetermined external terminal can be set as desired in response to occurrence of a predetermined interrupt factor or exception factor.

[23] <System for setting external terminals according to data processing state at the time of occurrence of abnormality>
A data processing system according to still another embodiment of the present invention includes a first semiconductor device (100, 300) that performs data processing, and a second semiconductor device (500) that is connected to the first semiconductor device and receives control thereof. To 502). The first semiconductor device stores in advance a control data for controlling a terminal state of a predetermined input / output terminal in accordance with a state for each processing of the data processing when an abnormality occurs in the nonvolatile memory unit, A search key for specifying the control data is sequentially set in the nonvolatile memory unit for each processing. When the abnormality occurs, the first semiconductor device sets a state of a predetermined input / output terminal to a pull-up, pull-down, high impedance, or previous value holding state according to control data referred to based on the search key. To do. The second semiconductor device receives a state of a required terminal among the predetermined input / output terminals by an input circuit to determine an internal state, and the first semiconductor device includes a required terminal among the predetermined input / output terminals. Is received by the input circuit to determine the internal state.

  Thereby, the first semiconductor device can fix the state of the external terminal in a programmable manner in accordance with the data processing status to be executed. Therefore, the state of the second semiconductor device connected to the external terminal of the first semiconductor device, and further, the first semiconductor device according to the abnormality recognized by the first semiconductor device and the program being executed by the semiconductor device at that time It is possible to control its own state to a required state, and it is possible to programmably determine the state of the data processing system when an abnormality occurs.

[24] <System for setting external terminals according to the cause of occurrence of an abnormality and the execution program address>
A data processing system according to still another embodiment of the present invention includes a first semiconductor device (200, 400) that performs data processing, and a second semiconductor device (600) that is connected to the first semiconductor device and receives control thereof. 606). When an abnormality occurs, the first semiconductor device controls a terminal state of a predetermined input / output terminal according to a program range of the data processing and a generation factor of a predetermined event assumed during execution of the program in the range. The control data for storing the control data is stored in advance in the nonvolatile memory unit, and a search key for specifying the control data is sequentially set in the nonvolatile memory unit as data processing proceeds. When the abnormality occurs, the state of a predetermined input / output terminal is set to a pull-up, pull-down, high impedance, or previous value holding state according to control data referred to based on the search key. The second semiconductor device receives a state of a required terminal among the predetermined input / output terminals by an input circuit to determine an internal state, and the first semiconductor device is a state of the required terminal among the predetermined input / output terminals. Is received by the input circuit to determine the internal state.

  Control for controlling the terminal state of a predetermined input / output terminal according to not only the processing state of the data processing but also the type of abnormality when the abnormality occurs in the first semiconductor device with respect to the data processing system according to Item 23. The difference is that the data is stored in the non-volatile memory section. Because of the difference, the state of the external terminal can be set more finely than the item 23.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 illustrates a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. The semiconductor device receives the external power supply voltage Vext and the ground voltage Vss as an operating power supply.

  The semiconductor device 100 is configured as a data processing device having a program processing function such as a system-on-chip system LSI or a microcomputer. The core logic (CRLGC) 101 as a data processing unit of the semiconductor device 100 is not particularly limited, but a CPU (central processing unit) that executes instructions, an accelerator that bears a part of data processing functions that can be processed by the CPU, and a CPU RAM used as a work area, and peripheral circuits of a CPU such as a timer and a DMAC (direct memory access controller). The CPU of the core logic 101 fetches and executes an instruction from the program memory 102 connected via the memory bus 103.

  FIG. 1 typically illustrates one external interface unit (EXIF) 105. A corresponding external terminal 106 is connected to the external interface unit 105. The external interface unit 105 includes a tristate output buffer circuit 110 having an output terminal connected to a corresponding external terminal 106, an input buffer circuit 111 having an input terminal connected to the external terminal 106, a terminal state setting circuit 112, and a tristate. An enable signal generation circuit 113 of the output buffer circuit 110 is provided.

  The terminal state setting circuit 112 is connected to the external terminal 106 and selectively sets the external terminal 106 in a pull-up, pull-down, open, or previous value holding state via the selection switch 120. The pull-up state is achieved by connecting the external terminal 106 to the power supply voltage Vext with the selection switch 120. The pull-down state is achieved by connecting the external terminal 106 to the ground voltage Vss with the selection switch 120. The open state is achieved by connecting the external terminal 106 to the floating node NC with the selection switch 120. The pre-holding state is achieved by connecting the external terminal 106 to the static latch SLAT with the selection switch 120. When the tri-state output buffer circuit 110 is enabled for output, the selection switch 120 selects the open state. When the external terminal 106 is set to a pull-up, pull-down, open, or previous value holding state by the terminal state setting circuit 112, the tri-state output buffer circuit 110 is set to a high impedance state.

  The enable signal generation circuit 113 sets the output enable signal 122 to the high level via the selection switch 121 when enabling the output operation of the tristate output buffer circuit 110, and outputs the enable signal via the selection switch 121 when disabling the output operation. 122 is set to the low level.

  The interface control unit (IFCNT) 132 generates a switch control signal 130 for the selection switch 120 and a switch control signal 131 for the selection switch 121. The switch logic instruction to the interface control unit 132 is given by the core logic 101 or the nonvolatile storage unit 140. When the power-on reset or the system reset is canceled, the core logic 101 causes the terminal state setting circuit 112 to select the floating node NC by the switch control signal 131. When an output operation is performed from the external terminal 106 by a data processing operation according to a program stored in the program memory 102, a state in which an output operation by the tristate output buffer circuit 110 can be performed in the enable signal generation circuit 113 by a switch control signal 130. Let them choose. When performing the input operation, the enable signal generation circuit 113 is made to select the high impedance state of the tristate output buffer circuit 110 by the switch control signal 130. It should be understood that the external interface unit 105, the external terminal 106, and the interface control unit 132 are arranged as many as necessary for the semiconductor device 100, although not specifically illustrated.

  The nonvolatile storage unit 140 stores and reads out control data for regulating the state of the external terminal 106 to a predetermined state when occurrence of a predetermined event is detected in the semiconductor device. The configuration will be described in detail below.

  The nonvolatile storage unit 140 is mainly configured by an electrically rewritable nonvolatile memory, and a lookup table 141 and a state designation code register (ICREG) 143 are stored in the nonvolatile memory area, and erasing and writing are performed on them. A timing controller (TMGCNT) 142 for performing control and reading control of stored information is provided.

  The lookup table 141 stores a plurality of control data using a state designation code for designating the state of an external terminal represented by 106 as a search key. The state designation code is determined in advance assuming the internal state of the core logic 101 and further the other state of the semiconductor device 100. Here, such a state to be assumed is not only a state such as an interrupt or an exception caused by data processing by the core logic 101 but also a specific signal 151 input from the outside via the external input terminal 150. This is a state (for example, an interrupt generation state caused by an external interrupt request) that occurs inside the core logic 101 when notified. The state generated inside the core logic 101 by being notified by the detection signal 153 of the undesired level drop of the external power supply voltage Vext by the power supply detector (LVD) 152 is also considered. The state designation code is assigned to each internal state. In FIG. 1, state 1, state 2,... Mean a state designation code, and control data D11, D12,... Corresponding to terminal 1, terminal 2,. For example, the control data of the external terminal 106 is D11 when in state 1 and D21 when in state 2. The look-up table 141 may be written by the CPU in response to reset release from the outside and written to the nonvolatile memory unit 140 via the memory bus 103, or written in advance at the semiconductor device manufacturing stage. You may make it rewrite according to it.

  A status designation code is written in the status designation code register (ICREG) 143 via the memory bus 103 in accordance with a program executed by the CPU. For example, assuming a case where a program is executed in an event-driven manner, each time the execution of each program corresponding to an event starts, a status designation code for dealing with an abnormality that is expected to occur in each program execution Write to the specified code register 143. When the core logic 101 detects the occurrence of a predetermined internal state by executing a program, notification from the outside, notification of power supply voltage drop, etc., the detection signal 155 is given to the timing controller 142. In response to this, the timing controller 142 searches the look-up table 141 for control data in a state matching the state specification code set in the state specification code register 143 at that time, and searches the control data corresponding to the corresponding interface control. To part 132. Thus, the interface control circuit 132 sets the tristate output buffer circuit 110 to high impedance according to the given control data, and then pulls up, pulls down, high impedance, or the previous value of the corresponding external terminal 106 by the terminal state setting circuit 112. Set the hold status.

  FIG. 2 illustrates the operation timing of the nonvolatile memory unit 140 accompanying the data processing operation of the semiconductor device 100.

  Here, it is assumed that the CPU of the core logic 101 executes the programs A, B, and C in this order. When executing the program A, the CPU writes a state designation code corresponding to the state 1 to the state designation code register (ICREG) 143 via the memory bus 103 at the head (S1). Here, the state 1 is a state designation code corresponding to a predetermined event (occurrence of a predetermined abnormality) assumed to occur during the execution of the program A. Following this, the CPU continues to execute the program A. For example, when an interrupt (INT1) is generated, the CPU performs a save operation and transitions to the execution of the program B.

  When executing the program B, the CPU transfers the state designation code corresponding to the state 2 to the state designation code register (ICREG) 143 via the memory bus 103 and rewrites it (S2). Here, state 2 is a state designation code corresponding to a predetermined event (occurrence of a predetermined abnormality) assumed to occur during execution of program B. Following this, the CPU continues to execute the program B, and returns to the original execution state of the program A when the execution is completed.

  When returning to the execution state of the program A, the CPU transfers the state designation code corresponding to the state 1 to the state designation code register (ICREG) 143 via the memory bus 103 and rewrites it (S3). When the CPU completes execution of the program A, the CPU proceeds to execution of the next program C.

  When the program C is executed, the CPU transfers the state designation code corresponding to the state 3 to the state designation code register (ICREG) 143 via the memory bus 103 and rewrites the program C (S4). Here, the state 3 is a state designation code corresponding to a predetermined event (occurrence of a predetermined abnormality) assumed to occur during the execution of the program C. Following this, the CPU continues to execute program C. If an abnormality corresponding to the state 3 occurs on the way (S5), the nonvolatile storage unit 140 gives control data of each terminal corresponding to the state 3 to the corresponding interface control unit 132, and the interface control unit 132 responds according to the control data. The state of the external terminal 106 to be fixed is fixed to a state of pull-up, pull-down, high impedance, or previous value holding via the interface circuit 105 (S6).

  FIG. 3 illustrates a data processing system using the semiconductor device 100. Another semiconductor device (IC1, IC2, IC3) 500, 501, 502 is connected to the semiconductor device (LSI) 100 via its external terminal. In the figure, each of IO0 to IO7 means an interface circuit corresponding to an external terminal of the semiconductor device 100. A semiconductor device (LSI) 100 inputs and outputs signals to and controls other semiconductor devices 500, 501, and 502. In particular, the semiconductor device (IC2) 501 is a reset IC.

  FIG. 4 illustrates the operation timing of the data processing system of FIG. Here, a case where another semiconductor device inputs a state of an external terminal whose state is fixed by occurrence of a predetermined event and determines its operation mode is illustrated.

  At time t0, the CPU writes a state designation code corresponding to the state x in the state designation code register (ICREG) 143 and executes a program, for example, a program with a large amount of calculation. During execution of the program, an error corresponding to the state x is generated in the CPU at time t1, and the state of the CPU becomes unstable. In the stable state of the CPU up to time t1, the semiconductor device (IC1) 500 and the semiconductor device (IC3) 502 perform predetermined operations, and the semiconductor device (IC2) 501 outputs a reset signal in a reset release state. . When an error occurs at time 1, the semiconductor device 100 fixes the external terminals of IO1, IO2, and IO3 to L (low level), H (high level), and H (high level), respectively. The semiconductor device (IC1) 500 that receives this state shifts to the self-diagnosis mode. For example, when the semiconductor device (IC2) 501 receives the diagnosis result, a reset is issued at time t2, whereby the system reset of the semiconductor devices 100, 500, 502 is performed, and the system reset is released at time t3. Thereafter, the semiconductor devices 100, 500 and 502 are allowed to perform predetermined operations. In the example of FIG. 4, it is assumed that the external terminal fixing function due to the occurrence of an error is inactivated for the semiconductor device (IC3) 502.

  FIG. 5 illustrates a data processing system using the semiconductor device 100. The basic configuration is the same as that in FIG. 3, but here, a case where the semiconductor device 100 itself inputs the state of the external terminal whose state is fixed by the occurrence of a predetermined event and defines its state is illustrated. In accordance with this point, the semiconductor device 100 includes a part of the input buffer circuit 111 and the terminal state setting circuit 112 for the external terminals IO5 and IO6.

  FIG. 6 illustrates the operation timing of the data processing system of FIG. Here, the case where the semiconductor device 100 itself inputs the state of the external terminals IO5 and IO6 whose state is fixed by the occurrence of a predetermined event from the input buffer circuit 111 and defines its state is illustrated.

  At time t0, the CPU writes a state designation code corresponding to the state x in the state designation code register (ICREG) 143 and executes a program, for example, a program with a large amount of calculation. During execution of the program, an error corresponding to the state x is generated in the CPU at time t1, and the state of the CPU becomes unstable. In the stable state of the CPU up to time t1, the semiconductor device (IC1) 500 and the semiconductor device (IC3) 502 perform predetermined operations, and the semiconductor device (IC2) 501 outputs a reset signal in a reset release state. . When an error occurs at time 1, the semiconductor device 100 fixes the external terminals of IO1, IO2, and IO3 to L (low level), H (high level), and H (high level), respectively, and the external terminal of IO5. Pre-up is performed and the external terminal of IO6 is fixed to pull-down. The semiconductor device (IC1) 500 that receives this state shifts to the self-diagnosis mode. The semiconductor device (IC3) 502 sets the external terminals corresponding to IO5 and IO6 to high impedance, while the semiconductor device (LSI) 100 causes the input from the external terminals corresponding to IO5 and IO6 to the input buffer circuit 111 to be floating. The internal state is maintained while suppressing indefiniteness by itself. During this time, when the semiconductor device (IC2) 501 receives a diagnosis result from the semiconductor device (IC1) 500, a reset is issued at time t2, thereby system resetting of the semiconductor devices 100, 500, 502 is performed, and at time t3, the system is reset. After the reset is released, the semiconductor devices 100, 500, and 502 are allowed to perform predetermined operations thereafter.

  According to the first embodiment, the following operational effects are obtained.

  (1) A lookup table 141 is prepared, and a state designation code is stored in advance in the state designation code register 143 according to data processing by the core logic 101. When an abnormality occurs, the lookup table 141 is stored using the state designation code. Since it refers, the state of the external terminal can be set in a programmable manner in accordance with the data processing status to be executed. In particular, since the non-volatile storage unit 140 autonomously searches the lookup table 141 and supplies the searched control data to the input / output control circuit 132, the processing is performed in accordance with the soundness of the core logic 101 when a predetermined event occurs. There is no need to secure it. Therefore, depending on the abnormality recognized by the semiconductor device 100 and the program currently being executed by the semiconductor device 100, the states of the circuits 500, 501, and 502 connected to the external terminal 106 of the semiconductor device 100, and further the semiconductor The state of the apparatus 100 itself can be controlled to a required state.

  (2) Since the state designation code corresponding to the occurrence of a predetermined event corresponding to each program to be executed or processing only needs to be first written in the nonvolatile state designation code register 143, a preset state designation code is used to generate a predetermined event. It is possible to prevent the occurrence of a situation that is lost or changed depending on the time.

  (3) The core logic 101 only has to bear the operation of writing the state designation code at the time of occurrence of a predetermined event corresponding to each program or process to be executed in the state designation code register 143.

  (4) The state of the predetermined external terminal is determined by setting the tristate output buffer 110 to high impedance according to the control data and setting the terminal state setting circuit 112 to a pull-up, pull-down, open, or previous value holding state. When the predetermined event occurs, it becomes easy to stabilize the external input / output terminal 106 to the state indicated by the control data, regardless of the state of the tri-state output buffer 110.

  (5) Not only the change of the power supply voltage detected by the power supply detector 152 to a predetermined voltage or less, the occurrence of a predetermined interrupt factor or exception factor, but also the power supply rise detection, the PLL circuit is unlocked, and the oscillation stop detection of crystal oscillation The state of the external terminal can be set programmably according to the type of abnormality such as.

  (6) By adopting a high-speed rewritable storage format such as MRAM in the non-volatile storage unit, the number 100 required for the flash memory to rewrite the state designation code every time the processing program changes. There is no need to spend time such as microseconds. Therefore, it is also suitable for a system that requires real-time characteristics.

<< Embodiment 2 >>
FIG. 7 illustrates a semiconductor device according to the second embodiment of the present invention. The semiconductor device 200 shown in the figure is different from that shown in FIG. 1 in the configuration of the nonvolatile memory unit and the control method.

  The semiconductor device 200 is configured as a data processing device having a program processing function such as a system-on-chip system LSI or a microcomputer. The core logic (CRLGC) 201 as a data processing unit of the semiconductor device 200 is not particularly limited, but a CPU (central processing unit) that executes instructions, an accelerator that bears a part of data processing functions that can be processed by the CPU, and a CPU RAM used as a work area, and peripheral circuits of a CPU such as a timer and a DMAC (direct memory access controller). The CPU of the core logic 201 fetches and executes an instruction from the program memory 102 connected via the memory bus 103.

  FIG. 7 typically illustrates one external interface unit (EXIF) 105. A corresponding external terminal 106 is connected to the external interface unit 105. The configuration of the external interface unit 105 is the same as that shown in FIG. The interface control unit (IFCNT) 132 that controls the external interface unit 105 is also configured in the same manner as in FIG. The switch logic instruction to the interface control unit 132 is given by the core logic 201 or the nonvolatile storage unit 240. When the power-on reset or the system reset is canceled, the core logic 201 causes the terminal state setting circuit 112 to select the floating node NC by the switch control signal 131. When an output operation is performed from the external terminal 106 by a data processing operation according to a program stored in the program memory 102, a state in which an output operation by the tristate output buffer circuit 110 can be performed in the enable signal generation circuit 113 by a switch control signal 130. Let them choose. When performing the input operation, the enable signal generation circuit 113 is made to select the high impedance state of the tristate output buffer circuit 110 by the switch control signal 130. It should be understood that the external interface unit 105, the external terminal 106, and the interface control unit 132 are arranged as many as necessary for the semiconductor device 100, although not specifically illustrated.

  The nonvolatile storage unit 240 stores and reads out control data for restricting the state of the external terminal 106 to a predetermined state when occurrence of a predetermined event is detected in the semiconductor device. The configuration will be described in detail below.

  The nonvolatile storage unit 240 is mainly configured by an electrically rewritable nonvolatile memory. The nonvolatile memory area includes a first lookup table 244, a second lookup table 241, and an execution address register (EAREG) 243. A timing controller (TMGCNT) 242 for storing, erasing and writing control for them, and reading control of stored information is provided.

  For each program address range executed by the core logic 201 as the data processing unit, the first look-up table 244 corresponds to an external terminal state designation code corresponding to a predetermined event occurrence factor assumed during execution of a program in the range. It is a table attached. The predetermined event assumed during the execution of the program is determined by assuming the internal state of the core logic 201 and further the other state of the semiconductor device 200. Here, such a state to be assumed is not only a state such as an interrupt or an exception caused by data processing by the core logic 201 but also a specific signal 151 input from the outside via the external input terminal 150. This is a state that occurs inside the core logic 201 by being notified (for example, an interrupt generation state due to an external interrupt request). In addition, a state generated in the core logic 201 by being notified by an undesired level decrease detection signal 153 of the external power supply voltage Vext by the power supply detector (LVD) 152 is also considered. Here, factors such as interrupts and exceptions are assumed as the occurrence factors of the predetermined event. The program address range to be executed can be specified by, for example, a start address and an end address, or by a start address and a program size. In FIG. 7, the first look-up table 244 shows abnormal factors such as interrupts and exceptions that are expected to occur during the execution of each program specified by the start address (SA) and end address (E) of the program. Holds the state specification code according to the corresponding internal state. In the figure, state designation codes are illustrated as state 1, state 8, and state 3.

  The second lookup table 241 is configured in the same manner as the lookup table 141, and stores a plurality of control data using a state designation code for designating the state of the external terminal as a search key. In the figure, state 1, state 2,... Mean a state designation code, and control data D11, D12,... Corresponding to terminal 1, terminal 2,. For example, the control data of the external terminal 106 is D11 when in state 1 and D21 when in state 2.

  The look-up tables 241 and 244 may be written by the CPU in response to reset release from the outside and written to the nonvolatile memory unit 240 via the memory bus 103, or written in advance during the manufacturing stage of the semiconductor device. You may make it rewrite as needed.

  The execution address register (EAREG) 243 is a non-volatile register that sequentially holds instruction address information for capturing the current execution instruction address by the CPU of the core logic 201. For example, the address of an instruction executed by the CPU, for example, the value of the program counter of the CPU is directly given to the execution address register 243 from the dedicated signal line 257 and written in the execution address register 243. It is also possible to write via the memory bus 103. Therefore, since it is necessary to write the execution address to the execution address register 243 at a high speed with respect to the instruction execution cycle of the CPU, the nonvolatile memory unit 240 has a higher write access speed like the MRAM than the flash memory. It is a good idea to use memory. The execution address stored in the execution address register 243 can be limited to upper address information that can identify the boundary address of the program.

  When the core logic 201 detects the occurrence of a predetermined internal state by executing a program, notification from the outside, notification of power supply voltage drop, etc., the core logic 201 gives the detection signal 255 and the cause of occurrence of the internal state 256 to the timing controller 242. In response to this, the timing controller 242 refers to the state entry in the program address range including the instruction address set in the execution address register 243 at that time from the first lookup table 244, and from among the state entries, Extract the status specification code corresponding to the cause of the error. Further, the timing controller 242 searches the second look-up table 241 for control data in a state that matches the extracted state designation code, and provides the searched control data to the corresponding interface control unit 132. Thus, the interface control circuit 132 sets the tristate output buffer circuit 110 to high impedance according to the given control data, and then pulls up, pulls down, high impedance, or the previous value of the corresponding external terminal 106 by the terminal state setting circuit 112. Set the hold status.

  FIG. 8 illustrates an operation timing using the nonvolatile storage unit 140 accompanying the data processing operation of the semiconductor device 200.

  Here, it is assumed that the CPU of the core logic 201 executes the programs A, B, and C in this order. The execution address register 243 of the nonvolatile memory unit 240 sequentially receives and holds the address of the instruction currently executed by the CPU. Therefore, as described in the first embodiment, the CPU does not need to write the status designation code corresponding to the status designation code register 143 at the beginning of the program. When an abnormality occurs during the execution of the program C, for example, a power supply abnormality, the interrupt factor corresponding to the abnormality and the occurrence of the abnormality are notified to the timing controller 242, so that the first lookup table is determined by the address information held by the execution address register 243 at that time. The state designation code is acquired by referring to 244, and thereby, control data is supplied from the second lookup table 241 to the interface control unit 132. As a result, the interface control unit 132 fixes the state of the corresponding external terminal 106 to a state of pull-up, pull-down, high impedance, or previous value holding via the interface circuit 105 according to the control data.

  FIG. 9 illustrates a data processing system using the semiconductor device 200. The semiconductor device 200 is a master microcomputer, and a reset IC 600, a communication destination microcomputer 601, a sensor 602, a sensor 603, a peripheral IC 604, a sub-microcomputer 605, and a power supply IC 606 are connected as other semiconductor devices through its external terminals.

  For example, when the master microcomputer runs out of control in this data data processing system, the state of the external terminals of the master microcomputer 200 is fixed programmably to the circuit connected thereto depending on the program being operated and the operating state. The operation will be described as an example. For example, when the master microcomputer 200 goes out of control in a certain operating state, a reset issue flag is supplied to the reset IC 600 (I1), a self-diagnosis and power return command is issued to the power supply IC 606 (I2), and the peripheral IC 604 is given. A case is assumed where the current status is instructed (I3). At this time, the first lookup table 244 has the storage information of FIG. 10, and the second lookup table 241 has the storage information of FIG. In FIG. 10, state 2 is set in the state designation code when a reset exception is caused as an abnormality in the address range A2 to A3. In FIG. 11, Hiz, Pull-up, Pull-Down,..., Pull-Down are set in the control data of the external terminals PA0 to Pxx in the state 2. The external terminal PA1 is assigned as an output terminal for a reset issuance flag, the external terminal PA2 is assigned as an output terminal for a self-diagnosis and power recovery instruction, and Pxx is assigned as an instruction terminal for maintaining the current status for the peripheral IC 604. When the master microcomputer 200 is executing a program in the address range of A2 to A3, if a reset exception occurs, for example, reset is performed according to the stored information in the first lookup table 244 in FIG. 10 and the second lookup table 241 in FIG. A reset issuance flag is supplied to the IC 600 (I1), and a self-diagnosis and power restoration command is issued to the power supply IC 606 (I2). As a result, the states of the external terminals PA1, PA2, and PAxx necessary for instructing the peripheral IC 604 to maintain the current state (I3) are generated.

  According to the second embodiment, the following operational effects are obtained.

  First and second look-up tables 244 and 241 are prepared in the nonvolatile memory unit 240 in advance, and the information in the execution address register 240 is rewritten to the address information of the execution address as data processing progresses. Since the first and second lookup tables 244 and 241 are referred to based on the execution address information, the state of the external terminal 106 can be set to be programmable according to the data processing status to be executed. In particular, the control data can be specified based on the program address, and the control data is referred to using the two look-up tables 244 and 241. Therefore, it is possible to more flexibly set the state of the external terminal. it can. In particular, since the nonvolatile storage unit 240 autonomously performs the search of the control data using the first and second look-up tables 244 and 241 and the supply of the searched control data to the input / output control circuit 132. Similar to 1, the process does not require ensuring the soundness of the data processing unit when a predetermined event occurs. Therefore, depending on the abnormality recognized by the semiconductor device 200 and the program being executed by the semiconductor device 100 at that time, the state of the peripheral circuits 600 to 606 connected to the external terminal 106 of the semiconductor device 100 and further the semiconductor device 100 It is possible to control its own state to a required state.

  In addition, the same effects as those of the first embodiment are obtained.

<< Embodiment 3 >>
FIG. 12 illustrates a semiconductor device 300 according to the third embodiment of the invention. The difference from the first embodiment is that, when a predetermined event occurs, the reference subject of the lookup table 141 using the address information of the state designation code register 143 is the core logic 101A. Since it is not necessary for the nonvolatile storage unit 140A to make such a reference autonomously, it is not necessary to provide the nonvolatile memory unit 140A with the predetermined event detection signal 155 in the first embodiment. The internal timing control of the nonvolatile storage unit 140A is performed by the timing controller 142A. For example, when a predetermined event such as an interrupt or an exception occurs, the core logic 101A reads the address information of the state designation code register 143 via the memory bus 103, and responds from the lookup table 141 using the read address information. Control data to be read out. In the figure, the read data is directly supplied from the lookup table 141 to the interface control unit 132. However, the present invention is not limited to this, and the core logic may read the control data and supply it to the interface control unit 132. Since other configurations are the same as those of the first embodiment, detailed description thereof is omitted.

  Since the semiconductor device 300 uses the core logic 101A to search the lookup table 141 based on the state designation code, the nonvolatile storage unit 140A does not need to have a lookup function for the lookup table 141 based on the state designation code. Can be handled by software processing. Therefore, it is assumed that the soundness of the core logic 101A is ensured even when a predetermined event occurs, and it is possible to cope with the occurrence of an event in which the data processing of the core logic 101A is completely disabled by the occurrence of the predetermined event. Can not. About the other point, there exists an effect similar to Embodiment 1. FIG.

<< Embodiment 4 >>
FIG. 13 illustrates a semiconductor device 400 according to the fourth embodiment of the present invention. The difference from the second embodiment is that the core logic 201A is the reference entity of the lookup tables 244 and 241 using the address information of the execution address register 243 when a predetermined event occurs. Since it is not necessary for the nonvolatile storage unit 240A to make such a reference autonomously, it is not necessary to provide the nonvolatile storage unit 240A with the predetermined event detection signal 255 and its generation factor 256 in the second embodiment. The timing controller 242A performs internal timing control of the nonvolatile storage unit 240A. For example, when a predetermined event such as an interrupt or an exception occurs, the core logic 201A reads the address information of the execution address register 243 via the memory bus 103, and uses the read address information from the first lookup table 244. The corresponding state designation code is read, and the control data is read from the second lookup table 241 and controlled using the read state designation code. In the figure, the read control data is directly supplied from the second lookup table 241 to the interface control unit 132. However, the present invention is not limited to this, and the core logic 201A reads the control data and supplies it to the interface control unit 132. May be. Since other configurations are the same as those of the first embodiment, detailed description thereof is omitted.

  Compared to the semiconductor device 200 of the second embodiment, the semiconductor device 400 searches the first and second lookup tables 244 and 241 based on the instruction address by the core logic 201A. It is not necessary to provide the search function of the first lookup table 244 and the search function of the second lookup table 241 based on the state designation code, and the core logic 201A can be used to cope with the software process. Therefore, it is assumed that the soundness of the core logic 201A is ensured even when a predetermined event occurs, and it is possible to cope with the occurrence of an event in which the data processing of the core logic 201A is completely disabled by the occurrence of the predetermined event. Can not. About the other point, there exists an effect similar to Embodiment 2. FIG.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the occurrence of a predetermined event serving as a trigger for setting the state of the external terminal is not limited to the above-described power-down detection, power-up detection, PLL lock-off, crystal oscillation stop detection, etc., and can be changed as appropriate.

  The setting mode for setting the state of the external terminal is not limited to the fixed level, but the voltage level of the external terminal is set so as to form a predetermined signal waveform periodically, such as H → L → H →... It may be changed.

  The nonvolatile memory portion is not limited to an MRAM that can achieve an access speed comparable to that of an on-chip SRAM formed by a CMOS process, but is mainly an electrically rewritable nonvolatile memory such as flash memory or EEPROM. It is also possible to configure as.

  In the second and fourth embodiments, the address information of the execution instruction written in the execution address register 243 is not limited to the case where the address information is directly supplied from the core logic to the register 243, and may be performed via the timing controller 242.

100 Semiconductor device Vext External power supply voltage Vss Ground voltage 101 Core logic (CRLGC)
103 Memory Bus 102 Program Memory 105 External Interface Unit (EXIF)
106 External terminal 110 Tri-state output buffer circuit 111 Input buffer circuit 113 Enable signal generation circuit 122 Output enable signal 122 is set to high level, and when output operation is disabled, output enable signal 122 is set to low level via selection switch 121 .

132 Interface control unit (IFCNT)
130, 131 Switch control signal 140 Non-volatile storage unit 102 Program memory 141 Look-up table 143 State designation code register (ICREG)
142 Timing Controller (TMGCNT)
155 Detection signal 200 Semiconductor device 201 Core logic (CRLGC)
240 Non-volatile storage unit 244 First lookup table 241 Second lookup table 243 Execution address register (EAREG)
242 Timing controller (TMGCNT)
255 Detection Signal 256 Internal State Occurrence Factor 300 Semiconductor Device 101A Core Logic 140A Nonvolatile Storage Unit 142A Timing Controller 400 Semiconductor Device 201A Core Logic 240A Nonvolatile Storage Unit 242A Timing Controller

Claims (24)

A plurality of external terminals;
An interface unit connected to the external terminal;
An interface control unit for controlling the interface unit;
A data processing unit that performs processing of an input signal input from the interface control unit, generation of an output signal output from the interface unit, and other data processing;
A non-volatile storage unit connected to the data processing unit,
The interface unit includes a tristate output buffer circuit having an output terminal connected to the predetermined external terminal, an input buffer circuit having an input terminal connected to the predetermined external terminal, and a predetermined external terminal connected to the interface unit. A terminal state setting circuit for selectively setting an external terminal to a pull-up, pull-down, open, or previous value holding state;
The non-volatile storage unit has an area for storing a control data look-up table using a state designation code for designating the state of the external terminal as a search key, and the state is stored in advance according to data processing by the data processing unit. When the designation code is stored and the occurrence of a predetermined event is notified from the data processing unit, the control data is read from the lookup table using the state designation code stored in advance,
The interface control unit controls the tristate output buffer circuit and the terminal state setting circuit according to the read control data to determine the state of the predetermined external terminal.   The nonvolatile storage unit has a nonvolatile state designation code register in which the state designation code can be written by the data processing unit, and when the occurrence of a predetermined event is notified from the data processing unit, the state designation code register The semiconductor device according to claim 1, wherein the control data retrieved from the lookup table using the state designation code is output to the interface unit.   3. The semiconductor device according to claim 2, wherein the data processing unit writes a required state designation code in the state designation code register in advance at the beginning of the data processing as part of the data processing.   The interface control unit sets the state of the predetermined external terminal by setting the terminal state setting circuit in a state of pulling up, pulling down, opening, or holding a previous value by setting the tristate output buffer to high impedance according to the control data. The semiconductor device according to claim 3, which is determined. The predetermined event is a change of the power supply voltage detected by the power supply detector to a predetermined voltage or lower,
The non-volatile storage unit, when notified from the data processing unit that the power supply voltage is changed to a predetermined voltage or less, uses the state designation code stored in the state designation code register to retrieve the control The semiconductor device according to claim 3, wherein data is output to the interface unit. The predetermined event is a predetermined interrupt factor or exception factor,
The non-volatile storage unit, when notified of occurrence of the predetermined interrupt factor or exception factor from the data processing unit, the control retrieved from a lookup table using a state designation code held by the state designation code register The semiconductor device according to claim 3, wherein data is output to the interface unit. A plurality of external terminals;
An interface unit connected to the external terminal;
An interface control unit for controlling the interface unit;
A data processing unit that performs processing of an input signal input from the interface control unit, generation of an output signal output from the interface unit, program processing for executing an instruction, and other data processing;
A non-volatile storage unit connected to the data processing unit,
The interface unit includes a tristate output buffer circuit having an output terminal connected to the predetermined external terminal, an input buffer circuit having an input terminal connected to the predetermined external terminal, and a predetermined external terminal connected to the interface unit. A terminal state setting circuit for selectively setting an external terminal to a pull-up, pull-down, open, or previous value holding state;
The nonvolatile storage unit sequentially stores instruction address information for capturing the current execution instruction address by the data processing unit, and for each program address range executed by the data processing unit, A first lookup table in which a state designation code of an external terminal is associated with an occurrence factor of a predetermined event assumed during execution of a program in the range, and a second lookup of control data using the state designation code as a search key A table, and when the occurrence of a predetermined event is notified from the data processing unit, from the first lookup table based on the instruction address information of the execution address register and the occurrence factor of the predetermined event Obtaining the state designation code and using the obtained state designation code, the second lookup table Given to the interface control unit reads the control data from the le,
The interface control unit determines the state of the predetermined external terminal by controlling the tri-state output buffer circuit and the terminal state setting circuit according to given control data.   The semiconductor device according to claim 7, wherein the execution address register is an MRAM.   The interface control unit sets the state of the predetermined external terminal by setting the terminal state setting circuit in a state of pulling up, pulling down, opening, or holding a previous value by setting the tristate output buffer to high impedance according to the control data. The semiconductor device according to claim 7, which is determined. The occurrence factor of the predetermined event is a change of the power supply voltage detected by the power supply detector to a predetermined voltage or lower,
When the occurrence of an interrupt factor due to a change below the predetermined voltage is notified from the data processing unit, the nonvolatile memory unit receives the value of the execution address register and the state designation code corresponding to the factor. 8. The semiconductor device according to claim 7, wherein the semiconductor device is obtained from a lookup table, and control data is obtained from the second look-up table using the obtained state designation code and output to the interface unit. The occurrence factor of the predetermined event is a predetermined interrupt factor or an exception factor,
When the occurrence of the predetermined interrupt factor or exception factor is notified from the data processing unit, the nonvolatile storage unit first sets the state designation code corresponding to the value of the execution address register and the factor at that time The semiconductor device according to claim 7, wherein the semiconductor device is obtained from a look-up table, and control data is read from the second look-up table using the obtained state designation code and output to the interface unit. A plurality of external terminals;
An interface unit connected to the external terminal;
An interface control unit for controlling the interface unit;
A data processing unit that performs processing of an input signal input from the interface control unit, generation of an output signal output from the interface unit, and other data processing;
A non-volatile storage unit connected to the data processing unit,
The interface unit includes a tristate output buffer circuit having an output terminal connected to the predetermined external terminal, an input buffer circuit having an input terminal connected to the predetermined external terminal, and a predetermined external terminal connected to the interface unit. A terminal state setting circuit for selectively setting an external terminal to a pull-up, pull-down, open, or previous value holding state;
The non-volatile storage unit has an area for storing a lookup table of control data using a state designation code for designating a state of the external terminal as a search key,
The data processing unit stores the state designation code in the nonvolatile storage unit in advance according to data processing, and when the occurrence of a predetermined event is notified, the state designation code stored in the nonvolatile storage unit is stored in advance. Read out the control data from the lookup table,
The interface control unit controls the tristate output buffer circuit and the terminal state setting circuit according to the read control data to determine the state of the predetermined external terminal. The nonvolatile storage unit has a nonvolatile state designation code register in which the state designation code can be written by the data processing unit,
13. The semiconductor device according to claim 12, wherein when the occurrence of a predetermined event is detected, the data processing unit outputs the control data retrieved from the lookup table using the state designation code of the state designation code register to the interface unit. .   14. The semiconductor device according to claim 13, wherein the data processing unit writes a required state designation code in the state designation code register in advance at the beginning of the data processing as part of the data processing.   The interface control unit sets the state of the predetermined external terminal by setting the terminal state setting circuit in a state of pulling up, pulling down, opening, or holding a previous value by setting the tristate output buffer to high impedance according to the control data. The semiconductor device according to claim 14, which is determined. The predetermined event is a change of the power supply voltage detected by the power supply detector to a predetermined voltage or lower,
When the data processing unit determines the change of the power supply voltage to a predetermined voltage or less by the output of the power supply detector, the control data retrieved from the lookup table using the state designation code held by the state designation code register is obtained. The semiconductor device according to claim 14, wherein the semiconductor device outputs to the interface unit. The predetermined event is a predetermined interrupt factor or exception factor,
The data processing unit is configured to retrieve the control data retrieved from a look-up table using a state designation code stored in the state designation code register by an interrupt process by the predetermined interrupt factor or an exception process by a predetermined exception factor. 15. The semiconductor device according to claim 14, wherein A plurality of external terminals;
An interface unit connected to the external terminal;
An interface control unit for controlling the interface unit;
A data processing unit that performs processing of an input signal input from the interface control unit, generation of an output signal output from the interface unit, program processing for executing an instruction, and other data processing;
A non-volatile storage unit connected to the data processing unit,
The interface unit includes a tristate output buffer circuit having an output terminal connected to the predetermined external terminal, an input buffer circuit having an input terminal connected to the predetermined external terminal, and a predetermined external terminal connected to the interface unit. A terminal state setting circuit for selectively setting an external terminal to a pull-up, pull-down, open, or previous value holding state;
The nonvolatile storage unit sequentially stores instruction address information for capturing the current execution instruction address by the data processing unit, and for each program address range executed by the data processing unit, A first lookup table in which a state designation code of an external terminal is associated with an occurrence factor of a predetermined event assumed during execution of a program in the range, and a second lookup of control data using the state designation code as a search key A table and an area for storing
The data processing unit acquires a state designation code from the first lookup table based on instruction address information of the execution address register and a cause of occurrence of the predetermined event when a predetermined event occurs, and the obtained state designation code Read control data from the second look-up table using
The interface control unit determines the state of the predetermined external terminal by controlling the tristate output buffer circuit and the terminal state setting circuit according to the read control data.   The semiconductor device according to claim 18, wherein the execution address register is an MRAM.   The interface control unit sets the state of the predetermined external terminal by setting the terminal state setting circuit in a state of pulling up, pulling down, opening, or holding a previous value by setting the tristate output buffer to high impedance according to the control data. The semiconductor device according to claim 18, which is determined. The occurrence factor of the predetermined event is a change of the power supply voltage detected by the power supply detector to a predetermined voltage or lower,
The data processing unit obtains the value of the execution address register at that time and the state designation code corresponding to the factor from the first look-up table by an interrupt process caused by a change to the predetermined voltage or less, The semiconductor device according to claim 18, wherein control data is read from the second look-up table using the acquired state designation code and output to the interface unit. The occurrence factor of the predetermined event is a predetermined interrupt factor or an exception factor,
The data processing unit acquires the value of the execution address register at that time and the state designation code corresponding to the factor from the first look-up table by the interrupt processing by the predetermined interrupt factor or the exception processing by the predetermined exception factor. The semiconductor device according to claim 18, wherein control data is acquired from the second look-up table using the acquired state designation code and output to the interface unit. A data processing system comprising: a first semiconductor device that performs data processing; and a second semiconductor device that is connected to and controlled by the first semiconductor device,
The first semiconductor device stores in advance a control data for controlling a terminal state of a predetermined input / output terminal in accordance with a state for each processing of the data processing when an abnormality occurs in the nonvolatile memory unit, A search key for specifying the control data is sequentially set in the nonvolatile memory unit for each processing, and when the abnormality occurs, the state of a predetermined input / output terminal according to the control data referred to based on the search key Set to pull-up, pull-down, high impedance or hold previous value,
The second semiconductor device receives a state of a required terminal among the predetermined input / output terminals by an input circuit to determine an internal state, and the first semiconductor device includes a required terminal among the predetermined input / output terminals. A data processing system that determines the internal state by receiving the state of the input at the input circuit. A data processing system comprising: a first semiconductor device that performs data processing; and a second semiconductor device that is connected to and controlled by the first semiconductor device,
When an abnormality occurs, the first semiconductor device controls a terminal state of a predetermined input / output terminal according to a program range of the data processing and a generation factor of a predetermined event assumed during execution of the program in the range. Control data for storing the control data in advance in the nonvolatile memory unit, and sequentially setting a search key for specifying the control data in the nonvolatile memory unit as the data processing proceeds. In accordance with the control data referred to based on, the state of the predetermined input / output terminal is set to a pull-up, pull-down, high impedance or previous value holding state,
The second semiconductor device receives a state of a required terminal among the predetermined input / output terminals by an input circuit to determine an internal state, and the first semiconductor device is a state of the required terminal among the predetermined input / output terminals. A data processing system that receives an input circuit to determine the internal state.

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