JPH05300199A - Serial data transfer equipment - Google Patents

Abstract

PURPOSE:To test the function of a reception error detecting circuit by the loop back test of the serial data. CONSTITUTION:When the logical values of a test mode specifying signal input terminal TEST and a modification mode specifying signal input terminal MOD are both '1', the modification loop back mode is obtained. At this time, when the bit M1 of a modification specifying register 100 is '1', the output of a parity bit generating circuit 12 is reversed and inputted to a received data input line 27. When a bit M0 is '1', the output of a stop bit generating circuit 13 is reversed and inputted to the received data input line 27. Thus, the function of an error detecting circuit 23 is checked by the loop back test mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transfer device, and more particularly to a serial data transfer device having a self system test function.

[0002]

2. Description of the Related Art Generally, a serial data transfer apparatus having a transmitter and a receiver inputs the data transmitted from the transmitter to the receiver in order to test its own function. In many cases, it has a test mode (hereinafter referred to as a loopback test mode) capable of performing the above.
As a result, even if the device is connected to the line, the self-system can be tested without being affected by the outside.

FIG. 4 is a circuit diagram of a serial data transfer device showing such a conventional example, and FIG. 5 is a timing diagram of various bits for explaining the data transfer format in FIG. As shown in FIG. 4, this conventional serial data transfer device is an example of a device generally called start-stop synchronization type. In the asynchronous mode, a start bit is added to the beginning of a character and a stop bit is added to the end to transmit / receive serial data. As an example of the format, a data length of 8 bits and a parity bit addition mode are shown in FIG. Is shown in. This 8-bit data is transmitted in order from LSB (D0) to MSB (D7).

First, in FIG. 4, the transmission side of the serial data transfer device is connected to the data bus 1 and sends out a start bit. Transmission shift register 10 and this register 1
0, etc., a transmission control circuit 11, a parity generation circuit 12 that creates a parity bit, a stop bit generation circuit 13 that generates a stop bit, transfer data selection transfer gates 14 to 16, and a transmission data output terminal. With TXD. In addition, the reception side is the reception control circuit 2
1, a reception buffer 22, an error detection circuit 23, a reception data input terminal RXD, a test mode designation signal input terminal TEST, test mode transfer gates 30 and 32, and a test mode inverter circuit. 31 and 31 are provided. The transmission data written from the data bus 1 to the transmission shift register 10 has a logical value of 0.
A start bit (hereinafter referred to as “0”) is added,
In synchronism with the transmission shift clock 17 supplied from the transmission control circuit 11 to the transmission shift register 10, shift-out is performed toward the transmission data output terminal TXD based on the format shown in FIG. At this time, the parity generation circuit 12
Receives the data to be shifted out from the transmission shift register 10 and generates the logic of the parity bit. In even parity mode, the number of logical value 1 (hereinafter referred to as “1”) included in both data bits and parity bits is even, and in odd parity mode, both data bits and parity bits are included. The logical values of the parity bits are determined so that the number of included “1” s is odd. On the other hand, the stop bit generation circuit 13 is for generating data "1" (mark state) when the stop bit is transmitted and the line is not used.

Next, the transmission control circuit 11 outputs transmission data selection signals 18A, 18B and 18C in addition to the transmission shift clock 17 according to the type of data to be transmitted. Here, during transmission of the start bit and the data bit, the selection signal 18A is "1" and 18B and 18C are "0". As a result, the transfer gate 14 becomes conductive and the transfer gates 15 and 16 become non-conductive. Further, during transmission of the parity bit, the selection signal 18B becomes "1", the selection signals 18A and 18C become "0", the transfer gate 15 becomes conductive, and the transfer gates 14 and 16 become non-conductive. Further, when the stop bit is being sent and the line is not used, the selection signal 18C is "1", the other selection signals 18A and 18B are "0", the transfer gate 16 is in the conductive state and the transfer gates 14 and 15 are in the conductive state.
Becomes non-conductive. Thus, at the time of transmission, the transmission data based on the format of FIG. 5 is output from the transmission data output terminal TXD via the transmission data output line 19.

When the reception control circuit 21 recognizes that the start bit is input from the reception data input line 27, it outputs the reception shift clock 24. In response to this, the reception shift register 20 sequentially takes in the data bits on the reception data input line 27. Then, when the reception is completed, the data in the reception shift register 20 is transferred to the reception buffer 22, and the data bus 1 is sent in response to the request from the CPU.
Read out. Further, during reception, the error detection circuit 23 monitors the received data by the clock 25, and when the parity does not match (parity error) or the stop bit is not detected (framing error), the interrupt signal 26 is generated and the CPU is notified. Notify that a reception error has occurred.

Next, the test mode designation signal input terminal TE
When ST is "0", it is in the normal operation mode, the transfer gate 30 is non-conductive, and the output of the inverter circuit 31 is "1". Therefore, the transfer gate 32 is conductive and the external circuit The data input to the reception data input terminal RXD is supplied to the reception data input line 27. When the test mode designation signal input terminal TEST is "1", the loopback test mode is set, the transfer gate 30 is in the conductive state, and the output of the inverter circuit 31 is "0", so the transfer gate 32 is in the non-conductive state and the external The data of the transmission data output line 19 is supplied to the reception data input line 27 without being affected by the data input to the reception data input terminal RXD from the line.

[0008]

The above-mentioned conventional serial data transfer device uses the loopback test mode to test whether or not the normally transmitted data can be normally received by the own receiving device. It is possible. However, if abnormal data is received, it is not possible for the receiving device to detect an error and output an interrupt signal, that is, to perform a test in the loopback test mode as to whether the error detection circuit functions normally. Can not. For this reason, it is necessary to externally give irregular data to test the error detection circuit, and in order to improve the reliability of the test, there is a drawback that the apparatus becomes complicated and the cost becomes high.

An object of the present invention is to provide a serial data transfer device which can improve the reliability of the test at low cost by eliminating the need for external data or external device.

[0010]

A serial data transfer apparatus of the present invention transmits a transmission circuit having a serial transmission register, a reception circuit having a serial reception register, and data transmitted bit-serially from the serial transmission register. A means for outputting from the data output terminal, a data loopback means for inputting the bit-serial transmission data to the serial reception register without passing through an external line, and a serial reception by a data modification designation signal without going through an external line. And a means for modifying a part of the return data input to the register.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram of a serial data transfer device showing a first embodiment of the present invention. As shown in Figure 1,
In this embodiment, parts having the same functions as those of the conventional example shown in FIG. 4 are given the same numbers. Also in this embodiment, the transmission side includes a transmission shift register 10 connected to the data bus 1,
Transmission shift clock 17 and transmission data selection signal 18
It has a transmission control circuit 11 for transmitting A to 18C, a parity generation circuit 12 and a stop bit generation circuit 13, transmission data selection transfer gates 14 to 16, and a transmission data output terminal TXD. The receiving side has a reception shift register 20, a reception data input terminal RXD, a reception control circuit 21, a reception buffer 22, and an error detection circuit 23. Furthermore, in addition to these transmitting side and receiving side circuits, a test mode designation signal input terminal TEST
And the transfer gates 30 and 32 for the test mode,
The test mode inverter circuit 31, the modification designation register 100 connected to the data bus 1, and the exclusive OR gate 10 for taking the logic of the parity bit and the stop bit.
1, 102, transfer gates 107 to 109 for data modification, an inverter circuit 103, an OR gate circuit 104, AND gate circuits 105 and 106 for generating a selection signal when modifying data, and a modification mode designation signal input. And a terminal MOD. These test mode designating signal input terminal TEST and modified mode designating signal input terminal MOD are terminals for designating the folding test mode.

First, when TEST = "0", MOD
The normal operation mode is set irrespective of the logical value of the input of, and this is equivalent to the case of TEST = "0" in FIG. Further, when TEST = “1”, the return mode is set, but two kinds of return modes are set by the input logical value of the modification mode designation signal input terminal MOD at this time.

Next, operations in these two kinds of folding modes will be described. First, MO with TEST = "1"
When D = “0”, the output of the inverter circuit 103 becomes “1” and the output of the OR gate circuit 104 becomes “1”,
The transfer gate 107 becomes conductive. Also, A
Since the outputs of the ND gate circuits 105 and 106 are "0", the transfer gates 108 and 109 are non-conductive. Further, since the transfer gate 30 is conductive and the output of the inverter circuit 31 is "0", the transfer gate 32 is non-conductive. From the above, TEST
= 1 and MOD = 0, transmission data output line 1
9 and the reception data input line 27 are connected. This corresponds to the case of TEST = "1" in FIG. 4 described above, that is, the folding mode of the conventional example.

Next, TEST = "1" and MOD = "1".
At this time, since the output of the inverter circuit 103 is “0”, the output of the OR gate circuit 104 depends on the logical value of the transmission data selection signal 18A output from the transmission control circuit 11. Since MOD = "1", the outputs of the AND gate circuits 105 and 106 depend on the logical values of the transmission data selection signals 18B and 18C, respectively. Here, from the data bus 1 to the modification designation register 100, M1 =
A data flow in the loopback test mode when data of "1" and M0 = "0" is written will be described with reference to FIGS.

FIG. 2 is a timing chart of signals at various parts in FIG. As shown in FIG. 2, here, M1 = “1”,
It shows the operation in the loopback test mode when M0 = “0”. First, the data written in the transmission shift register 10 from the data bus 1 is added with a start bit and is shifted out toward the transmission data output TXD in synchronization with the transmission shift clock 17 from the transmission control circuit 11. At this time, the parity generation circuit 12 receives the data shifted out from the transmission shift register 10 and generates the logic of the parity bit. However, the transmission data selection signal 18 is sent during the transmission of the start bit and the bit bit.
Since A becomes "1" and the other selection signals 18B and 18C become "0", only the transfer gate 14 becomes conductive. Further, since the output of the OR gate circuit 104 becomes "1", the transfer gate 107 becomes conductive. However, since the outputs of the AND gate circuits 105 and 106 are both "0", the transfer gates 108 and 109 are non-conductive. Therefore, the same data as the transmission data becomes the reception data by the route of the transmission shift register 10, the transfer gate 14, the transmission data output line 19, the transfer gate 107, the transfer gate 30, the reception data input line 27, and the reception shift register 20. ..

During transmission of the parity bit, the transmission data selection signal 18B becomes "1" and the other selection signals 18
Since A and 18C are "0", transfer gate 1
5 is conductive and transfer gates 14 and 16 are non-conductive. As a result, the output of the OR gate circuit 104 becomes "0" and the transfer gate 107 becomes non-conductive. On the other hand, the output of the AND gate circuit 105 becomes "1", and the transfer gate 108 becomes conductive. Further, the output of the AND gate circuit 106 becomes "0", and the transfer gate 109 becomes non-conductive.
Therefore, the parity generation circuit 12 → the transfer gate 1
The route of 5 → transmission data output line 19 is not connected to the reception side because the transfer gate 107 is in the non-conduction state, and is connected only to the transmission data output terminal TXD. Instead, a path of the output of the exclusive OR gate circuit 101-> transfer gate 108-> transfer gate 30-> reception data input line 27-> reception shift register 20 is formed, and the data via a path different from the transmission path is received data. Become. However, since M1 = “1”, the output of the exclusive OR gate circuit 101 is a bit-inverted version of the output of the parity generation circuit 12, which is the original parity bit value. In other words, the parity bit received by returning is modified so that the parity bit becomes irregular data.

Further, when the stop bit is being sent and the line is not used, the transmission data selection signal 18C becomes "1" and the other selection signals 18A and 18B become "0", so that the transfer gate 16 is in the conductive state and the transfer gate is in the transfer state. Gates 14 and 15 are rendered non-conductive. This makes O
Since the output of the R gate circuit 104 becomes "0", the transfer gate 107 becomes non-conductive. Also, AND
Since the output of the gate circuit 105 is also "0", the transfer gate 108 also becomes non-conductive. But AND
Since the output of the gate circuit 106 is "1", the transfer gate 109 becomes conductive. Therefore, the path from the stop bit generation circuit 13 to the transfer gate 16 to the transmission data output line 9 is not connected to the receiving side because the transfer gate 107 is in the non-conducting state, but is connected only to the transmission data output terminal TXD. Instead, the output of the exclusive OR gate circuit 102 → the transfer gate 10
Since the route of 9 → transfer gate 30 → reception data input line 27 → reception shift register 20 is formed, data via a route different from the transmission route becomes the reception data. However, since M0 = “0”, the output of the exclusive OR gate circuit 101 has the same logical value as the output of the stop bit generating circuit 13 which is the original stop value. That is,
The stop bit received by returning will be regular data.

In short, the modification designation register 100 can realize a test mode (modification folding mode) in which the values of the parity bit and the stop bit of the data returned to the receiving side can be freely modified by the logical values of the bits M1 and M0. .. In the example of FIG. 2, since the parity bit is modified by the irregular data and returned to the receiving side, the error detection circuit 23 confirms the parity error and outputs the interrupt signal 26.

[0020]

[Table 1]

The above description is summarized in Table 1.

FIG. 3 is a modification mode designation circuit diagram in the serial data transfer apparatus for explaining the second embodiment of the present invention. As shown in FIG. 3, the present embodiment has the same basic configuration as that of the first embodiment of FIG. 1 described above, except that the bit M1 of the modification designation register 100 in FIG. 1 is different.
And the modification mode specification circuit of M0 is modified mode specification terminal M
It consists of D1 and MD0. The operation of this embodiment is similar to that of the first embodiment described above, but in this embodiment, the modified folding mode of the parity bit and the stop bit is dynamically switched by the logical values input to the external terminals MD1 and MD0, respectively. It is designed to be able to.

[0023]

As described above, the serial data transfer apparatus of the present invention uses the loopback test mode to test whether or not normally transmitted data can be normally received by its own receiving apparatus. Not only that, even if abnormal data is received, the receiving device should detect an error and output an interrupt signal, that is, perform a test in the loopback test mode to see if the error detection circuit is functioning normally. Therefore, it is not necessary to externally give irregular data to test the error detection circuit, and the test reliability can be improved at low cost without using an external device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a serial data transfer device showing a first embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts in FIG.

FIG. 3 is a modification mode designation circuit diagram in a serial data transfer device for explaining a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a serial data transfer device showing a conventional example.

5 is a timing chart of various bits for explaining the data transfer format in FIG.

[Explanation of symbols]

1 Data Bus 10 Transmission Shift Register 11 Transmission Control Circuit 12 Parity Generation Circuit 13 Stop Bit Generation Circuit 14-16, 30, 32, 107-109 Transfer Gate 20 Reception Shift Register 21 Reception Control Circuit 22 Reception Buffer 23 Error Detection Circuit 31, 103 inverter circuit 100 modification designation register 101, 102 exclusive OR gate 104 OR gate circuit 105, 106 AND gate circuit TXD transmission data output terminal RXD reception data input terminal TEST test mode specification signal input terminal MOD modification mode specification signal input terminal MD1 , MD2 decoration designation terminal

Claims (2)

[Claims] 1. A transmission circuit having a serial transmission register, a reception circuit having a serial reception register, a means for outputting data transmitted bit serially from the serial transmission register from a transmission data output terminal, Data loopback means for inputting transmission data to the serial reception register without passing through an external line, and a part of the loopback data input to the serial reception register without passing through an external line by a data modification designation signal. And a serial data transfer device. 2. The serial data transfer device according to claim 1, wherein the data modification designation signal is supplied from a modification designation register or a modification designation terminal.