JPH09237197A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device whereby an error detecting function is surely diagnosed and reliability is improved by artificially transmitting data of an erroneous transfer mode from a transmission side to a reception side. SOLUTION: CPU 14 generates pseudo error data at the time of a test mode and an adding circuit 18 adds pseudo error data to transmission data which is held in a transmission shift register 17. A selector circuit 24 supplies transmission data where pseudo error data which is outputted from the transmission shift register 17 at the time of test mode to an error detecting circuit 25. Therefore, it is diagnosed whether or not the error detecting circuit 25 is normally operated by transmission data adding pseudo error data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit such as a microcomputer, and more particularly to a semiconductor integrated circuit device having a serial interface circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a semiconductor integrated circuit device having a conventional serial interface circuit. The semiconductor integrated circuit device 41 includes a central processing unit (CP
U) is provided with a transmission shift register (TSR) 42 for serially transmitting the data to the outside, and a reception shift register (RSR) 43 for serially receiving the data supplied from the outside and supplying the data to the CPU. ing. The output end of the transmission shift register (TSR) 42 is connected to the transmission terminal 44, and the reception terminal 45 is connected to the input end of the reception shift register 43 via an error detection circuit 46. The error detection circuit 46 detects a framing error from the parity error of the received data or the presence / absence of a stop bit added at the end of the serial data.

[0003]

In the semiconductor integrated circuit device having the error detection circuit 46, whether the function of the error detection circuit 46 operates normally, that is,
If the self-diagnosis can be made as to whether or not the parity error or the framing error of the received data is normally detected, the reliability of the semiconductor integrated circuit device can be improved.

Conventionally, when a self-diagnosis is performed, the output terminal 44 and the input terminal 45 are externally connected, the data output from the transmission shift register 42 is received, and whether the received data is normal or not is determined. It was detected by the error detection circuit 46. However, the transfer mode of the transmission shift register 42 and the reception mode of the reception shift register 43 are generally set uniquely, and if the transmission side has odd parity, the reception side also has odd parity. Therefore, it is difficult to artificially send the data in the wrong transfer mode from the transmitting side to the receiving side, and the parity error detecting function of the error detecting circuit 46 cannot be sufficiently tested.

Similarly, it is difficult to artificially send data having different bit lengths from the transmitting side to the receiving side. Therefore, the error detection circuit 46 detects a framing error when there is only one type of transfer mode, or detects data of different bit lengths, for example, parity of a serial port having 8-bit transfer and 8-bit + parity bit transfer mode. The error detection function could not be self-diagnosed.

The present invention has been made in order to solve the above problems, and its purpose is to make it possible to intentionally send data in an incorrect transfer mode from a transmitting side to a receiving side, and to provide an error detecting function. Can be reliably diagnosed,
Provided is a semiconductor integrated circuit device capable of improving reliability.

[0007]

According to the present invention, an output terminal is connected to a transmission terminal, holding means for holding transmission data sent from the transmission terminal, and pseudo error data in the test mode connected to the holding means. An additional circuit for adding to the transmission data, a receiving terminal for receiving the data, a detecting means for detecting an error in the data received by the receiving terminal, one input end connected to the receiving terminal, and the other input end for the The transmission data is connected to the output end of the holding means, the output end is connected to the detection means, and the transmission data to which the pseudo error data output from the holding means in the test mode is added is selected and supplied to the detection means. And selecting means.

Further, according to the present invention, a transmission terminal to which an external circuit including a detection means for detecting an error in received data is connected, and an output end is connected to the transmission terminal, and transmission data sent from the transmission terminal is held. Holding means, a control device for generating pseudo error data in the test mode, and an additional circuit connected to the holding means for adding the pseudo error data generated by the control device in the test mode to the transmission data. In the test mode, the transmission data to which the pseudo error data is added is transmitted from the transmission terminal to the external circuit.

That is, according to the present invention, pseudo error data is added to transmission data in the semiconductor integrated circuit device in the test mode to enable transmission. Therefore, it is possible to artificially send data in the wrong transfer mode from the transmitting side to the receiving side. Moreover, the semiconductor integrated circuit device is provided with selecting means for selecting the transmission data to which the pseudo error data is added and supplying it to the detecting means. Therefore, it is possible to diagnose whether or not the detection means is operating normally by the transmission data including the pseudo error data.

Further, by supplying the transmission data to which the pseudo error data is added to the external circuit from the transmission terminal,
It is also possible to diagnose an external circuit that does not have a function of generating pseudo error data.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention.
2 shows a serial interface circuit according to the embodiment of FIG. The semiconductor integrated circuit device 11 is provided with a plurality of terminals. FIG. 1 shows only the transmission terminal 12 as the serial output port and the reception terminal 13 as the serial input port. A central processing unit (hereinafter referred to as CPU) is provided inside the semiconductor integrated circuit device 11.
14 is provided, and the CPU 14 is connected to the data bus 15. A transmission shift register (TS) is connected to the data bus 15 via a buffer register (BFR) 16.
R) 17 is connected, and the output end of the transmission shift register 17 is connected to the transmission terminal 12. An additional circuit 18 for adding pseudo error data to the transmission data in the test mode is connected to, for example, the MSB side of the transmission shift register 17. The additional circuit 18 is a D-type flip-flop circuit (hereinafter referred to as a DFF circuit).
19, 20 and latch circuits (LAT) 21, 22 and a selector circuit (SEL) 23. The DFF circuits 19 and 20 are connected in series, and together with the transmission shift register 17, form a shift register that operates by a clock signal CK. The power supply potential Vcc is supplied to the input terminal of the DFF circuit 19,
Each set input end of 20 is connected to the output end of each of the latch circuits 21 and 22 formed of, for example, a DFF circuit. The input terminals of these latch circuits 21 and 22 are connected to the data bus 15. The output terminal of the DFF circuit 20 is connected to one input terminal of the selector circuit 23, and the power supply potential Vcc is supplied to the other input terminal of the selector circuit 23. The selector circuit 23 is controlled by the control signal S1 output from the CPU 14.

On the other hand, one input end of the selector circuit 24 is connected to the reception terminal 13, and the other input end is connected to the output end of the transmission shift register 17. The selector circuit 24 selects the output terminal of the reception terminal 13 or the transmission shift register 17 according to the control signal S2 output from the CPU 14, and the output terminal of the selector circuit 24 is an error detection circuit. (EDC) 25
It is connected to the. The error detection circuit 25 detects a framing error based on, for example, a parity error of input data or the presence / absence of a stop bit added at the end of serial data. The output end of the error detection circuit 25 is connected to the reception shift register (RSR) 26, and the output end of the reception shift register 26 is the buffer register 2.
7 is connected. The output terminal of the buffer register 27 is connected to the data bus 15. Further, the error detection output signal output from the error detection circuit 25 is supplied to the CPU 14.

The operation of the above configuration will be described.
During normal operation, the data output from the CPU 14 is supplied in parallel to the transmission shift register 17 via the data bus 15 and the buffer register 16.
The data supplied to the transmission shift register 17 is serially transmitted from the transmission terminal 12 according to the clock signal CK. At this time, in the selector circuit 23, the power supply potential Vcc is selected by the control signal S1 output from the CPU 14. Therefore, for example, a high-level stop bit is added to the MSB of the data output from the transmission shift register 17.

In the selector circuit 24, the receiving terminal 13 is selected by the control signal S2 output from the CPU 14. The data supplied from the outside to the reception terminal 13 is supplied to the error detection circuit 25 via the selector circuit 24, and the error detection circuit 25 detects the presence or absence of an error in the reception data. This error detection circuit 25
The data passed through is supplied to the reception shift register 26, and the data in the reception shift register 26 is supplied to the CPU 14 via the buffer register 27 and the data bus 15.

On the other hand, for example, when the power is turned on, the CPU 14
First, the test mode is set, and the operation of the error detection circuit 25 is self-diagnosed. At this time, the selector circuit 2
3 is D according to the control signal S1 output from the CPU 14.
The output terminal of the FF circuit 20 is selected, and the selector circuit 24 selects the output terminal of the transmission shift register 17 according to the control signal S2. In this state, the CPU 14 outputs, for example, two pieces of pseudo error data. One of these is a parity bit and the other is a stop bit. The stop bit is set in the DFF circuit 19 via the latch circuit 21, and the parity bit is set in the latch circuit 22.
Is set in the DFF circuit 20 via. These parity bits and stop bits are regarded as incorrect data. Further, arbitrary data is set in the transmission shift register 17 via the data bus 15 and the buffer register 16.

In this state, the data shift register 17 and the DFF circuits 19 and 20 are set in the transmission shift register 17 and the DFF circuits 19 and 20.
These data are transferred according to the selector circuit 2
4 is supplied to the error detection circuit 25. The error detection circuit 25 checks the parity bit and the stop bit, and if the error detection circuit 25 is operating normally, sends an error detection output signal corresponding to a parity error or a framing error to the CPU 14. CPU14
Can recognize that the error detection circuit 25 is operating normally based on the supplied error detection output signal.

According to the above-described embodiment, the additional circuit 18 and the selector circuit 24 are provided in the semiconductor integrated circuit device 11, and in the test mode, the additional circuit 18 sends the transmission data with a pseudo error as a test bit including a stop bit and a parity bit. The data is added and output from the transmission shift register 17, and the transmission shift register 17
The output signal of is taken into the error detection circuit 25 by the selector circuit 24. Therefore, the semiconductor integrated circuit device 11 can self-diagnose the operation state of the error detection circuit 25, so that the reliability of the semiconductor integrated circuit device 11 can be improved.

Next, a second embodiment of the present invention will be described with reference to FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals. In the first embodiment, the operation state of the error detection circuit 25 inside the semiconductor integrated circuit device 11 is self-diagnosed in the test mode. On the other hand, in the second embodiment, the operating state of the error detection circuit of another semiconductor integrated circuit device connected to the semiconductor integrated circuit device 11 can be diagnosed.

That is, in FIG. 2, the transmission terminal 12 of the semiconductor integrated circuit device 11 is connected to the reception terminal 32 of the semiconductor integrated circuit device 31, and the reception terminal 13 is connected to the transmission terminal 33 of the semiconductor integrated circuit device 31. . Inside the semiconductor integrated circuit device 31, an error detection circuit 34 connected to the reception terminal 32, a reception shift register 35 connected to the error detection circuit 34, a transmission shift register 36 connected to the transmission terminal 33, and the like. Is provided.

In the above structure, the transmission data and the pseudo error data generated as described above inside the semiconductor integrated circuit device 11 in the test mode are output from the transmission terminal 12 and the reception terminal 32 of the semiconductor integrated circuit device 31. Are supplied to the error detection circuit 34. Error detection circuit 3
If 4 is normal, pseudo error data can be detected, and an error detection output signal can be sent to the CPU (not shown) of the semiconductor integrated circuit device 31. Therefore,
The CPU, based on the supplied error detection output signal,
It can be recognized that the error detection circuit 34 is operating normally.

According to the second embodiment, the transmission data including the pseudo error data generated in the semiconductor integrated circuit device 11 is supplied to the semiconductor integrated circuit device 31, so that the pseudo error data generation function is not provided. The error detection circuit 34 of the semiconductor integrated circuit device 31 can be diagnosed. Therefore, the reliability of the semiconductor integrated circuit device 11 and the other semiconductor integrated circuit device 31 connected thereto can be improved.

The configuration of the additional circuit 18 is not limited to the configuration shown in FIG. 1, and as shown in FIGS. 3A and 3B, for example, only one of the parity bit and the stop bit is set. It may be configured to.

[0023]

As described above in detail, according to the present invention, the error detection function can be surely diagnosed by intentionally transmitting the data in the wrong transfer mode from the transmitting side to the receiving side. A semiconductor integrated circuit device capable of improving reliability can be provided.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of essential parts showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example of transmission data, showing a modification of the present invention.

FIG. 4 is a circuit configuration diagram of a main part showing a conventional semiconductor integrated circuit device.

[Explanation of symbols]

18 ... Additional circuit, 11, 31 ... Semiconductor integrated circuit device, 1
2, 33 ... Transmission terminal, 13, 32 ... Reception terminal, 14 ... C
PU, 17, 36 ... Transmission shift register (TSR),
26, 35 ... Shift register for reception (RSR), 24 ...
Selector circuit, 25, 34 ... Error detection circuit.

Claims (4)

[Claims] 1. A holding unit having an output terminal connected to a transmission terminal for holding transmission data sent from the transmission terminal, and an additional circuit connected to the holding unit for adding pseudo error data to the transmission data in a test mode. A receiving terminal for receiving data, a detecting means for detecting an error in the data received by the receiving terminal, one input terminal connected to the receiving terminal, and the other input terminal connected to the output terminal of the holding means. An output terminal connected to the detection means, and selecting means for selecting the transmission data added with the pseudo error data output from the holding means in the test mode and supplying the selected transmission data to the detection means. A characteristic semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, further comprising a control device that generates the pseudo error data in the test mode and supplies the pseudo error data to the additional circuit. 3. The semiconductor integrated circuit device according to claim 1, wherein the control device generates at least one of an erroneous parity bit and a stop bit as the pseudo error data in the test mode. 4. A transmission terminal to which an external circuit including a detection means for detecting an error in received data is connected, and a holding means having an output end connected to the transmission terminal and holding transmission data sent from the transmission terminal. A control device for generating pseudo error data in a test mode; and an additional circuit connected to the holding means for adding the pseudo error data generated by the control device in the test mode to the transmission data, A semiconductor integrated circuit device, wherein in the test mode, the transmission data to which the pseudo error data is added is transmitted from the transmission terminal to the external circuit.