JPS6253039A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To improve transmission efficiency without the need of the transmission of a frame synchronizing signal separately from a data signal by using in common a parity check bit for the detection of frame synchronizing position. CONSTITUTION:A signal series whose frame consists of a 1 word data comprising plural bits and its patiry check bit is sent from a transmission side. A reception signal is inputted to a pattern detection circuit 13 comprising the cascade connection of shift registers 14-1, 14-2 having 1-frame of word length is inputted at the reception side. Then the parity check circuit 12 applied parity check to a data series in the shift registers 14-1, 14-2 of each stage every time of one bit shift. When no parity error exists as to all of the shift registers 14-1, 14-2 of each stage, it is detected as the frame synchronizing location.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frame synchronization method for detecting a frame synchronization position for a data signal including a matrix check bit within one frame.

(Prior Art) The configuration of a conventional frame synchronization system will be explained with reference to FIGS. 4 and 5.

On the transmitting side, as shown in FIG. 5, a predetermined specific bit stamp is added every 3t-frame period to the bit sequence of one frame consisting of data signal 1 of one word with multiple bits and parity check bit 2. The receiving side searches for this signal and synchronizes the timing circuit of the receiving device to achieve frame synchronization. Figure 4 shows the configuration of a commonly used 1-bit instant shift frame synchronization circuit. In FIG. 4, the received data series is input to a shift register 5 in a tangent detection circuit 4. In FIG.

In the bang detection circuit 4, the frame synchronization
The match detection circuit 7 compares a predetermined specific bit pattern obtained from the input data sequence pattern with the input data sequence pattern, and performs .

This detection is performed at the clock cycle (one bit cycle) of the received clock obtained by the clock regeneration circuit 8, and a match/mismatch signal is output for each clock. On the other hand, the frame counter 9 outputs a frame counter, and if the current detection result does not match, the AND/Key 10 outputs a signal indicating a mismatch. This discrepancy clock signal is fed back to the inhibit gate 11, and inhibits the next clock signal at the time of detecting the bang. As a result, the counting of the frame counter 9 is stopped by one clock, and a frame pulse is also generated at the next bit position. In this way, if the detection result at a frame pulse position does not match, the bit position is immediately shifted to the next bit position and a new detection result is identified. If the bang detection result is a match, this bit position is regarded as the frame synchronization position, the frame counter 9 starts counting from that point, and a frame signal is output one frame ahead. In this way, one of the above operations is repeated depending on whether or not the detection results match or differ at the frame pulse position, and frame synchronization is established by shifting the frame pulse to the correct frame synchronization position. Then, according to this frame synchronization position, a check for the presence or absence of a correctness error is performed by the correctness check circuit 12. Normally, the frame synchronization position is stabilized by installing a frame synchronization protection circuit (not shown) in the feedback loop from the AND gate 10 to the inhibit gate 11 to prevent synchronization loss (misframe) due to code errors, etc. is planned.

(Problems to be Solved by the Invention) According to this method, it is necessary to transmit an extra frame synchronization signal in addition to the data signal to be transmitted, which increases the required amount of information transmission. When the transmission amount matches the line capacity, there is a drawback that it is necessary to secure one extra line for transmitting the frame synchronization signal. For example, in audio signal transmission for stereo broadcasting, one sample of audio data consists of 11 bits, and by adding one bit of 9 bits, one frame consists of 12 bits. . Since the sampling frequency is 32 KHz, the required information transmission amount is 12×32=384 kb/s. Usually, the capacity of digital data is an integral multiple of 64 kb/s, so this corresponds to 4 lines (1 channel #64 kb/s). Therefore, in order to transmit the frame synchronization signal, it becomes necessary to allocate one more line.

As described above, in the conventional method, it was necessary to transmit the frame synchronization signal separately from the data signal, so there was a drawback that the transmission efficiency was poor.

An object of the present invention is to eliminate the need for frame synchronization signal transmission;
The purpose of this invention is to provide a frame synchronization method with high transmission efficiency.

(Means for Solving the Problems) The present invention detects a frame synchronization position on the receiving side without using a frame synchronization signal.
What is done by using this method is to input the signal sequence to the shift register on the receiving side, and perform all 9 property checks on the data sequence in the shift register every time it is shifted by 1 pit.
The main feature is that frame position detection and synchronization check are performed simultaneously by detecting a point in time when there is no parity error as a frame synchronization position.

Conventional technology does not require frame synchronization signal transmission;
Another difference is that frame synchronization position detection and parity checking can be performed simultaneously.

(Operation) The input signal is input to a shift renostar that accommodates all of a plurality of frames, and a parity check is performed for each frame.

The synchronization position is the position where the integrity of all frames is determined to be normal. Therefore, the parity bit essentially doubles as synchronous pinot.

(Example) Fig. 1 and Fig. 2 are diagrams explaining the present invention in detail, Fig. 2 shows the entire data series of one frame, and Fig. 1 shows the case where two stages of shift renostars of one frame length are connected in cascade. This shows the configuration of the frame synchronization position detection circuit. Circuits that are the same as those in FIGS. 4 and 5 are given the same numbers.

As shown in FIG. 2, in the present invention, a specific beep for frame synchronization is not required in the transmission signal, and only the data signal and parity check bit are transmitted. On the receiving side, the received data sequence is transferred to the cascade-connected shift register 14-1.1 in the tangent detection circuit 13 in FIG.
4-2. The received data input to the shift register is converted into 1 bit according to the clock period (1 bit period) of the received clock pulse obtained by the clock recovery circuit 8.
The bits are shifted sequentially. At this time, the data in each stage of the shift register is checked for each clock cycle, and its output is input to the AND gate 15, and the results of the data in the shift registers in all shift registers are output. Ru. On the other hand, as in the case of FIG. 4, the frame counter 9 outputs the frame/mother pulse, and the 1? If the result of the retouch check is a mismatch (noty error), a mismatch pulse is output from the ANDf-) 10. This mismatch pulse is fed back to the inhibit date 11 and inhibits the next clock pulse at the time of the bang detection (return tee check). As a result, the counting of the frame counter 9 stops for one clock,
A frame counter is also generated at the next bit position. In this manner, when the result of the quality check at a frame pulse position is an error, the data is sequentially shifted to the next bit position and a new /'P property check result is identified. Here, when the data corresponding to one frame is accommodated in exactly one stage of the shift register, the parity check circuit of each stage detects that a no-critity check error has occurred and is an inner. If one frame of data spans two stages of registers, a no-critity check error will occur. Therefore, the frame synchronization position can be detected by searching for a point in time when all stages of parity checks are error-free. As in the case of Figure 4, A? If there is no error in the integrity check, this bit position is regarded as the frame synchronization position, and the frame counter 9 starts counting from that point, and the frame synchronization position is started one frame ahead.
Gurus is output. In this way, one of the above operations is repeated depending on the presence or absence of an error in the AIJ tee check at the frame/9th pulse position, and the frame pulse is shifted to the correct frame synchronization position and frame synchronization is established. As is clear from the above operation, in the present invention, a check for the presence or absence of a parity error according to the frame synchronization position is performed at the same time as the frame synchronization position is detected. That is, it can be seen that there is no parity error at the detected frame position.

The above is a configuration in which the shift register has two stages.
For stages other than stages (n stages, n≧22, e.g. n=3 or n=4), it can be easily realized by increasing or decreasing the number of stages of shift registers and standard check circuits, and the number of input terminals of AND gates. It is possible. FIG. 3 shows the configuration in the case of n stages. Further, as in the case of the conventional example, the frame synchronization position can be stabilized by a frame synchronization protection circuit (not shown) to prevent synchronization loss (misframe) due to code errors or the like.

Next, pseudo synchronization will be explained. For example, in the case of a non-stationary signal such as an audio signal, 1
When you retrieve a frame's worth of data, is it even (or odd) J? probability) is 1/2. Therefore, when one frame of data spans cascade-connected shift registers, the probability of occurrence of a check error in each stage of shift registers is 1/
It becomes 2. Even if there is no parity check error in the shift register, the probability that it corresponds to the data position of one frame is 1/2, that is,
This means that the probability of pseudo-synchronization occurring is 172.

When a plurality of stages of shift registers are connected in cascade, this probability decreases to (1/2)'' if the number of stages is fn.

On the other hand, in the conventional frame synchronization method, one bit or a plurality of pits of frame synchronization bits (fixed/set by a combination of 1 or 0) are added to one frame of data. At this time, if the total number of frame synchronization bits is n bits, the probability of pseudo-synchronization occurring will similarly be (1/2).In this way, the probability of pseudo-synchronization occurring in this method is determined by the number of cascaded shift registers and the conventional method. If the number of synchronization/zoom pits in one frame is made to match, the probability of occurrence of pseudo synchronization in the conventional method is equivalent, and the same characteristics can be obtained.

(Effects of the Invention) As explained above, in the present invention, since the parity check is also used for frame synchronization position detection,
There is no need to transmit the frame synchronization signal separately from the data signal, improving transmission efficiency, and further improving frame position detection.
There is an advantage that the same circuit can be used to execute the yariti check and the check at the same time.

[Brief explanation of drawings]

FIG. 1 shows a synchronous position detection circuit according to an embodiment of the present invention;
3 shows another embodiment of the present invention, FIG. 4 shows a conventional frame position detection circuit, and FIG. 5 shows a conventional frame data sequence. 1...Data signal, 2...Nogrititichenokpinot, 3...Frame synchronization/yatan, 4...zotan detection circuit, 5...shift register, 6...frame synchronization Bang generation circuit, 7... Coincidence detection circuit, 8... Clock regeneration circuit, 9... Frame counter, 10...
Unpique 0-t, 11... Inhibit gut, 12.
... P integrity check circuit, 13... Bang detection circuit, 14-1.14-2, ... 14-n... Shift register, 15... AND gate.

Claims (1)

[Scope of Claims] A signal sequence in which one frame is composed of one word of data consisting of a plurality of bits and a parity check bit for the one word of data is transmitted on the transmitting side, and the word length of one frame is transmitted on the receiving side. The signal sequence is input to a shift register having a total length of n frames, which is made by cascading n stages of shift registers (n is a natural number), and
Frame synchronization characterized in that a parity check is performed on the data sequence in each stage of shift registers each time a bit is shifted, and a frame synchronization position is detected when there is no parity error in all n stages of shift registers. method.