KR100468887B1 - Monitoring System of Serial Data Communication for Signal System of Rail Road - Google Patents

Abstract

The present invention relates to a railway data equipment serial data communication monitoring system, and more particularly, by adding a one-chip circuit to the serial data communication circuit between railway signal equipment to perform code inspection of communication data and failure detection of an electrical serial communication circuit. It relates to a circuit.

The present invention provides a communication system comprising: a first serial adapter 21 for transmitting and receiving serial data transmitted from a CPU; A second serial adapter 22 for feeding back serial data transmitted and received through the first serial adapter 21; Railway signal equipment, characterized in that it comprises a monitoring unit 30 for detecting the error of the serial data connected and transmitted between the first serial adapter 21 and the second serial adapter 22 and the CPU 40 Provide serial data communication monitoring system.

Description

Monitoring System of Serial Data Communication for Signal System of Rail Road}

The present invention relates to a railway data equipment serial data communication monitoring system, and more particularly, by adding a one-chip circuit to the serial data communication circuit between railway signal equipment to perform code inspection of communication data and failure detection of an electrical serial communication circuit. It relates to a circuit.

The conventional serial communication circuit is configured as shown in FIG. The received data is converted into a digital signal using the serial adapter 11 and then received via the UART 12 which converts the data into parallel data for interfacing with the CPU 13.

On the contrary, data transmission converts parallel data through a data line into a digital signal in serial form via the UART 12 and then into an electrical signal of electrical 232/422/485 via the serial adapter 11.

In the conventional serial communication as described above, the data may be transformed due to noise depending on the characteristics of the medium through which the data is transmitted and environmental factors.

In order to monitor such data modification, various code techniques are used to check and correct data errors by using CRC check in application software executed in a microprocessor.

However, this technique is a software-dependent method, and the entire system may be malfunctioned due to algorithm errors. The failure of a serial adapter or UART, a physical device that transmits and receives serial data, cannot be detected.

Since the data to be transmitted is judged normal operation by responding from the counterpart system communicating without feedback, it is impossible to confirm whether the transmitted data has been altered or the counterpart system has malfunctioned. It is a factor that lowers the reliability.

The present invention is to solve the problems of the prior art as described above, to ensure the reliability of the data communication between the railway signal equipment, to detect the wrong data transmission by software by receiving the feedback of the transmitted data in real time, It is to provide a railway signal equipment serial data communication monitoring system having a function of comparing the contents of the received text with a table and performing a code operation necessary for encryption or decryption at a high speed.

1 is a block diagram for explaining a conventional serial data communication circuit.

2 is a block diagram for explaining the configuration of a railway signal equipment serial data communication monitoring system according to the present invention.

In order to achieve the above object, the present invention, as shown in FIG. 2, is connected between the first and second serial adapters 21 and 22 and the CPU 40 for interfacing serial data to be transmitted and received with the counterpart system. It consists of a monitoring unit 30 for monitoring the error of the serial data to be.

The first and second serial adapters 21 and 22 are dual-transmitted / received as circuits for interfacing electrical signals corresponding to 232/422/485 with digital serial data signals.

The monitoring unit 30 includes an Rx data CMP / TDC 31, an Rx / Tx data CMP / TDC 32, an FDC 34, and a code checker data table CMP 35.

The Rx data CMP / TDC 31 adjusts a fine time difference due to the characteristics of the first serial adapter 21 and detects a defect of the duplicated first serial adapter 21. This operation evaluates the output signal of the serial adapter 21 duplicated by the comparison circuit existing inside the CMP / TDC 31, and the time delay detection circuit (TDC) is used to exclude the occurrence of a defect due to the physical characteristics of the device. The time delay detection circuit determines that the data inconsistency exceeding the delay time range allowed by the data transmission rate is a failure.

The Rx / Tx data CMP / TDC 32 adjusts the fine time difference of the serial data of the second serial adapter 22 by the inspection logic, compares the transmitted data with the returned data, and outputs the actual output voltage. Defects are detected.

The UART 33 is duplexed with a circuit for converting serial data into parallel data or vice versa, and has a self-checking characteristic.

The FDC 34, that is, the fault detection circuit, aggregates all the defect occurrence signals from the Rx data CMP / TDC 31 and the Rx / Tx data CMP / TDC 32.

The code checker data table CMP 35 extracts only the data portion of the received data converted in parallel by the UART 33 and compares it with the input data format.

The operation of the present invention configured as described above will be divided into transmission and reception of serial data.

The transmission process of serial data is as follows.

The CPU 40 transmits the transmission data to the UART 33 in a manner of controlling the general UART.

The UART 33 transmits the data using the first serial adapter 21 after checking whether there is data to be transmitted in the previously input data table.

At this time, the transmission output is connected to the reception input of the redundant second serial adapter 22 and the transmitted data is fed back to the monitoring unit 30.

This data is again converted to parallel data via the UART 33 and then compared with the transmission data stored in the internal buffer.

If the returned data is different from the transmitted data, the system considers the defect of the first serial adapter 21 to transmit a failure alert.

In general serial data communication, 128 bytes are transmitted by attaching serial data of 1 byte unit.

This specialized form monitors each byte at high speed using the railway signal equipment serial data communication monitoring system according to the present invention, which is designed only in a hardware structure.

On the other hand, the reception process of the serial data is as follows.

Data from the outside detects defects in the adapter and comparator while going through the redundant adapter and comparator.

The serial data output as the same result from the duplicated adapter and the comparator is similarly converted into parallel data via the duplicated UART 33, and the converted result values are also compared to detect a defect of the UART 33.

The reception of serial data has a slight time difference depending on the analog characteristics of the adapter corresponding to the physical device. Therefore, the comparator used in this circuit incorporates a falling edge detector that synchronizes the start of data, allowing comparison of serial data in consideration of time difference.

The data thus compared and verified is compared with whether data exists in a previously input data table, and the verified data is transmitted to the CPU 40 through the system bus.

The present invention made as described above is applicable to Ethernet communication in addition to serial data communication control, and can be applied to data verification of other data communication in which data format is standardized in addition to railway signal equipment.

The present invention made as described above can minimize the defect detection time of the serial data transmission / receiving hardware by using a hardware logic circuit, and compare the transmitted data with the transmitted data and the returned data as parallel data so that the actually transmitted data is compared. Can be verified

In addition, by using hardware to detect and correct data errors, the system reliability is improved, and the one-chip module design enables easy addition to existing serial data communication circuits.

Claims (2)

A first serial adapter for transmitting and receiving serial data transmitted from a CPU; A second serial adapter for feeding back serial data transmitted and received through the first serial adapter; And a monitoring unit detecting an error of serial data connected and transmitted between the first serial adapter and the second serial adapter and the CPU. The method of claim 1, wherein the monitoring unit comprises: an Rx data CMP / TDC that adjusts a fine time difference due to a characteristic of the first serial adapter and detects a defect of the redundant first serial adapter; An Rx / Tx data CMP / TDC that adjusts a fine time difference of the serial data of the second serial adapter and compares the transmitted data and the feedback data to detect a defect of the transmission data; A UART which is duplicated by a circuit for converting serial data into parallel data and vice versa, and having a self-checking characteristic; An FDC for synthesizing all defect generation signals from the Rx data CMP / TDC and the Rx / Tx data CMP / TDC; And the code checker data table CMP, which extracts only the data portion of the received data converted in parallel by the UART and compares it with the input data form.