JPH02305037A - Abnormality detecting system for data transmission system - Google Patents

Abstract

PURPOSE:To more narrowly specify a hardware abnormality generation range and to quickly cope with the generation of abnormality by connecting a testing buffer in parallel through a switching circuit to a transmission buffer and a reception buffer, respectively. CONSTITUTION:Each testing buffer 23, 25 is connected in parallel through each switching circuit 21a, 21b, 24a and 24b to a transmission buffer 1 and a reception buffer 8. In this state, in the case results of operation of both arithmetic circuits 11, 16, 13 and 17 do not coincide, the generation of abnormality is confirmed, and in this case, the switching circuits 21a, 21b, 24a and 24b are switched to the testing buffers 23, 25, and by these testing buffers 23, 25, monitoring of abnormality of a hardware is performed. Subsequently, when the results of operation do not coincide again, it is judged that abnormality is generated on the side of arithmetic circuits 11, 16, 13 and 17. On the other hand, when the results of operation coincide, it is judged that the transmission buffer 1 or the reception buffer 8 switched to the testing buffers 23, 25 is abnormal. In such a way, a hardware abnormality generation range is specified more narrowly, and it is possible to cope quickly with the generation of abnormality.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention detects abnormalities in hardware components including each buffer in a data transmission system that transmits data using a transmission buffer and a reception buffer. This invention relates to an abnormality detection method for a data transmission system.

(Prior Art) In a data transmission system that transmits digital data, when the data transmission speed becomes too high, the processing speed of the CPU (central processing unit) in each data processing device on the sending and receiving sides becomes faster than the transmission speed. I can't catch up.

In order to eliminate such inconveniences, a data transmission system using a receiving buffer and a transmitting buffer, as shown in FIG. 2, is generally adopted.

That is, in FIG. 2, when transmitting data, transmission data a sent from a data processing device on the transmission side (not shown) is temporarily stored in the transmission buffer 1.

The transmission data a stored in the transmission buffer 1 is read out by the P/S conversion circuit 2 and converted from parallel data to serial data, and then converted to the CRC generated by the CRC generation circuit 3.
An RC check code is added, and the transmission output circuit 4
After being subjected to level conversion, encoding, modulation, etc., the signal is sent to the transmission line 5.

In addition, when receiving data, the transmission line 5
The serial data received from the S
The data is converted into the original parallel data by the /P conversion circuit 7 and temporarily stored in the reception buffer 8. Then, the received data b stored in the receive buffer 8 is read by a data processing device on the receiving side (not shown) and predetermined data processing is performed.

The serial data output from the reception input circuit 6 is sent to the S/P conversion circuit 7 and is also input to the CRC check circuit 9. The CRC check circuit 9 detects a CRC check code added to the received serial data and determines whether an abnormality (error) has occurred in the received data. When an abnormality is detected, an abnormality detection signal C is sent to the data processing device on the receiving side.

However, with this abnormality detection method, the transmission output circuit 4.
Although it is possible to detect that some abnormality has occurred in the transmission line 5 and the reception input circuit 6, the transmission buffer 1. If an abnormality occurs in the reception buffer 8, the P/S conversion circuit 2, the S/P conversion circuit 7, etc., there is a problem in that each data processing device cannot detect the abnormality.

In order to eliminate such inconveniences, arithmetic circuits are provided before and after the transmission buffer and reception buffer, and predetermined calculations are performed at the time of storing and reading data in each buffer.
The inventors proposed an abnormality detection method that detects abnormalities in each buffer by comparing the results of both calculations (Patent Application No. 1983).
-77087).

In this abnormality detection method, as shown in FIG.
1, checksum calculation is performed in this sum generation storage circuit 11, and the calculation result is stored.

Further, the transmission data converted into serial data by the P/S conversion circuit 2 is sent to the transmission output circuit 4 and the CRC generation circuit 3, and is also input to the S/P conversion circuit 12.
Converted to the original data. Then, this parallel data is input to the next sum generation and verification circuit 13, and the
The sum calculation is performed and the calculation result is compared and contrasted with the calculation result stored in the sum generation storage circuit 11.

If the results of each calculation match, the transmission buffer 1
It is determined that there is no abnormality in the P/S conversion circuit 2. If the calculation results do not match, it means that some abnormality has occurred in the transmission buffer 1 and the P/S conversion circuit 2, and an abnormality detection ratio signal d is sent to the data processing device on the transmission side. Further, when an abnormality is detected, an invalid code is further added from the abort circuit 14 to the transmission data to which the CRC check code is attached, which is output from the transmission output circuit 4, as necessary. Then, by detecting the invalidation code from the received data b, the data processing device on the receiving side can determine whether the corresponding received data b is invalid.

On the receiving side, the serial data received by the reception input circuit 6 is sent to the S/P conversion circuit 7 and the CRC-check circuit 9, and is also input to the S/P conversion circuit 15, where it is converted into the original parallel data. be done. Then, the received data converted into parallel data is subjected to a checksum calculation by the next sum generation/storage circuit 16, and the calculation result is stored.

Further, the received data converted into the original parallel data by the S/P conversion circuit 7 is once stored in the receiving buffer 8 and then read out by the data processing device on the receiving side, but the read received data b is It is transmitted to the data processing device and input to the sum generation and verification circuit 17. Then, a checksum operation is performed on the received data b, and the result of the operation is compared with the result of the operation stored in the sum generation/storage circuit 16. If the calculation results match, it is determined that there is no abnormality in the reception buffer 8 and the S/P conversion circuit 7. If the calculation results do not match, some kind of abnormality has occurred in the transmission buffer 8 and the S/P conversion circuit 7, and an abnormality detection signal e is sent to the data processing device on the receiving side.

With such an abnormality detection method, in addition to the abnormality that occurs during transmission as described above, it is possible to reliably detect abnormalities in hardware components before the transmission output circuit 4 or hardware components after the reception input circuit 6. .

However, even with the abnormality detection method configured in this way, the following problems still exist.

In other words, when each data processing device receives each of the abnormality detection signals d and e, it can confirm that some kind of abnormality has occurred in the hardware before the transmission output circuit 4 or after the reception input circuit 7. Send error range to buffer 1
．． Receive buffer 8 side or sum generation storage circuit 11.1
6 and the sum generation/verification circuit 13. It is not possible to determine whether it is the 17 side. Therefore, there is a problem in that it is not possible to specify a more limited range of abnormality occurrence.

In addition, when the transmitting and receiving circuit shown in Figure 3 is incorporated into one integrated circuit, in order to eliminate malfunctions due to manufacturing defects, it is necessary to intentionally combine the calculation results of the sum generation and storage circuit with the sum generation and verification circuit. intentionally make the respective sum check calculation results inconsistent and output abnormality detection signals d and e,
It is necessary to check the operation of the sum generation/storage circuit and the sum generation/verification circuit, but with the abnormality detection method shown in Figure 3, there is no way to intentionally cause discrepancies in the checksum calculation results, resulting in a more perfect product. There are also problems in which testing cannot be carried out.

(Problem to be solved by the invention) In this way, even in the abnormality detection method shown in FIG.
If it is not possible to further limit the range of abnormality occurrence, and if this transmitter/receiver circuit is integrated into one integrated circuit, a more complete product inspection including operation confirmation of the sum generation storage circuit and the sum generation verification circuit is required. There are some issues that make it impossible to implement.

The present invention was made in view of these circumstances, and
By connecting test buffers in parallel to the transmitting buffer and receiving buffer through respective switching circuits, if a discrepancy occurs in each calculation result, it is possible to determine whether the abnormality occurred in the calculation circuit or in each buffer. As a result, it is possible to narrow down the scope of occurrence of hardware abnormalities, quickly respond to abnormalities, and more efficiently check the functionality of each hardware component, including product inspection during manufacturing. The purpose of this paper is to provide a method for detecting abnormalities in data transmission systems that can be implemented.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the abnormality detection method of the data transmission system of the present invention is such that data to be transmitted is temporarily stored in the transmission buffer 7 and then sent to the transmission line. In a data transmission system in which data received from a transmission line is temporarily stored in a reception buffer and then read from the reception buffer, an arithmetic circuit that performs a predetermined operation on data input to each buffer of the transmission buffer and the reception buffer. and an arithmetic circuit that performs predetermined arithmetic operations on the data output from each buffer. By comparing the arithmetic results of both arithmetic circuits, abnormalities in the hardware including each of the buffers are monitored, and each switching is performed for each buffer. Connect each test buffer in parallel through the circuit, and if the calculation results of both calculation circuits do not match, switch the switching circuit to the test buffer side,
By monitoring the hardware abnormality again using this test buffer, the range in which the hardware abnormality occurs is specified.

(Function) According to the abnormality detection method of the data transmission system configured as described above, for example, when an abnormality occurs in a hardware component such as a transmission buffer, a reception buffer, or each arithmetic circuit, an error is detected that is input to each buffer. Since the calculation results between the data and the data output from each buffer no longer match, the occurrence of an abnormality is confirmed.

When the occurrence of an abnormality is confirmed, the switching circuit is switched to the test buffer side, and the above-mentioned hardware abnormality monitoring is performed using this test buffer. Then, as described above, if the calculation results do not match again, it can be determined that an abnormality has occurred on the calculation circuit side. Furthermore, if the calculation results match, it can be determined that the transmission buffer or reception buffer switched to the test buffer is abnormal.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a data transmission system employing the abnormality detection method of the embodiment. Components that are the same as those in FIG. 3 are given the same reference numerals, and redundant explanations will be omitted.

In this embodiment, switching circuits 21a and 21b are inserted in the input and output signal paths of the transmission buffer 1, respectively.
Transmission buffer 1 is connected to the normally closed terminal of each switching circuit 21a, 21b.
is connected, and a test buffer 23 having the same configuration as the transmission buffer 1 is connected to the normally open terminal. And each switching circuit 21a.

21b is simultaneously switched and controlled by a switching signal f from the data processing device on the transmitting side. In the normal operating state, the switching circuits 21a and 21b are switched and connected to the normally closed terminal side, that is, to the transmission buffer 1 side.

On the receiving side, similarly to the transmitting side, switching circuits 24a are provided in the human output signal paths of the receiving buffer 8, respectively.

24b is inserted, and each switching circuit 24a.

The receiving buffer 8 is connected to the normally closed terminal of 24b, and the test buffer 25 having the same configuration as the transmitting buffer 8 is connected to the normally open terminal. The switching circuits 24a and 24b are simultaneously controlled to be switched by a switching signal g from a data processing device on the transmitting side. In the normal operating state, the switching circuit 24a.

24b is switched and connected to the normally closed terminal side, that is, to the receiving buffer 8 side.

Next, the operation of the abnormality detection method of the data transmission system configured as described above will be explained. First, in a normal state, each switching circuit 21a, 21b.

23a and 23b are switching signals f from each data processing device;
g is connected to the normally closed terminal side, that is, the transmission buffer 1 and reception buffer 8 sides.

When parallel transmission data a is input from a data processing device on the transmission side (not shown), the transmission data a is temporarily stored in a transmission buffer 1 and then converted into serial data by a P/S conversion circuit 2. . Further, the transmission data a inputted from the data processing device is subjected to checksum calculation in the sum generation storage circuit 11, and the calculation result is stored.

Further, the transmission data converted into serial data by the P/S conversion circuit 2 is attached with CRC check data by the CRC generation circuit 3, and is sent to the transmission line 5 via the transmission output circuit 4. Furthermore, the transmission data converted into serial data by the P/S conversion circuit 2 is converted into original parallel data by the S/P conversion circuit 12. Then, this parallel data is subjected to checksum calculation in the next sum generation/verification circuit 13, and the calculation result is compared and contrasted with the calculation result stored in the sum generation/storage circuit 11. If the calculation results match, it is determined that there is no abnormality in the transmission buffer 1 and the P/S conversion circuit 2. If the calculation results do not match, it means that a similar or similar abnormality has occurred in the transmission buffer 1 and the P/S conversion circuit 2, and therefore an abnormality detection signal d is sent to the data processing device on the transmission side. Further, when an abnormality is detected, an abort circuit 4 further adds an invalid code to the transmission data to which the CRC check code is attached, which is output from the transmission output circuit 4, as necessary.

Now, upon receiving the abnormality detection signal d, the data processing device on the transmitting side inverts the level of the switching signal C and outputs the signal to the switching circuit 21a.
, 21b to the test buffer 23 side. and,
The same transmission data a as described above is output. The transmission data a input from the data processing device is now transferred to the test buffer 2.
3 and then sent to the P/S conversion circuit 2 where it is converted into serial data. Further, the input transmission data a is subjected to a checksum calculation in the sum generation/storage circuit 11.

Then, the checksum 'fan' for the output transmission data a output from the test buffer 23 is performed in the sum generation verification circuit 13 and compared with the checksum calculation result calculated in the sum generation storage circuit 11 again. be done.

If the calculation results match, the abnormality detection signal d is not output, so the data processing device on the transmitting side can determine that the transmitting buffer 1 is abnormal.

Also, a′! If the J results do not match, the abnormality detection value d is output again, so the data processing device on the sending side determines that the sending buffer 1 is normal and the calculations of the sum generation storage circuit 11 or the sum generation collation circuit 13 etc. It can be determined that the circuit is abnormal.

That is, the data processing device includes a transmission buffer 1° sum generation storage circuit 11. It is possible to specify the range in which an abnormality occurs in hardware components such as the sum generation and verification circuit 13, whether it is on the transmission buffer side or on the arithmetic circuit side.

On the receiving side, the range in which an abnormality has occurred in the hardware member can be identified using almost the same procedure as on the transmitting side.

That is, serial reception data input from the reception input circuit 6 is first passed through the CRC check circuit 9 to the transmission line 5 and the transmission output circuit 4. The presence or absence of an abnormality in the receiving input circuit 6 is detected. Next, it is determined whether the checksum calculation result of the -sum generation storage circuit 16 and the checksum calculation result of the sum generation collation circuit 17 via the reception buffer 8 match or do not match, and if they do not match, an abnormality detection signal e is received. The data is sent to the data processing device on the side.

Then, the data processing device on the receiving side that has received the abnormality detection signal e inverts the level of the disconnection signal g and outputs it to the switching circuit 24.
Switch a and 24b to the test buffer 25 side. Then, it waits for the next received data to be input to the reception input circuit 6. Then, when the received data is input from the reception input circuit 6, the checksum calculation result of the sum generation storage circuit 16 and the checksum calculation result of the sum generation collation circuit 17 via the test buffer 25 are combined as described above. It is determined whether there is a match or a mismatch.

If the calculation results match, the abnormality detection signal e is not output, so the data processing device on the receiving side uses the receiving buffer 8.
can be determined to be abnormal.

In addition, if the calculation results do not match, the abnormality detection signal e is sent again.
Since this is output, it can be determined that the reception buffer 8 is normal and that the calculation circuits such as the sum generation/storage circuit 16 or the sum generation/verification circuit 17 are abnormal.

That is, the data processing device includes a reception buffer 8 degrees, a sum generation storage circuit 16. It is possible to specify the range in which an abnormality occurs in hardware components such as the sum generation and verification circuit 17, whether it is on the receiving buffer side or on the arithmetic circuit side.

Therefore, in a data transmission system that adopts such an abnormality detection method, if an abnormality occurs in a hardware component, the range of the hardware component where the abnormality occurs can be quickly identified, and recovery measures can be taken quickly in response to the occurrence of the abnormality. can be executed.

In addition, by connecting either one of the transmission buffer 1 or the test buffer 23°, the reception buffer 8, or the test buffer 25 that is intentionally malfunctioning, a comparison discrepancy can be generated in the sum generation verification circuit 13°17. It is possible to output abnormality detection signals d and e. Therefore, the sum generation/storage circuit 11.16 and the sum generation/verification circuit 13.1
7 operation check can be performed.

Therefore, when such a transmission/reception circuit is incorporated into a single integrated circuit, in order to eliminate malfunctions due to manufacturing defects, the calculation results of the sum generation storage circuit and each of the sum generation and verification circuits are intentionally Sum check/fr″
! 5. It is necessary to intentionally make the results inconsistent and output the abnormality detection signals d and e to check the operation of the sum generation storage circuit and the sum generation verification circuit. However, if the abnormality detection method shown in Fig. 1 is used, It becomes easy to intentionally cause discrepancies in checksum calculation results, and more complete product inspection can be performed.

[Effects of the Invention] As explained above, according to the abnormality detection method of the data transmission system of the present invention, test buffers are connected in parallel to the transmitting buffer and the receiving buffer through respective switching circuits. . Therefore, when a discrepancy occurs in each calculation result, it is possible to identify whether the abnormality occurred in the calculation circuit or each buffer, and as a result, the range of hardware abnormality occurrence can be narrower, and the response to the abnormality occurrence can be determined. Can be implemented quickly. Furthermore, by connecting a test buffer that has intentionally failed, it is possible to more efficiently check the functionality of each hardware component, including product inspection during manufacturing.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a data transmission system adopting the abnormality detection method of the embodiment, Fig. 2 is a block diagram showing a conventional data transmission system, and Fig. 3 is an abnormality detection method filed and applied for before this application. 1 is a block diagram illustrating a data transmission system employing the above. 1... Transmission buffer, 4... Transmission output circuit, 5...
- Transmission line, 6... Reception input circuit, 8... Reception buffer, 11.16... Sum generation storage circuit (arithmetic circuit), 13.17... Sum generation verification circuit (arithmetic circuit),
21a, 21b, 24a, 24b--switching circuit, 23
．． 2.5... Test buffer, a... Transmission data,
b... Received data, d, e... Abnormality detection signal, f,
g...J change signal.

Claims (1)

[Scope of Claims] A data transmission system in which data to be transmitted is once stored in a transmission buffer and then sent to a transmission line, and data received from the transmission line is once stored in a reception buffer and then read from the reception buffer, comprising: An arithmetic circuit that performs a predetermined arithmetic operation on data input to each buffer of a transmitting buffer and a receiving buffer, and an arithmetic circuit that performs the predetermined arithmetic operation on data output from each of the buffers, and both arithmetic circuits are provided. monitor the hardware including the buffers for abnormalities by comparing the calculation results, connect each test buffer in parallel to each buffer via each switching circuit, and check that the calculation results of both calculation circuits match. If not, the switching circuit is switched to the test buffer side, and the hardware abnormality monitoring is performed again using the test buffer, thereby specifying the hardware abnormality occurrence range. System anomaly detection method.