JPH05204692A - Failure detecting/separating system for information processor - Google Patents

Abstract

PURPOSE:To detect and separate a failed information processor without increasing the number of hardwares in an information processing system capable of allowing N (N is an integer >=3) information processors to execute the same processing, comparing respective processing results and improving its reliability. CONSTITUTION:The selecting combinations of two processing results out of processing results obtained from N information processors 11 to 13 are divided, respective processing results are mutually compared by comparing means 31 to 33, and when respective comparing results coincide with each other, the means 31 to 33 outputs the comparing results to an output bus 6 through output lines. When discrepancy is generated in the comparing results, the means 31 to 33 send error signal and set up their output lines to a high impedance state. Thus the failed information processor is specified based upon the error signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to determination and failure of a processing result obtained when multiple processing is performed in an information processing system including N (N is an integer of 3 or more) information processing devices. The present invention relates to detection of an information processing device and disconnection of a failure information processing device.

[0002]

2. Description of the Related Art Generally, in an information processing system having N information processing devices, the processing results of these information processing devices are once input to a majority voting device and the processing results are determined here. Then, after identifying the failure information processing device based on this determination result, the failure information processing device is separated using the system control device.

[0003]

As described above, in the conventional information processing system, the processing results of the N information processing devices are discriminated using the majority voting method to judge the fault information processing device. Therefore, there is a problem that the amount of hardware increases when determining and disconnecting the failure information processing device, and as a result, not only the reliability decreases but also the price increases.

It is an object of the present invention to provide a failure detection and isolation system which requires a small amount of hardware and can provide an inexpensive information processing system with high reliability.

[0005]

According to the present invention, N (N is an integer equal to or greater than 3) information processing devices are provided, and the information processing devices execute the same operation to each other, and In an information processing system that outputs an N-th processing result, the first to N-th processing results are divided into the number of combinations for selecting two from N, and the processing results are paired with each other. Comparing and detecting whether or not they match, when the processing results match, the comparing means outputs the processing result to the output bus via the output line for each processing result pair. Output, when the processing results do not match, an error signal is sent for each processing result pair and the output line is set to a high impedance state,
Failure detection of an information processing device characterized in that a failure information processing device is specified based on the error signal
A separation method can be obtained. Here, it is desirable that the comparing means sends the error signal and keeps the high impedance state until it receives the reset signal.

[0006]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, an information processing system to which the present invention is applied includes N (N is an integer of 3 or more) information processing devices. In the illustrated example, three information processing devices are provided. These information processing apparatuses 11 to 13 simultaneously perform the same processing, execute the same processing by three information processing apparatuses, determine whether the same processing result is output, and determine the reliability of the processing result. I am raising.

As shown in the drawing, the processing results 21 to 26 are output from the above-mentioned information processing devices 11 to 13 (here,
The processing results output from the same information processing device are the same). The processing results 22 and 23 are given to the comparator 31,
The processing results 24 and 25 are given to the comparator 32. Then, the processing results 20 and 21 are given to the comparator 33.
Each of the comparators 31 to 33 compares the processing results given as inputs, and when the processing results match, outputs the processing results as output values 51 to 53 to the output bus 6. On the other hand, in each of the comparators 31 to 33, when the input processing result is different, the output line to the output bus 6 is set to high impedance and is sent to the error outputs 41 to 43.

Here, with reference to FIG. 1, for example, the failure detection / isolation method according to the present invention will be described assuming that the information processing apparatus 11 has a failure.

Here, since the information processing device 11 has failed and the information processing device 12 and the information processing device 13 are operating normally, 2 of the processing result from the information processing device 11 is obtained.
Only 1 and 22 are different from the processing results of other information processing devices. That is, the processing results 23 to 26 of the information processing device 12 and the information processing device 13 are the same. Therefore, in the comparator 32, the processing result 24 and the processing result 2
5 is detected, and as a result, the comparator 32 outputs the output value 52. On the other hand, the comparator 33 detects a mismatch between the processing result 26 and the processing result 21. Therefore, the output line is set to high impedance and the error output 43 is sent out. Similarly, the comparator 31 detects a mismatch between the processing result 22 and the processing result 23. Therefore, the output line is set to high impedance and the error output 41 is sent out.

As described above, the output lines of the comparators 31 and 33 have high impedance, and only the comparator 32 outputs the output value. As a result, the value on the output bus 6 becomes the output value of the comparator 32, that is, the processing result of the information processing device 12 and the information device 13 which are operating normally.
Furthermore, since the error outputs 41 and 43 are output here, the failure information processing apparatus can make a determination by giving these error outputs 41 and 43 to an external circuit (not shown). That is, it is found that the information processing device 11 is out of order, and thus the information processing device 11 is disconnected by the external circuit.

Similarly, when the information processing device 12 fails, the output lines of the comparator 31 and the comparator 32 become high impedance, and the output value 53 of the comparator 33 appears on the output bus 6. Then, since the error outputs 41 and 42 are output from the comparators 31 and 32, respectively, it can be determined that the information processing device 12 has a failure.

Further, when the information processing device 13 fails, the output lines of the comparator 32 and the comparator 33 become high impedance, and the output value 51 of the comparator 31 appears on the output bus 6. Then, since the comparators 32 and 33 output the error outputs 42 and 43, respectively, it can be determined that the information processing apparatus 13 has a failure.

As described above, in the above-described embodiment, since the error output and the high impedance operation are temporarily performed, it is possible to deal with the intermittent failure of each of the information processing devices 11 to 13, and further the error output 41 to 43. The error log can be obtained by recording.

In the above-described embodiment, the comparator is configured to temporarily perform error output and high impedance, but the error output is continuously output and the output line is connected until the control signal is received from the outside. High impedance may be used, and in this case, the comparators 31 to 31 are used.
Control signals 71 to 73 are applied to the signal No. 3 as required. As described above, the control signals 71 to 73 are transmitted to the comparators 31 to 31.
3 to control the comparators 31 to 3 when a mismatch is detected.
3 automatically disconnects the failure information processing device, and when receiving the control signals 71 to 73 from the outside, the comparators 31 to 33 can connect the information processing devices 11 to 13 again.

In the above embodiment, the information processing system having three information processing devices has been described as an example, but the number of information processing devices is not limited to three, and it is easy to use four or more information processing devices. Applicable.

[0017]

In an information processing system equipped with N (N is an integer of 3 or more) information processing device, the processing results are compared by the number of combinations that take two processing results from the N processing results,
As a result, if they are different, the output line is set to high impedance so that the output of the faulty information processing device is not influenced by the output bus. The effect is that detection and separation can be performed.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of an information processing system to which the present invention is applied.

[Explanation of symbols]

 11-13 Information processing device 21-23 Processing result 31-33 Comparator 41-43 Error output signal line 51-53 Output of comparator 6 Output bus

Claims (3)

[Claims] 1. An information processing apparatus comprising N (N is an integer equal to or greater than 3) information processing apparatuses, the information processing apparatuses executing the same arithmetic operation and outputting first to N-th processing results, respectively. In the system, the first to Nth processing results are N
The processing result pairs are divided into the number of combinations to be selected from the two, and the processing result is compared for each of the processing result pairs, and the comparing means has a comparing means for detecting whether or not there is a match. When they match each other, the processing result is output to the output bus via the output line for each processing result pair, and if the processing results do not match, an error signal is sent for each processing result pair. A failure detection / isolation method for an information processing apparatus, wherein the output line is set to a high impedance state and the failure information processing apparatus is specified based on the error signal. 2. The failure detection / isolation method for an information processing apparatus according to claim 1, wherein the comparison means is composed of N comparators, and the comparators correspond to the processing result pairs. A failure detection / isolation method for information processing devices, which is characterized in that 3. The failure detection / isolation method for an information processing apparatus according to claim 1, wherein the comparison means sends the error signal and continues the high impedance state until receiving a reset signal. A failure detection / isolation method for information processing devices, which is characterized in that