JPH05250196A - Fault tolerant system of computer - Google Patents

Abstract

PURPOSE:To obtain high reliability and to reduce the cost of the whole constitution by setting either one of normal CPU to transmit the output even if an abnormality occurs in either one of three sets of CPU. CONSTITUTION:CPU 11 to 13 synchronizing mutually and performing the same processing are provided, each output of the CPU 11 and 12 is compared by a first comparison circuit CMP 14, each output of the CPU 12 and 13 is compared by a second CMP 15 and each output of CPU 13 and 11 is compared by a third CMP 16. In this case, if each CPU 11 to 13 is normal, each output of the CPU 11 to 13 is transmitted to an output bus 17 by making them the same state and synchronizing each other and a data processing is performed without interfering each other. In contrast with this, as the CMP 14 and 16 generates uncoincident output if an abnormality occurs in the CPU 11, for instance, and gate circuits GAT 18, 20 are turned off by this, the outputs of the CPU 11 and 13 are hindered, and one set of the normal CPU 12 and 13 or the only output of the CPU 12 is transmitted to the output bus 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault tolerant system in which when a plurality of central processing units perform the same processing, the abnormal central processing unit is disconnected and the normal central processing unit continues the processing. Is.

[0002]

2. Description of the Related Art In a data processing device or the like which is required to have high reliability, a central processing unit (hereinafter, CPU) 1 and 2 are used to provide a CPU group (hereinafter, C
PG) 3 and CPU C and CPU 4
PG6, each output of CPU1 and 2 and CPU
The respective outputs of 4 and 5 are compared with the respective ones by comparison circuits (hereinafter, CMP) 7 and 8, and the respective outputs of the CPUs 1, 2, 4 and 5 are transmitted via the CMPs 7 and 8. There is.

The CPUs 1, 2 and 4 and 5 perform the same processing in synchronization with each other, and the CMPs 7 and 8 output the outputs as they are if the outputs of the CPUs 1 and 2 and the CPUs 4 and 5 match. For example, CPU
If an abnormality occurs in 1, the CMP 7 judges that the outputs do not match, and blocks the outputs of the CPUs 1 and 2.
Only the outputs 4 and 5 are sent out, so that the data processing as a whole continues.

[0004]

However, in the conventional system shown in FIG. 2, four CPUs 1, 2, and 4, 5 are required, resulting in an expensive defect. Therefore, an object of the present invention is to provide a computer fault-tolerant method capable of maintaining the same reliability with three CPUs.

[0005]

In order to achieve the above-mentioned object, the present invention provides first to third CPUs that perform the same processing in synchronization with each other and outputs of the first and second CPUs. A first CMP to be compared, a second CMP to compare outputs of the second and third CPUs, and a third and first CPU
CMP for comparing each output of the first and third CMP
First to third gate circuits which are turned off by a mismatch output of a circuit which is inserted between each output of the PU and the common output bus and compares the outputs of the corresponding CPUs in the first to third CMPs. It is equipped with and.

[0006]

Therefore, if an abnormality occurs in one of the CPUs, a CMP that compares the output of this with the output of another CPU
Generated a mismatch output, and the CPU and other C
The gate circuit inserted on the output side of any one of the CPUs is turned off, and only the output of the other one of the normal CPUs is continuously sent to the common bus.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the block diagram of FIG. In the figure, there are provided first to third CPUs 11 to 13 that perform the same processing in synchronization with each other, and the respective outputs of the CPUs 11 and 12 are connected to the first CM.
The second CMP 15 compares the outputs of the CPUs 12 and 13 with each other, and the third CMP 16 compares the outputs of the CPUs 13 and 11 with each other.
First to third gate circuits (hereinafter, referred to as GATs) 18 to 2 are provided between the respective outputs 1 to 13 and the common output bus 17.
0 is inserted, and these are turned off by the mismatch output of the CMP that compares the outputs of the corresponding CPUs among the CMPs 14 to 16.

Therefore, if the CPUs 11 to 13 are normal, the GATs 18 to 20 are on and the CPUs
The respective outputs of 11 to 13 are sent to the output bus 17 in the same state and in synchronization with each other, and data processing is performed without interfering with each other.

On the other hand, if an abnormality occurs in the CPU 11, for example, the CMPs 14 and 16 produce a mismatch output, which turns off the GATs 18 and 20.
The outputs of the CPUs 13 and 13 are blocked and only one of the normal CPUs 12 and 13, that is, only the output of the CPU 12 is output to the output bus 17.
The data processing is continuously performed.

It should be noted that if an abnormality occurs in the CPU 12, only the output of the CPU 13 is sent out in the same manner, and if an abnormality occurs in the CPU 13, only the output of the CPU 11 is sent out in the same manner, so that the overall reliability is high. can get.

[0011]

As is apparent from the above description, according to the present invention, even if an abnormality occurs in any one of the three CPUs, only the output of any one of the normal CPUs is transmitted. As a result, the same high reliability as the conventional one can be obtained with three CPUs, and the price reduction of the entire configuration can be realized, and a remarkable effect can be obtained particularly in a data processing device requiring high reliability. Be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

[Explanation of symbols]

 11-13 Central processing unit 14-16 Comparison circuit 17 Output bus 18-20 Gate circuit

Claims (1)

[Claims] 1. A first to a third central processing unit that performs the same processing in synchronization with each other, a first comparison circuit that compares the outputs of the first and second central processing units, and the first comparison circuit. A second comparison circuit for comparing the outputs of the second and third central processing units, a third comparison circuit for comparing the outputs of the third and first central processing units, and the first to third sections. No. 1 to 3 each of which is inserted between each output of the central processing unit and the common output bus, and is turned off by a mismatch output of a circuit comparing the outputs of the corresponding central processing units in the first to third comparison circuits. A fault tolerant system for a computer, comprising: a first to a third gate circuit.