JPH0749803Y2 - Pin layout structure of integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial field of application) The present invention provides a pin arrangement of an integrated circuit having signal pins for outputting output signals given in parallel from a plurality of output circuits to the outside. Regarding the structure.

(Prior Art) The pin arrangement in an integrated circuit has been determined in consideration of the layout of a circuit formed on a semiconductor chip, or making it easier to distinguish the function of the pin from the outside. That is, a signal pin (hereinafter referred to as “same function signal pin”) from which each bit signal of information composed of a plurality of bit signals is output.
, For example, the respective signal pins for outputting the address signal and the data signal, which are the 32-bit address information and the data bit signal, are arranged as much as possible.

When pins of a large scale integrated circuit (LSI) having a relatively large number of identical function signal pins are arranged according to such an arrangement structure, a large number of identical function signal pins are concentrated. For example, in a 32-bit microprocessor, 32 address signal pins and 32 data signal pins are centrally arranged.

For this reason, output circuits having a relatively large current drive capability for giving bit signals to the same function signal pins are also arranged in a concentrated manner inside the chip. In such an output circuit, a switching operation is often performed almost in parallel due to the function of the output signal.

In this switching operation, the counter electromotive force of LΔi / Δt is generated due to the inductance component existing in the wiring of the power supply (the high voltage source and the low voltage source). Here, the inductance L is in the order of nH (nanohenry), and Δt (switching time) is several nanoseconds due to the speedup of the LSI. In addition, when there are many output circuits that perform switching operations in parallel, the current change amount (Δi) also increases. Therefore, when many output circuits arranged intensively perform switching operation in parallel, a counter electromotive force is locally generated in the power supply line, and the power supply voltage fluctuates greatly.

Therefore, measures are taken to increase the number of power supply pins and reduce the inductance of the power supply lines. In such measures, in order to suppress the counter electromotive force locally generated, it is necessary to locally arrange the power supply pin.

(Problems to be Solved by the Invention) As described above, it is necessary to increase the number of power supply pins and arrange them locally for fluctuations in the power supply voltage due to local noise. As a result, the number of pins in the integrated circuit as a whole is increased and the size of the package is increased.

Therefore, the present invention has been made in view of the above, and an object thereof is to provide a pin arrangement structure of an integrated circuit in which fluctuations in power supply voltage are reduced without increasing the number of pins. is there.

[Configuration of Device] (Means for Solving the Problem) In order to achieve the above-mentioned object, the present invention externally outputs each bit signal of information consisting of a plurality of bit signals provided from an output circuit and representing the same function. A plurality of signal pins for outputting to are provided, and the plurality of signal pins are arranged in a distributed manner so that the output circuits corresponding to the plurality of signal pins are arranged in a distributed manner.

(Operation) In the above configuration, according to the present invention, a plurality of signal pins for outputting a bit signal are arranged in a distributed manner, and output circuits corresponding to the respective signal pins are arranged in a distributed manner with respect to the power source, thereby centralizing the signal. I decided not to place it.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

1 to 4 are diagrams showing pin arrangements of integrated circuits according to the first to fourth embodiments of the present invention.

In the first embodiment shown in FIG. 1, the integrated circuit outputs eight address signal pins (A0 to A7) whose signal pins output address signals to the outside and data signals to the outside. It is composed of eight data signal pins (D0 to D7) and other signal pins (F to M) including a power supply product. That is,
Two sets of eight same function signal pins are provided.

In such an integrated circuit, the address signal pins and the data signal pins are alternately arranged separately on the left and right sides of the integrated circuit, as shown in FIG. That is, the address signal pins A0 to A3 and the data signal pins D4 to D7 are alternately arranged in the left peripheral portion of the integrated circuit.
A4 to A7 and data signal pins D0 to D3 are alternately arranged on the right peripheral portion of the integrated circuit. Therefore, eight address signal pins and eight data signal pins are arranged in a distributed manner without being concentrated. An output circuit (not shown) that gives a signal corresponding to each signal pin to each signal pin is usually arranged so as to have a short distance from the signal pin. Therefore, in the pin arrangement as described above, The output circuits will also be distributed and arranged. This allows
Even if the output circuits corresponding to the same function signal pin, for example, the address signal pin simultaneously perform the switching operation, the counter electromotive force due to the switching is not concentrated on the power supply wiring. That is, the counter electromotive force that causes noise to the power supply is dispersed in the power supply wiring.

Therefore, if the power supply configuration is the same, it is possible to considerably suppress the fluctuation of the power supply voltage, as compared with the case where the same function pins are arranged in a concentrated manner. On the other hand, when the allowable fluctuation value of the power supply voltage is determined, the number of power supply pins can be reduced as compared with the conventional case, and it is not necessary to locally arrange the power supply pins.

Further, when the output circuits are distributed and arranged, a difference occurs in the length of the input wiring path in each output circuit. Therefore, a difference occurs in the input signal of each output circuit, and the operation timing of each output circuit is slightly shifted. Therefore, the number of output circuits that switch at the same time is reduced, and fluctuations in the power supply voltage can be reduced.

The number of power supply pins and the location of the power supply pins may be determined according to the specifications of each integrated circuit. For example, in the pin arrangement shown in FIG. 1, if there is only one power pin,
The output circuits corresponding to the address signal pins and the data signal pins are all supplied with power from the same power supply system. If two power supply pins are provided and two power supply systems corresponding to the respective power supply pins are provided, one of the output circuits corresponding to the address signal pins A0 to A3 and the data signal pins D4 to D7 is Power may be supplied from the power supply system, and power may be supplied from the other power supply system to the output circuits corresponding to the address signal pins A4 to A7 and the data signal pins D0 to D3.

The second embodiment of the present invention shown in FIG. 2 is such that two address signal pins and two data signal pins are alternately arranged. Even with such an arrangement, the output circuits corresponding to the respective signal pins are arranged in a distributed manner. Therefore, also in the second embodiment, the same effect as that of the first embodiment can be obtained.

The third embodiment of the present invention shown in FIG. 3 is an integrated circuit having a pair of same function signal pins (B0 to B9), and has the same function signal pins and other signal pins (F to R). By arranging them alternately, the signal pins having the same function are mixed with other signal pins and dispersed. Even with this arrangement, the output circuits corresponding to the same function signal pins are arranged in a dispersed manner, and the same effect as that of the first embodiment can be obtained.

The fourth embodiment of the present invention shown in FIG. 4 has three sets of identical function signal pins (B0-B5, C0-C5, E0-
In the integrated circuit having E5), the same function signal pins are alternately arranged. Even with this arrangement, the same effect as that of the first embodiment can be obtained.

Even in the second to fourth embodiments, the number of power supply pins and the location of the power supply pins may be determined according to the specifications of each integrated circuit as in the first embodiment. Further, the present invention is not limited to the above-mentioned embodiment, and if the plurality of same function signal pins are arranged so that the output circuits corresponding to the plurality of same function signal pins are distributed with respect to the power supply wiring. , It does not matter what the layout is.

[Effects of the Invention] As described above, in the integrated circuit to which the present invention is applied, the output circuits corresponding to the respective signal pins for outputting the bit signals may be arranged in a distributed manner with respect to the power supply wiring. It will be possible. As a result, the switching noise of the output circuit with respect to the power supply wiring is dispersed, and the fluctuation of the power supply voltage can be reduced without increasing the number of pins.

[Brief description of drawings]

1 to 4 are views showing pin arrangement structures of integrated circuits according to the first to fourth embodiments of the present invention. A0 to A7 …… Address signal pins D0 to D7 …… Data signal pins B0 to B9, C0 to C5, E0 to E5 …… Same function signal pins

Claims (2)

[Scope of utility model registration request] 1. A plurality of address signal pins for outputting an address signal provided from an output circuit to the outside and / or a plurality of data signal pins for outputting a data signal provided from an output circuit to the outside, wherein the address signal pin is provided. The address signal pins and / or the data signal pins are distributed and arranged so that the corresponding output circuits and / or the output circuits corresponding to the data signal pins are arranged in a distributed manner, and the address signal pins and / or the data signal pins are arranged in correspondence with the address signal pins. The pin arrangement structure of the integrated circuit, wherein the output circuit and / or the output circuit corresponding to the data signal pin receives power from the same power supply pin. 2. The pin arrangement structure of an integrated circuit according to claim 1, wherein some or all of the address signal pins and the data signal pins are alternately arranged.