JP2000260947A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily secure a required number of pads for a chip area by using the pads commonly for power supplies and signals. SOLUTION: A pad 14 is connected to an internal power supply VDD via a P-channel transistor and at the same time is connected to a TEST circuit (TEG circuit) via a transmission gate, a low-level control signal and its inversion signal are inputted from a pad 11 to the transmission gate, and the same low- level control signal is inputted to the P-channel transistor for turning on and off the P-channel transistor and the transmission gate, respectively, thus connecting the pad 14 to the internal power supply VDD and causing the pad 14 to function as one for power supply. Also, a high-level control signal and its inversion signal are inputted from the pad 11 to the transmission gate), and the same high-level control signal is inputted to the P-channel transistor for turning off and on the P-channel transistor and the transmission gate, thus connecting the pad 14 to the internal circuit of the TEST circuit (TEG circuit) and causing the pad 14 to function as one for test signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit such as an LSI, and more particularly, to a pad provided on an integrated circuit.

[0002]

2. Description of the Related Art FIG. 14 is a schematic diagram showing a configuration example of a conventional integrated circuit. A plurality of pads 1 are arranged on an LSI chip.
To the internal power supply VDD with the wiring 76 and TEST with the wiring 77
Each pad 1 is connected to a circuit (or a TEG circuit), and each pad 1 is exclusively assigned to a power supply and a signal. Therefore, if the number of pads used for power supply and signal increases, the number of pads must be arranged on the LSI chip by that number.

[0003]

As described above, the pads provided on the conventional integrated circuit are independent for the power supply and the signal, and are not shared. In recent years, the integration ratio of integrated circuits has been improving, and the chip area has tended to be smaller. However, since the pad size cannot keep up with it,
There is a problem that the required number of pads cannot be secured for the chip area. For example, when a plurality of pads provided on an LSI chip are assigned for signals, a situation occurs in which pads to be assigned for power supply become insufficient.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to make the number of pads necessary for a chip area by using the pads for both power supply and signal. An object of the present invention is to provide an integrated circuit that can be easily secured.

[0005]

According to one aspect of the present invention, there is provided an integrated circuit having a plurality of pads, wherein at least one of the pads is connected to an internal power supply. Or a switching circuit connected to either one of the internal circuits, and another one of the pads.
It is another object of the present invention to switch a connection by inputting a control signal from the pads to the switching circuit.

According to a second aspect of the present invention, in an integrated circuit having a plurality of pads, a transistor for connecting at least one of the pads to an internal power supply and a pad connected to the transistor are connected to an internal power supply. When the transistor is turned on by a clocked inverter connected to an internal circuit and a control signal input from another one of the pads, the clocked inverter is turned off and the transistor is turned off. And a control circuit for turning on the clocked inverter.

According to a third aspect of the present invention, in an integrated circuit having a plurality of pads, a transistor for connecting at least one or more of the pads to an internal power supply, and a pad to which the transistor is connected are provided. When the transistor is turned on by a transmission gate connected to an internal circuit and a control signal input from another one of the pads, the transmission gate is turned off, and when the transistor is turned off, And a control circuit for turning on the transmission gate.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the integrated circuit of the present invention.
FIG. 2 is a circuit diagram showing an embodiment. A plurality of pads 11, 12, 13, and 14 used for a signal or a power supply are provided on an LSI chip. Pad 1
4 is connected to an internal power supply (VDD) via a P-channel transistor 15 and to a TEST circuit (or TEG circuit) via a transmission gate 16.
The gate of the P-channel transistor 15 is connected to the pad 11 allocated for TEST1. Transmission gate 1
The gate of the N-channel transistor 161 is TEST
1 for the P-channel transistor 1
The gate of 62 is connected to the TEST1 pad 11 via the inverter 17.

Pad 1 for test and power supply (VDD)
4 includes a plurality of internal power supplies (VDD) and T
P-channel transistor 15 for switching EST circuit (or TEG circuit), transmission gate 16 and inverter 17
Switching circuit, but a pad 1 for test 1
1 is common.

Next, the operation of this embodiment will be described. Normally, the TEST1 pad 11 is at low level “0” and the P-channel transistor 15 is turned on, but the N-channel transistor 161,
Since the P-channel transistor 162 is also off, the transmission gate 16 is shut off. As a result, the pad 14 is connected to the internal power supply VDD through the P-channel transistor 15 and functions as a power supply (VDD) pad.

Next, when the TEST1 pad 11 is changed from low level "0" to high level "1", the P-channel transistor 15 is turned off. At this time, the N-channel transistors 161 and P of the transmission gate 16 are turned off. The channel transistor 162 turns on and the transmission gate 16 conducts.

As a result, the pad 14 is connected to the transmission gate 16
Through a TEST circuit (or TEG circuit), and functions as a bidirectional pad for test signals.

Thus, during testing such as shipping, TE
The above test can be performed by applying "1" to the ST1 pad 11 and switching the pad 11 to a test signal.

According to the present embodiment, the plurality of pads 14
Are used as pads for the power supply VDD and for the test signal, the number of pads required per chip area can be reduced. Thereby, even if the integration ratio of the integrated circuit is improved and the chip area is reduced, the required number of pads for the chip area can be easily secured.

The circuit connected when the pad 14 is switched to a signal is not limited to the TEST circuit (or TEG circuit), but may be any circuit that inputs and outputs signals.
This is the same in the following embodiments.

FIG. 2 is a circuit diagram showing a second embodiment of the integrated circuit of the present invention. However, portions corresponding to the first embodiment shown in FIG. 1 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 20 used for a signal or a power supply are provided on an LSI chip. The pad 20 is connected to an internal power supply (VSS) via an N-channel transistor 18 and to a TEST circuit (or TEG circuit) via a transmission gate 16. The gate of the N-channel transistor 18 is connected via an inverter 17 to the pad 11 allocated for TEST1. The gate of the N-channel transistor 161 of the transmission gate 16 is connected to the pad 11 for TEST1.
, And the gate of the P-channel transistor 162 is connected to the TEST1 pad 11 via the inverter 17.

Pad 2 for test and power supply (VSS)
0 is a plural number, and the internal power supply (VSS) and T
N-channel transistor 18 for switching EST circuit (or TEG circuit), transmission gate 16 and inverter 17
Switching circuit, but a pad 1 for test 1
1 is common.

Next, the operation of this embodiment will be described. Normally, the TEST1 pad 11 is at low level "0", and the N-channel transistor 18 is turned on.
At this time, the N-channel transistor 16 of the transmission gate 16
1. Since the P-channel transistor 162 is off, the transmission gate 16 is shut off. As a result, the pad 20 is connected to the internal power supply VSS through the N-channel transistor 18 and functions as a power supply (VSS) pad.

Next, when the TEST1 pad 11 is changed from low level "0" to high level "1", the N-channel transistor 18 is turned off. At this time, the N-channel transistor 161 and the P-channel transistor 162 of the transmission gate 16 are turned on, and the transmission gate 16 is turned on. Thus, the pad 20 is connected to the TEST circuit (or the TEG circuit) through the transmission gate 16 and functions as a test signal bidirectional pad.

Therefore, at the time of testing such as shipping, TEST
The above test can be performed by applying “1” to the 1 pad 11 and switching the pad 20 to a test signal.

According to the present embodiment, the plurality of pads 20
Is used as a common pad for the power supply VSS and the signal for the TEST2 signal, the number of pads required per chip area can be reduced. As a result, even if the integration ratio of the integrated circuit is improved and the chip area is reduced, the required number of pads for the chip area can be easily secured.

FIG. 3 is a circuit diagram showing a third embodiment of the integrated circuit of the present invention. However, portions corresponding to the second embodiment shown in FIG. 2 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 20 used for a signal or a power supply are provided on an LSI chip. Pad 20 is an N-channel transistor 1
8 and a TEST circuit (or TEG circuit) via a transmission gate 16 while being connected to an internal power supply (VSS).
It is connected to the. The gate of the N-channel transistor 18 is connected to the pad 11 allocated for TEST1. N-channel transistor 161 of transmission gate 16
Is connected to the TEST1 pad 11 via the inverter 17, and the gate of the P-channel transistor 162 is connected to the TEST1 pad 11.

Pad 2 for test and power supply (VSS)
0 is a plural number, and the internal power supply (VSS) and T
N-channel transistor 18 for switching EST circuit (or TEG circuit), transmission gate 16 and inverter 17
Switching circuit, but a pad 1 for test 1
1 is common.

In this example, the polarity of the control signal input from the test 1 pad 11 for turning on and off the N-channel transistor 18 and the transmission gate 16 is opposite to that of the second embodiment shown in FIG. is there. That is, when "1" is applied to the test 11 pad 11, the N-channel transistor 18 is turned on and the transmission gate 16 is turned off.
The pad 20 functions as a power supply (VSS).

Next, when "0" is applied to the pad 11 for test 1, the N-channel transistor 18 is turned off and the transmission gate 16 is turned on, so that the pad 20 functions as a bidirectional test signal. Thus, the present embodiment has the same effect as the second embodiment.

FIG. 4 is a circuit diagram showing a fourth embodiment of the integrated circuit according to the present invention. However, portions corresponding to the first embodiment shown in FIG. 1 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 14 used for a signal or a power supply are provided on an LSI chip. Pad 14 is a P-channel transistor 1
5 and to a TEST circuit (or TEG circuit) via a transmission gate 16
It is connected to the. The gate of the P-channel transistor 15 is connected via an inverter 17 to the pad 11 assigned for TEST1. The gate of the N-channel transistor 161 of the transmission gate 16 is connected to the inverter 17.
And the gate of the P-channel transistor 162 is connected to the TEST1 pad 1
1 connected.

Pad 2 for test and power supply (VDD)
0 is a plurality, and the internal power supply (VDD) and T
P-channel transistor 15 for switching EST circuit (or TEG circuit), transmission gate 16 and inverter 17
Switching circuit, but a pad 1 for test 1
1 is common.

In this example, the polarity of the control signal input from the test 1 pad 11 for turning on and off the P-channel transistor 15 and the transmission gate 16 is different from that of the first embodiment shown in FIG. The opposite. That is, test 1
When "1" is applied to the pad 11, the P-channel transistor 15 is turned on and the transmission gate 16 is turned off, so that the pad 14 functions as a power supply (VDD).

Next, when "0" is applied to the test 1 pad 11, the P-channel transistor 15 is turned off and the transmission gate 16 is turned on, so that the pad 14 functions as a bidirectional test signal. Thus, the present embodiment has the same effect as the first embodiment.

FIG. 5 is a circuit diagram showing a fifth embodiment of the integrated circuit of the present invention. However, portions corresponding to the first embodiment shown in FIG. 1 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 14 used for a signal or a power supply are provided on an LSI chip. Pad 14 is a P-channel transistor 1
5 is connected to an internal power supply (VDD), and a TEST circuit (or T
EG circuit). The gate of the P-channel transistor 15 is connected to the pad 11 allocated for TEST1. The control terminal of the clocked inverter 21 is connected to the TEST1 pad 11 through the inverter 17 while being connected to the TEST1 pad 11.

Pad 1 for test and power supply (VDD)
4 includes a plurality of internal power supplies (VDD) and T
Although a switching circuit including a P-channel transistor 15 for switching an EST circuit (or a TEG circuit) and a clocked inverter 21 and an inverter 17 is provided, the pad 11 for test 1 is common.

In this embodiment, since the clocked inverter 21 is used, unlike the first embodiment shown in FIG.
The pad 14 serves both as a dedicated input for the TEST circuit (or the TEG circuit) and a power supply VDD.

Next, the operation of this embodiment will be described. Normally, the TEST1 pad 11 is at low level "0" and the P-channel transistor 15 is turned on. At this time, the clocked inverter 21 is turned off and cut off. Thereby, the pad 14 is connected to the internal power supply VDD through the P-channel transistor 15,
It functions as an input pad for a power supply (VDD).

Next, when the TEST1 pad 11 is changed from low level "0" to high level "1", the P-channel transistor 15 is turned off, but the clocked inverter 21 is turned on and becomes conductive.

As a result, the pad 14 is connected to the TEST circuit (or TEG circuit) through the clocked inverter 21 and functions as a test signal input pad.

Therefore, at the time of testing such as shipping, TEST
The above test can be performed by applying “1” to the pad 11 for one and switching the pad 11 for a test signal. When the signal input to the control terminal of the clocked inverter 21 by an arrow is at high level "1" and the signal input to the opposite side is at low level "0", the clocked inverter 21 is turned on to conduct. However, when the input signal is inverted, the clocked inverter 21 is turned off and cut off.

According to the present embodiment, the plurality of pads 14
Are used as pads for the power supply VDD and for the test signal, the number of pads required per chip area can be reduced. Thereby, even if the integration ratio of the integrated circuit is improved and the chip area is reduced, the required number of pads for the chip area can be easily secured.

Further, since the clocked inverter 21 is used for the switching circuit of the pad 14, the impedance of the switching circuit can be increased, the power consumption of the switching circuit can be reduced, and the input of the high voltage can be reduced. It can be carried out.

FIG. 6 is a circuit diagram showing a sixth embodiment of the integrated circuit of the present invention. However, portions corresponding to the second embodiment shown in FIG. 2 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 20 used for a signal or a power supply are provided on an LSI chip. Pad 20 is an N-channel transistor 1
8 and a TEST circuit (or TEST circuit) via a clocked inverter 21.
EG circuit). The gate of the N-channel transistor 18 is connected via an inverter 17 to the pad 11 allocated for TEST1. The control terminal of the clocked inverter 21 is connected to the TEST1 pad 11 through the inverter 17 while being connected to the TEST1 pad 11.

Pad 2 for test and power supply (VSS)
0 is a plural number, and the internal power supply (VSS) and T
A switching circuit including an N-channel transistor 18 for switching an EST circuit (or a TEG circuit), a clocked inverter 21 and an inverter 17 is provided, but the pad 11 for test 1 is common.

In this embodiment, since the clocked inverter 21 is used, unlike the second embodiment shown in FIG.
The pad 20 serves as both a dedicated pad for inputting a test signal and a pad for power supply VSS.

Next, the operation of this embodiment will be described. Normally, the TEST1 pad 11 is at low level "0" and the N-channel transistor 18 is turned on. At this time, the clocked inverter 21 is turned off and cut off. Thus, the pad 20 is connected to the internal power supply VSS through the N-channel transistor 18,
Functions as a power supply (VSS) pad.

Next, when the TEST1 pad 11 is changed from high level "0" to low level "1", the N-channel transistor 18 is turned off, but the clocked inverter 21 is turned on to conduct.

Thus, the pad 20 is connected to the TEST circuit (or TEG circuit) through the clocked inverter 21 and functions as a test signal input pad.

Therefore, at the time of testing such as shipping, TEST
The above test can be performed by applying “1” to the one pad 11 and switching the pad 11 for the test.

According to the present embodiment, the plurality of pads 20
Is used as a pad for both the power supply VSS and the test signal, the number of pads required per chip area can be reduced. Thereby, even if the integration ratio of the integrated circuit is improved and the chip area is reduced, the required number of pads for the chip area can be easily secured.

Further, since the clocked inverter 21 is used for the switching circuit of the pad 14, the impedance of the switching circuit can be increased, the power consumption of the switching circuit can be reduced, and the input of the high voltage can be reduced. It can be carried out.

FIG. 7 is a circuit diagram showing a seventh embodiment of the integrated circuit according to the present invention. However, portions corresponding to the sixth embodiment shown in FIG. 6 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 20 used for a signal or a power supply are provided on an LSI chip. Pad 20 is an N-channel transistor 1
8 and a TEST circuit (or TEST circuit) via a clocked inverter 21.
EG circuit). The gate of the N-channel transistor 18 is connected to the pad 11 allocated for TEST1. The control terminal of the clocked inverter 21 is connected to the TEST1 pad 11 through the inverter 17 while being connected to the TEST1 pad 11.

Pad 2 for test and power supply (VSS)
0 is a plural number, and the internal power supply (VSS) and T
A switching circuit including an N-channel transistor 18 for switching an EST circuit (or a TEG circuit), a clocked inverter 21 and an inverter 17 is provided, but the pad 11 for test 1 is common.

In this embodiment, since the clocked inverter 21 is used, unlike the first embodiment shown in FIG.
The pad 20 serves as both a dedicated pad for inputting a test signal and a pad for power supply VSS.

In the present embodiment, the polarity of the control signal input from the test 1 pad 11 for turning on and off the N-channel transistor 18 and the clocked inverter 21 is the sixth embodiment shown in FIG. The opposite of that of the form. That is, when "1" is applied to the pad 11 for test 1, the N-channel transistor 18 is turned on and the clocked inverter 21 is turned off.
SS), and when "0" is applied to the test 1 pad 20, the N-channel transistor 18 is turned off and the clocked inverter 21 is turned on, so that the pad 20 functions as a test input signal. There is an effect similar to that of the sixth embodiment.

FIG. 8 is a circuit diagram showing an integrated circuit according to an eighth embodiment of the present invention. However, parts corresponding to the fifth embodiment shown in FIG. 5 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 14 used for a signal or a power supply are provided on an LSI chip. Pad 14 is a P-channel transistor 1
5 is connected to an internal power supply (VDD), and a TEST circuit (or T
EG circuit). The gate of the P-channel transistor 15 is connected via an inverter 17 to the pad 11 assigned for TEST1. The control terminal of the clocked inverter 21 is connected to the TEST1 pad 11 through the inverter 17 while being connected to the TEST1 pad 11.

Pad 1 for test and power supply (VDD)
4 includes a plurality of internal power supplies (VDD) and T
Although a switching circuit including a P-channel transistor 15 for switching an EST circuit (or a TEG circuit) and a clocked inverter 21 and an inverter 17 is provided, the pad 11 for test 1 is common.

In this embodiment, since the clocked inverter 21 is used, unlike the fifth embodiment shown in FIG.
The pad 14 is a pad dedicated to input of the test signal and a pad for the power supply VSS.

In the present embodiment, the polarity of the control signal input from the test 1 pad 11 for turning on and off the P-channel transistor 15 and the clocked inverter 21 is the fifth embodiment shown in FIG. The opposite of that of the form. That is, when "1" is applied to the pad 11 for test 1, the P-channel transistor 15 is turned on and the clocked inverter 21 is turned off, so that the pad 14
DD).

Next, when "0" is applied to the test 1 pad 11, the P-channel transistor 15 is turned off and the clocked inverter 21 is turned on, so that the pad 14 functions as a test input signal. . Thus, the present embodiment has the same effect as the fifth embodiment.

FIG. 9 is a circuit diagram showing a ninth embodiment of the integrated circuit of the present invention. However, parts corresponding to the fifth embodiment shown in FIG. 5 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 14 used for a signal or a power supply are provided on an LSI chip. Pad 14 is a P-channel transistor 1
5, and to the TEST circuit (or TEG circuit) via the output side of the clocked inverter 21. The gate of the P-channel transistor 15 is connected to the pad 11 allocated for TEST1. The control terminal of the clocked inverter 21 is connected to the TEST1 pad 11 through the inverter 17 while being connected to the TEST1 pad 11.

Pad 1 for test and power supply (VDD)
4 includes a plurality of internal power supplies (VDD) and T
Although a switching circuit including a P-channel transistor 15 for switching an EST circuit (or a TEG circuit) and a clocked inverter 21 and an inverter 17 is provided, the pad 11 for test 1 is common.

Since the pad 14 of this embodiment is connected to the output side of the clocked inverter 21, the pad 14 shown in FIG.
Unlike the first embodiment, the pad 14 is a pad exclusively used for the output of the TEST circuit (or the TEG circuit) and for the power supply VDD.

Next, the operation of this embodiment will be described. Normally, the TEST1 pad 11 is at low level "0" and the P-channel transistor 15 is turned on. At this time, the clocked inverter 21 is turned off and cut off. Thereby, the pad 14 is connected to the internal power supply VDD through the P-channel transistor 15,
It functions as a power supply (VDD) pad.

Next, when the TEST1 pad 11 is changed from low level "0" to high level "1", the P-channel transistor 15 is turned off, but the clocked inverter 21 is turned on to conduct.

As a result, the pad 14 sets the input side to TES
Since it is connected to the output side of the clocked inverter 21 connected to the T circuit (or TEG circuit) connection, it functions as a test signal output pad.

Therefore, at the time of testing such as shipping, TEST
The above test can be performed by applying “1” to the one pad 11 and switching the pad 11 for the test.

According to the present embodiment, a plurality of pads 14
Are used as pads for the power supply VDD and for the test signal, the number of pads required per chip area can be reduced. Thereby, even if the integration ratio of the integrated circuit is improved and the chip area is reduced, the required number of pads for the chip area can be easily secured.

FIG. 10 is a circuit diagram showing a tenth embodiment of the integrated circuit according to the present invention. However, portions corresponding to the sixth embodiment shown in FIG. 6 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 20 used for a signal or a power supply are provided on an LSI chip. The pad 20 is connected to the internal power supply (VSS) via the N-channel transistor 18 and is connected to the TES via the output side of the clocked inverter 21.
It is connected to a T circuit (or TEG circuit). The gate of the N-channel transistor 18 is connected via an inverter 17 to the pad 11 allocated for TEST1. The control terminal of the clocked inverter 21 is TEST1
And connected to the TEST1 pad 11 via the inverter 17.

Pad 2 for test and power supply (VSS)
0 is a plural number, and the internal power supply (VSS) and T
A switching circuit including an N-channel transistor 18 for switching an EST circuit (or a TEG circuit), a clocked inverter 21 and an inverter 17 is provided, but the pad 11 for test 1 is common.

The pad 20 of this embodiment is a clocked inverter 2 having an input side connected to a TEST circuit (or a TEG circuit).
6 is different from the sixth embodiment shown in FIG. 6, the pad 20 is a pad exclusively used for the output of the TEST circuit (or TEG circuit) and for the power supply VDD.

The operation of this embodiment is such that when "1" is applied to the TEST1 pad 11 and the pad 20 is switched for testing, the pad 20 becomes a dedicated output pad of the TEST circuit (or TEG circuit). Is different from the sixth embodiment, and the other operations are the same as those of the sixth embodiment, and have the same effects.

FIG. 11 is a circuit diagram showing an eleventh embodiment of the integrated circuit of the present invention. However, portions corresponding to the seventh embodiment shown in FIG. 7 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 20 used for a signal or a power supply are provided on an LSI chip. The pad 20 is connected to the internal power supply (VSS) via the N-channel transistor 18 and is connected to the TES via the output side of the clocked inverter 21.
It is connected to a T circuit (or TEG circuit). The gate of the N-channel transistor 18 is connected to the pad 11 allocated for TEST1. The control terminal of the clocked inverter 21 is connected to the pad 11 for TEST1 and the pad 1 for TEST1 via the inverter 17.
1 connected.

Pad 2 for test and power supply (VSS)
0 is a plural number, and the internal power supply (VSS) and T
A switching circuit including an N-channel transistor 18 for switching an EST circuit (or a TEG circuit), a clocked inverter 21 and an inverter 17 is provided, but the pad 11 for test 1 is common.

The pad 20 of this embodiment is a clocked inverter 2 having an input side connected to a TEST circuit (or a TEG circuit).
Unlike the seventh embodiment shown in FIG. 7, the pad 20 serves as a dedicated pad for the output of the TEST circuit (or the TEG circuit) and also serves as the power supply VDD.

The operation of the present embodiment is such that when "1" is applied to the TEST1 pad 11 and the pad 20 is switched for testing, the pad 20 becomes a dedicated output pad of the TEST circuit (or TEG circuit). However, only the difference from the seventh embodiment is that the other operations are the same as those of the seventh embodiment and have the same effects.

FIG. 12 is a circuit diagram showing a twelfth embodiment of the integrated circuit of the present invention. However, portions corresponding to the eighth embodiment shown in FIG. 8 will be described using the same reference numerals. A plurality of pads 11, 12, 13, and 14 used for a signal or a power supply are provided on an LSI chip. The pad 14 is connected to an internal power supply (VDD) via a P-channel transistor 15 and TES via an output side of the clocked inverter 21.
It is connected to a T circuit (or TEG circuit). The gate of the P-channel transistor 15 is connected via an inverter 17 to the pad 11 assigned for TEST1. The control terminal of the clocked inverter 21 is TEST1
And connected to the TEST1 pad 11 via the inverter 17.

Pad 1 for test and power supply (VDD)
4 includes a plurality of internal power supplies (VDD) and T
Although a switching circuit including a P-channel transistor 15 for switching an EST circuit (or a TEG circuit) and a clocked inverter 21 and an inverter 17 is provided, the pad 11 for test 1 is common.

Since the present embodiment uses the clocked inverter 21, it differs from the fifth embodiment shown in FIG.
The pad 14 is a pad dedicated to input of the test signal and a pad for the power supply VSS.

The pad 14 of this embodiment is a clocked inverter 2 having an input side connected to a test circuit (or a TEG circuit).
Unlike the eighth embodiment shown in FIG. 8, the pad 14 serves as a dedicated pad for the output of the TEST circuit (or TEG circuit) and the power supply VDD, unlike the eighth embodiment shown in FIG.

The operation of the present embodiment is such that when “1” is applied to the TEST1 pad 11 and the pad 14 is switched for testing, the pad 14 becomes a dedicated output pad of the TEST circuit (or TEG circuit). Is different from the eighth embodiment, and the other operations are the same as those of the eighth embodiment, and have the same effects.

FIG. 13 is a circuit diagram showing a thirteenth embodiment of the integrated circuit according to the present invention. The integrated circuit of this example is a pad 14a, 14b, 20a, 20b for both power supply (VDD or VSS) and test described in the first, second, fifth, and tenth embodiments from the right side of the drawing. In this example, the pads 14a, 14b,
The TEST1 pad 11 for inputting a control signal for switching the functions of 20a and 20b is common.

Next, the operation of this embodiment will be described. When the TEST1 pad 11 is at the low level “0”, all the P-channel transistors 15 and the N-channel transistors 18 are on, and at this time, the transmission gate 16 and the clocked inverter 21 are off. For this reason,
The pads 14a, 14b, 20a, and 20b are connected to the internal power supply VDD, the internal power supply VSS, the internal power supply VDD, and the internal power supply VSS, respectively, and function as power supply pads.

Next, when the pad 11 is at the high level "1", all the P-channel transistors 15 and the N-channel transistors 18 are turned off.
And the clocked inverter 21 is on.

For this reason, the pads 14a, 14b, 20
a and 20b are each connected to a TEST circuit (TEG circuit). For this reason, the pads 14a and 20a
It becomes a pad for a bidirectional test signal of the circuit (TEG circuit). The pad 14b is a TEST circuit (TEG circuit)
, And the pad 20b becomes a pad for output of the TEST circuit (TEG circuit).

According to the present embodiment, a plurality of pads 14
a, 14b, 20a, and 20b are connected to the power supply VDD and the power supply VSS.
The number of necessary pads per chip area can be reduced by using the dual-purpose pads for test and test signals.
Thereby, even if the integration ratio of the integrated circuit is improved and the chip area is reduced, the required number of pads for the chip area can be easily secured.

[0083]

As described above in detail, according to the integrated circuit of the present invention, the necessary number of pads for the chip area can be easily secured by using the pads for both power supply and signal. Can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an integrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the integrated circuit of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the integrated circuit of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the integrated circuit of the present invention.

FIG. 5 is a circuit diagram showing a fifth embodiment of the integrated circuit of the present invention.

FIG. 6 is a circuit diagram showing a sixth embodiment of the integrated circuit of the present invention.

FIG. 7 is a circuit diagram showing a seventh embodiment of the integrated circuit of the present invention.

FIG. 8 is a circuit diagram showing an integrated circuit according to an eighth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a ninth embodiment of the integrated circuit of the present invention.

FIG. 10 is a circuit diagram showing a tenth embodiment of the integrated circuit of the present invention.

FIG. 11 is a circuit diagram illustrating an integrated circuit according to an eleventh embodiment of the present invention.

FIG. 12 is a circuit diagram showing a twelfth embodiment of the integrated circuit of the present invention.

FIG. 13 is a circuit diagram showing a thirteenth embodiment of the integrated circuit of the present invention.

FIG. 14 is a schematic diagram showing a configuration example of a conventional integrated circuit.

[Explanation of symbols]

11 to 14, 14a, 14b, 20, 20a, 20b
Pad 15, 162 P-channel transistor 16 Transmission gate 17 Inverter 18, 161 N-channel transistor 21 Clocked inverter

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 BE05 BE09 DT02 DT03 DT04 EZ20 5J056 AA00 BB53 BB60 CC00 DD12 DD28 EE03 FF07

Claims (3)

[Claims] 1. An integrated circuit having a plurality of pads, comprising: a switching circuit for connecting at least one of the pads to one of an internal power supply and an internal circuit. An integrated circuit for inputting a control signal from another pad to the switching circuit to switch the connection. 2. An integrated circuit having a plurality of pads, wherein: a transistor for connecting at least one of the pads to an internal power supply; and a clocked circuit for connecting the pad to which the transistor is connected to an internal circuit. An inverter and, when the transistor is turned on by a control signal input from another one of the pads, the clocked inverter is turned off; and when the transistor is turned off, the clocked inverter is turned off. An integrated circuit, comprising: a control circuit for turning on the integrated circuit. 3. An integrated circuit having a plurality of pads, wherein a transistor connects at least one of the pads to an internal power supply, and a transmission gate connects the pad connected to the transistor to an internal circuit. And controlling the transmission gate to be turned off when the transistor is turned on and the transmission gate to be turned on when the transistor is turned off by a control signal input from another one of the pads. An integrated circuit, comprising: a circuit;