JPH1168546A - Semiconductor equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pull-up resistor circuit or a pull-down resistor circuit that can reduce occupancy area on a semiconductor substrate and can guarantee power source voltage of extensive operations. SOLUTION: A low-voltage PMOS transistor 1 and a high-voltage PMOS transistor 2 are serially connected to each other between a power source voltage VDD and an input/output terminal 5. Any one gate electrodes of the PMOS transistor 2 is supplied with an ENABLE signal, in which a logical level becomes high when a command to be active is executed with respect to a register for connecting a pull-up resistor to an input terminal through a software. Also, a drain electrode and a source electrode for each of the PMOS transistors 1 and 2 are connected by switches 3 and 4 that can connect or disconnect both of the electrodes. By selecting these switches 3 and 4, the pull-up resistor is made by using the PMOS transistor which is appropriate for the power source voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a software pull-up resistor circuit or a software pull-down resistor circuit built in a microcomputer formed on a semiconductor substrate. The present invention relates to a semiconductor integrated circuit used.

[0002]

2. Description of the Related Art A microcomputer (hereinafter, referred to as a microcomputer) has input, output, or input / output terminals for easily controlling external devices. Since a microcomputer takes in a voltage level given from an external device into a CPU (Central Processing Unit) and performs processing, it is necessary to give a high level or a low level to an input terminal (including an input / output terminal in an input mode). When neither level can be applied due to control of an external device or the like, a resistance element is inserted between a power supply generally called a pull-up resistor and an input terminal to set the input terminal to a high level. The resistance element may be built in the microcomputer according to a demand for high integration of the external device control board.

[0003] A pull-up resistor incorporated in a microcomputer will be described below with reference to the one disclosed in Japanese Patent Application Laid-Open No. 62-259292. In FIG. 6, Rp is a pull-up resistor, Tr3 is a P-channel MOS transistor for interrupting a current flowing from _Vcc to the external terminal IN through the pull-up resistor Rp, and 14 is an external circuit. Tr1 and Tr2 are P-channel MOS transistors and N-channel MOS transistors, respectively.
Constructs an inverter circuit. Power save signal PS
Is low and the P-channel MOS transistor Tr3 is on, the input terminal of the CMOS inverter circuit is pulled up, and when the output of the external circuit 14 is high or in a high impedance state, a low-level signal is supplied to the internal circuit. At the time of low level, a high level signal is supplied to the internal circuit. On the other hand, when the power save signal PS is at the high level and the P-channel MOS transistor is off, the current flowing from _Vcc to the external terminal IN through the pull-up resistor Rp is cut off. The pull-up resistor gives a fixed level to the internal circuit particularly when the output of the external circuit is in a high impedance state.

[0004]

There are several problems in incorporating the above-mentioned circuit into a microcomputer. Usually, the resistance value of the pull-up resistor is several tens of K ohms. However, when this resistor is formed on a semiconductor substrate by a diffusion resistor or the like, the area becomes extremely large as compared with other elements, which causes an increase in the area of the semiconductor chip. In recent years, microcomputers have been increasingly required to operate at a low voltage, so that all circuits mounted on the microcomputer are required to guarantee characteristics at a wide range of voltages.

An object of the present invention is to provide a pull-up resistor circuit or a pull-down resistor circuit which can reduce the area occupied on a semiconductor substrate and can guarantee a wide operating power supply voltage.

[0006]

According to the present invention, there is provided a semiconductor integrated circuit comprising a plurality of circuits provided between a power supply on a high voltage side and an input terminal and having different voltage-resistance characteristics between a drain electrode and a source electrode during conduction. Having an insulated gate transistor, based on the voltage between the power supply on the high voltage side and the input terminal, select the plurality of insulated gate transistors, configure a pull-up resistor with the selected insulated gate transistor It becomes.

Further, the semiconductor integrated circuit of the present invention comprises a plurality of insulated gate transistors provided between a low-voltage side power supply and an input terminal and having different voltage-resistance characteristics between a drain electrode and a source electrode during conduction. Wherein the plurality of insulated gate transistors are selected based on a voltage between a low-voltage side power supply and an input terminal, and the selected insulated gate transistors constitute a pull-down resistor.

[0008] As described above, the input terminal
Input / output terminals in input mode are also included.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the background to the present invention will be described.

If the resistance value of the pull-up resistor is too high, a sufficient current cannot be supplied, and the potential of the input terminal cannot be set to the "H" level in some cases. On the other hand, if the resistance value is too low, the supply current increases and the voltage cannot be sufficiently reduced, and the potential of the input terminal may not be able to be set to the “L” level. Therefore, the pull-up resistor is required to have a resistance value within a predetermined range (the same applies to a pull-down resistor).

As a method for reducing the occupied area when a pull-up (or pull-down) resistor is formed on a semiconductor substrate, the present inventor has proposed a MOS transistor which is an insulated gate transistor as a pull-up (or pull-down) resistor. We considered using it. However, MOS
The transistor exhibits VDS-IDS characteristics as shown in FIG. 3A. When the operating power supply voltage is low and the voltage VDS between the source electrode and the drain electrode is low, the resistance (VDS / IDS) increases. For example, when a user attempts to perform a low-voltage operation on a power supply voltage applied to a microcomputer chip, the resistance value may exceed a desired predetermined range.

A semiconductor integrated circuit according to the present invention comprises a plurality of MOS transistors.
A MOS transistor having an optimum voltage-resistance characteristic between a source electrode and a drain electrode based on the operating power supply voltage of the user is selected from the transistors, and is used as a pull-up (or pull-down) resistor. That is, for example, two MOS transistors exhibiting VDS-IDS characteristics as shown in A and B of FIG.
When a transistor is formed and a user intends to perform a low-voltage operation, a MOS transistor having a characteristic B having a smaller resistance value in a low-voltage region is selected. A MOS transistor having a characteristic A having a larger resistance value in a voltage region is selected. In this way, as shown in FIG. 3C, pull-up (or pull-down) having a suitable resistance value with a small variation in the resistance value (the VDS-IDS characteristic is close to a straight line) at the user's operating power supply voltage. A resistor can be configured.

The area occupied on the semiconductor substrate is
Since there are only a plurality of MOS transistors and means for selecting these MOS transistors (for example, a logic circuit composed of connection wirings and transistors), the occupied area is smaller than the conventional method using a resistance element such as a diffusion resistor. Can be reduced. Further, since a plurality of MOS transistors can be selected, a wide operating power supply voltage can be guaranteed.

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a pull-up resistor circuit according to the present invention. Referring to FIG.
P-channel MOS transistors 1 and 2 are inserted in series with power supply voltage (high-voltage side power supply voltage) V _DD and input terminal 5, and an ENABLE signal that is enabled at a high level by software is supplied to any of the gate electrodes. Have been. A connection point A between P-channel MOS transistors 1 and 2 has a switch 3 for connecting or disconnecting with a power supply voltage and a switch for connecting or disconnecting with input terminal 5. 4 is connected. Here, the switches 3 and 4 select a MOS transistor. The P-channel MOS transistor 1 is a MOS transistor used at a low voltage (for example, 2 V), and the P-channel MOS transistor 2 is a MOS transistor used at a high voltage (for example, 5 V).

The connection and disconnection of the switch can be determined by the operating power supply voltage range of the user, so that it is performed in the wiring process in the semiconductor manufacturing process, and one of the switches 3 and 4 is selected. For example, if the user selects a low voltage, the source and the drain of the P-channel MOS transistor 2 are short-circuited by an aluminum wiring (switch 4 is connected), and if the user selects a high voltage, the P-channel MOS transistor 1
Is short-circuited with an aluminum wiring (switch 3 is connected).

Therefore, since the P-channel MOS transistor to be used has already been determined at the end of the semiconductor manufacturing process, the user activates the register for connecting the pull-up resistor to the input terminal by software. It becomes possible to connect the pull-up resistor only by executing the instruction that

In this embodiment, two MOS transistors are provided to constitute a pull-up resistor according to the present invention.
As shown in FIG. 6, the occupied area can be reduced by 20% or more as compared with the case where the resistance element of the diffusion resistance and the MOS transistor are provided. While it is difficult to reduce the occupied area of the diffusion resistor, the occupied area of the MOS transistor can be further reduced due to the progress of the semiconductor manufacturing technology, and the occupied area can be further reduced by the present invention.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram showing an embodiment of the pull-up resistor circuit according to the present invention. Referring to FIG. 2, a low-voltage P-channel MOS transistor 6 and a high-voltage P-channel MOS transistor 7 are inserted between power supply voltage V _DD and input terminal 8. As a control signal, if a low-voltage P-channel MOS transistor is used for a register for selecting low voltage or high voltage by software with the ENABLE signal and software, the logic level is set to low level, If a channel MOS transistor is used, a HIGH signal whose logic level becomes high is connected. Here, the selection of the MOS transistor is performed by a logic circuit including an inverter and a NAND circuit.

Therefore, the user can connect the pull-up resistor by instructing the two registers.

This embodiment has two MOS transistors,
By providing two NAND circuits and one inverter, it is possible to constitute a means for selecting a pull-up resistor and a MOS transistor according to the present invention. Therefore, as shown in FIG. Compare 7
% Or more of the occupied area could be reduced. While it is difficult to reduce the occupied area of the diffused resistor, the occupied area of a circuit such as a MOS transistor or an inverter can be further reduced due to the progress of semiconductor manufacturing technology. Become.

The present invention can be used not only for a semiconductor integrated circuit using a pull-up resistor but also for a semiconductor integrated circuit using a pull-down resistor. FIGS. 4 and 5 correspond to FIGS. 1 and 2, respectively.
Is an N-channel MOS transistor. In FIG. 5, reference numerals 16 and 17 are N-channel MOS transistors. As shown in FIG. 4, the N-channel MOS transistors 11 and 12 are inserted in series between GND (low-voltage side power supply voltage) and the input terminal 5. As shown in FIG. 5, the N-channel MOS transistors 16 and 17 are inserted between GND and the input terminal 5 in parallel connection. Since the configuration and operation of the semiconductor integrated circuits of FIGS. 4 and 5 are substantially the same as those of FIGS. 1 and 2, description thereof is omitted here.

[0023]

As described above, the semiconductor integrated circuit of the present invention has a plurality of insulated gate transistors and means for selecting a transistor to be used according to the operating power supply voltage. The mounting area can be made smaller than in the case where a pull-up (or pull-down) resistor is realized, and a wide operating power supply voltage can be guaranteed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a characteristic diagram for explaining the present invention.

FIG. 4 is a circuit diagram of another embodiment of the present invention.

FIG. 5 is a circuit diagram of another embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional semiconductor integrated circuit using a pull-up resistor.

[Explanation of symbols]

1, 2, 6, 7 P-channel type MOS transistors 11, 12, 16, 17 N-channel type MOS transistors 3, 4 Switch element Rp Resistance element 5, 8 Input terminal 14 External circuit

Claims (2)

[Claims] 1. A high-voltage side power supply comprising a plurality of insulated gate transistors provided between a high-voltage side power supply and an input terminal and having different voltage-resistance characteristics between a drain electrode and a source electrode during conduction. A semiconductor integrated circuit, wherein the plurality of insulated gate transistors are selected based on a voltage between the insulated gate transistors and a pull-up resistor is formed by the selected insulated gate transistors. 2. A low-voltage power supply comprising a plurality of insulated gate transistors provided between a low-voltage power supply and an input terminal and having different voltage-resistance characteristics between a drain electrode and a source electrode during conduction. A semiconductor integrated circuit, wherein the plurality of insulated gate transistors are selected based on a voltage between the insulated gate transistors and a pull-down resistor is formed by the selected insulated gate transistors.