JPH08125124A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To obtain a semiconductor integrated circuit in which a power switch circuit can be turned ON/OFF only with a small number of external or internal signals by connecting feeder lines, connected with bonding terminals, through the power switch circuit with a circuit block. CONSTITUTION: A circuit block 14 and a power switch circuit 40 are connected with feeder lines VDD and VSS. The power switch control circuit 40 turns power switch circuits 21, 22 ON/OFF for circuit blocks 11-13 based on a signal delivered from the circuit block 14 or an external signal received through a pad. When the circuit blocks 11-13 are turned ON/OFF independently, power consumption can be reduced as compared with a case where the circuit blocks 11-13 are turned ON/OFF simultaneously. Consequently, the power switch circuit can be turned ON/OFF with small number of external or internal signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit with reduced power consumption when not operating.

[0002]

2. Description of the Related Art Since portable electronic equipment is driven by a battery, it is required to reduce the power consumption of the semiconductor integrated circuit when the semiconductor integrated circuit is not in operation and to extend the life of the battery. Figure 5
FIG. 1B shows an outline of the conventional semiconductor integrated circuit 1. The basic logic gate 2 in the semiconductor integrated circuit 1 is, for example, as shown in FIG.
As shown in (A), it is a CMOS inverter, one end of which is connected to the power supply line VDD through the pMOS transistor 3 and the other end of which is connected to the power supply line VSS through the nMOS transistor 4. The transistors 3 and 4 are turned on during the operation, and the transistors 3 and 4 are turned off during the non-operation to reduce the power consumption.

[0003]

However, since the transistors 3 and 4 as the power supply switch circuit are provided for each of the basic logic gates 2, the number of transistors 3 and 4 becomes enormous and the chip size increases and the yield decreases. In addition, there were problems such as high cost. In view of such problems, an object of the present invention is to provide a semiconductor integrated circuit that can reduce the area occupied by a power switch circuit on a chip.

[0004]

According to the present invention, a power switch circuit for turning off when not in operation is arranged around a circuit block, and a power supply line connected to a bonding terminal is used for the power supply. It is connected to the circuit block via a switch circuit. According to the first aspect of the present invention, since the current consumption of the circuit block is generally smaller than the sum of the maximum current consumption of the basic circuits in the circuit block, the power supply is more than that in the case where each basic circuit in the circuit block is provided with the power switch circuit. The area occupied on the chip of the switch circuit can be reduced.

According to a first aspect of the present invention, there is provided a power supply switch control circuit for connecting the power supply line connected to the bonding terminal and controlling ON / OFF of the power supply switch circuit. According to the first aspect, the power switch circuit can be controlled to be turned on / off by only the internal signal without a small external signal or external signal.

In a second aspect of the present invention, the power switch circuit is provided commonly to a plurality of circuit blocks. According to the second aspect, when it is necessary to simultaneously control ON / OFF of a plurality of circuit blocks (including the case of almost the entire circuit on the semiconductor chip), the current consumption of the plurality of circuit blocks is generally the same as that of each circuit block. Since it is smaller than the sum of the maximum current consumption of, the area occupied on the chip of the power switch circuit can be reduced as compared with the case where the power switch circuit is provided for each circuit block.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below in three different forms with reference to the drawings. In the figure, the power switch circuit is hatched to clarify its position. [First Mode] FIG. 1 shows various arrangements of a power supply switch circuit for a semiconductor integrated circuit of the first mode and circuit blocks thereof.

In FIG. 1A, a semiconductor integrated circuit 10
Of the circuit blocks 11 to 14 inside, the circuit blocks 11 to 11
Each of the 13 has power switch circuits 21 and 22 arranged at the peripheral portions of the opposite ends thereof. Circuit block 11-
14 is functionally or physically divided and includes a plurality of basic logic gates. The power switch circuit 21 is 1
One or a plurality of transistors connected in parallel, for example, pMOS transistors, one end of which is connected to a pad 31 or 32 as a bonding terminal through a power supply line VDD, and the other end of which is shown in FIG. As shown, it is connected to a plurality of internal power supply lines Vdd arranged in parallel with each other at regular intervals. Similarly, the power switch circuit 22 includes one or a plurality of transistors connected in parallel, for example, nMOS transistors,
One end thereof is connected to a pad 33 or 34 as a bonding terminal via a power supply line (ground line) VSS, and the other end is connected to a plurality of internal power supply lines Vss arranged in parallel with each other at regular intervals. Has been done.

On the other hand, the power supply lines VDD and VSS are directly connected to the circuit block 14 and the power switch control circuit 40. The power switch control circuit 40, based on a signal from the circuit block 14 or a signal directly supplied from the outside via a pad, the circuit blocks 11 to 13.
ON / OFF of the power switch circuits 21 and 22 for each of the
Control off. This on / off control is performed independently or simultaneously for each of the circuit blocks 11 to 13 according to the function of the circuit blocks 11 to 13. Circuit blocks 11-13
When the on / off control is independently performed for each, power consumption can be reduced as compared with the case where the circuit blocks 11 to 13 are simultaneously on / off controlled. When the on / off control is performed only by the internal signal without the external signal, the external control signal is unnecessary, which is effective.

Power is supplied to each circuit (not shown) in the circuit blocks 11 to 13 from the internal power supply lines Vdd and Vss in the vicinity thereof. For example, the circuit block 11 has a large number of 2
When the input NAND gate is used, at the same time, the power supply line VDD is passed from the power supply line VDD through the NAND gate.
The number of NAND gates through which a through current flows to S is usually 20% or less of all the NAND gates in the circuit block 11.

Therefore, according to the first embodiment, the occupied area on the chip of the power supply switch circuit can be suppressed to 20% or less as compared with the conventional case where the power supply switch circuit is arranged in each NAND gate. Various arrangements of the power switch circuits 21 and 22 with respect to the circuit block 11 can be considered, and specific examples thereof are shown in FIGS.

In FIG. 1C, power supply switch circuits 21 and 22 are arranged along adjacent sides of the circuit block 11. In this case, as shown in FIG. 1D, the internal power supply line Vdd extending from the power switch circuit 21 and the internal power supply line Vss extending from the power switch circuit 22 are arranged so as to intersect with each other in different wiring layers. Has been done. In FIG. 1E, the power switch circuits 21 and 22 are arranged along the adjacent sides of the circuit block 11.

In FIG. 1F, each of the power supply switch circuits 21 and 22 is arranged along one side of the circuit block 11 and a part of two sides adjacent to the one side. In FIG. 1G, both ends of the power switch circuits 21 and 22 of FIG. 1F extend so that the power switch circuits 21 and 22 surround the entire circuit block 11. [Second Mode] In the first mode, the power switch circuit is arranged for each circuit block. However, a common power switch circuit may be arranged for a plurality of circuit blocks. A second mode is shown in FIG. In FIG. 2, the power supply lines VDD and VSS are not shown.

In FIG. 2A, a plurality of circuit blocks 11 are provided.
Power supply switch circuits 21 and 22 are arranged along these opposing sides with respect to .about. Circuit block 14
The same applies to 15 and 15. In FIG. 2B, the power supply switch circuit 21 is arranged along one side of the circuit blocks 11 and 12, and the power supply switch circuit 22 is arranged along the side adjacent to this side and between the circuit blocks 11 and 12. ing. As the circuit block 15, an extension of the internal power supply line for the circuit block 14 is used.

In FIG. 2C, the circuit blocks 11 to 13 are shown.
The power switch circuits 21 and 22 are arranged in the same manner as in FIGS. 1F and 1E, respectively, for the group 1 and the circuit blocks 14 and 15. In the above-described second mode, the current consumption of the plurality of circuit blocks is generally smaller than the sum of the maximum current consumption of each circuit block, especially when it is necessary to control ON / OFF of the plurality of circuit blocks at the same time. Thus, the area occupied by the power switch circuit on the chip can be reduced as compared with the case where the power switch circuit is provided for each circuit block.

[Third Mode] In the second mode, the circuit block is divided into a plurality of groups, and the power switch circuit is arranged for each group. However, almost all of the semiconductor chips in one semiconductor chip are arranged. It is also possible to dispose a power switch circuit in the circuit block, which is shown as a third form in FIGS. 3 and 4. In FIGS. 3 and 4, the power supply lines VDD and VSS are omitted.

In FIG. 3A, the circuit blocks 11-14 are shown.
The power switch circuits 21 and 22 are arranged along the opposite sides when the circuit is regarded as one circuit block. In FIG. 3B, when the circuit blocks 11 to 13 are regarded as one circuit block, the power switch circuits 21 and 22 are arranged in the same manner as in FIG. 1C. FIG.
In (C), when the circuit blocks 11 to 14 are regarded as one circuit block, the power supply switch circuits 21 and 22 are arranged in the same manner as in FIG. 1 (F).

In FIG. 4A, the power switch circuits 21 and 22 are arranged below the bonding pad row. In FIG. 4B, the power switch circuits 21 and 22 are arranged outside the bonding pad row. The circuit blocks 15 and 16 include power supply lines VDD and VSS.
Are supplied directly.

In FIG. 4C, the power switch circuit 21 is provided between the bonding pad row and the circuit blocks 11-14.
And 22 are arranged. Wide power supply lines VDD and VSS connected to the pads 31 and 33, respectively, are arranged on the upper layers of the power switch circuits 21 and 22, and are connected to one ends of the power switch circuits 21 and 22, respectively.

The above third mode can reduce the area occupied by the power switch circuit on the chip more than the second mode, especially when it is necessary to control on / off of almost all circuit blocks in the semiconductor chip at the same time.

[0021]

As described above, according to the semiconductor integrated circuit of the present invention, the current consumption of the circuit block is generally smaller than the sum of the maximum current consumption of the basic circuits in the circuit block. The effect that the area occupied on the chip of the power supply switch circuit can be reduced compared to the case where the power supply switch circuit is provided in the basic circuit.

According to the first aspect of the present invention, there is an effect that the power switch circuit can be controlled to be turned on / off by only the internal signal without a small external signal or external signal. According to the second aspect of the present invention, when it is necessary to control ON / OFF of a plurality of circuit blocks at the same time, the current consumption of the plurality of circuit blocks is generally smaller than the sum of the maximum current consumption of the respective circuit blocks. The effect that the area occupied on the chip of the power supply switch circuit can be reduced compared to the case where the power supply switch circuit is provided for each.

[Brief description of drawings]

FIG. 1 is a block diagram showing various arrangements of a power supply switch circuit for a semiconductor integrated circuit of the first embodiment of the present invention and a circuit block thereof.

FIG. 2 is a block diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional method for reducing power consumption of a semiconductor integrated circuit.

[Explanation of symbols]

 1, 10 Semiconductor integrated circuit 11-16 Circuit block 21, 22 Power switch circuit 31-34 Pad 40 Power switch control circuit

Claims (3)

[Claims] 1. A power switch circuit for turning off when not operating is arranged around the circuit block, and a power supply line connected to a bonding terminal is connected to the circuit block through the power switch circuit. A semiconductor integrated circuit characterized in that. 2. The semiconductor integrated circuit according to claim 1, further comprising a power switch control circuit for connecting a power supply line connected to a bonding terminal and controlling ON / OFF of the power switch circuit. circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the power switch circuit is provided commonly to a plurality of circuit blocks.