JPH0573272B2 - - Google Patents

Info

Publication number
JPH0573272B2
JPH0573272B2 JP1268187A JP1268187A JPH0573272B2 JP H0573272 B2 JPH0573272 B2 JP H0573272B2 JP 1268187 A JP1268187 A JP 1268187A JP 1268187 A JP1268187 A JP 1268187A JP H0573272 B2 JPH0573272 B2 JP H0573272B2
Authority
JP
Japan
Prior art keywords
output
power
circuits
pad
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1268187A
Other languages
Japanese (ja)
Other versions
JPS63179560A (en
Inventor
Makoto Myazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP1268187A priority Critical patent/JPS63179560A/en
Publication of JPS63179560A publication Critical patent/JPS63179560A/en
Publication of JPH0573272B2 publication Critical patent/JPH0573272B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路記憶装置に関し、特にその電
源パツドおよび接地電位パツドと出力回路の配置
に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to integrated circuit storage devices, and more particularly to the arrangement of power and ground potential pads and output circuits thereof.

〔従来の技術〕[Conventional technology]

従来、半導体集積回路を用いた記憶装置は第3
図に示すように、DIP(デユアルインラインパツ
ケージ)30に組立てられたときいちばん端のピ
ンが電源ピン31に設定されることが多かつたの
で、電源ピンとの接続が容易なように電源パツド
32を四辺の中央に設置するのが常であつた。第
4図はそのペレツトの電源パツド、接地電位パツ
ド、および各回路の配置例を示す平面図である。
電源パツド41と設置電位パツド42は、対向す
る長辺のそれぞれの中央に設置され、それぞれか
ら電源線43,44、接地線45,46が左右に
引出されて四辺に沿い延長され、これに出力回路
471〜474,481〜484および出力回路以外
を回路491,492が接続されている。第5図は
他の従来例の場合を示し、各2個に区分された電
源パツド51,52と接地電位パツド53,54
がそれぞれ長辺と短辺の中央に配置され、出力回
路用の電源線55,56および出力回路以外の回
路用の電源線57,58と、それぞれに対応する
接地線59,60,61,62との間に、出力回
路631〜634,641〜644と出力回路以外の
回路651,652が接続されている。
Conventionally, storage devices using semiconductor integrated circuits are
As shown in the figure, when assembled into a DIP (dual in-line package) 30, the very end pin was often set to the power pin 31, so the power pad 32 was set for easy connection to the power pin. It was customary to place it in the center of the four sides. FIG. 4 is a plan view showing an example of the arrangement of the power supply pad, ground potential pad, and each circuit of the pellet.
The power supply pad 41 and the installed potential pad 42 are installed at the center of each of the opposing long sides, and power supply wires 43, 44 and ground wires 45, 46 are drawn out from each side to the left and right and extended along the four sides, and output to these. Circuits 49 1 and 49 2 are connected to circuits other than the circuits 47 1 to 47 4 , 48 1 to 48 4 and the output circuit. FIG. 5 shows another conventional example, in which power supply pads 51 and 52 and ground potential pads 53 and 54 are each divided into two parts.
are arranged at the center of the long side and short side, respectively, and have power supply lines 55, 56 for the output circuit, power supply lines 57, 58 for circuits other than the output circuit, and ground lines 59, 60, 61, 62 corresponding to each other. Output circuits 63 1 to 63 4 , 64 1 to 64 4 and circuits 65 1 and 65 2 other than the output circuits are connected between the output circuits 63 1 to 63 4 and 64 1 to 64 4 and circuits 65 1 and 65 2 other than the output circuits.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した第4図の従来例の各出力回路471
472,473,474において、それらの電源の
入力点A,B,C,Dに生じる電位変化の状況を
第2図の曲線lに示す。すなわち、電源パツド4
1と出力回路471の間、および各出力回路相互
間の電源線43の抵抗値をいずれもRとし、各出
力回路471〜474に入力する電流値をいずれも
Iとすると、A点での電位変化は4IR、B点では
7IR(=4IR+3IR)、C点では9IR(=7IR+2IR)、
D点では10IR(=9IR+1IR)となる。この電位変
化の状況は出力回路481〜484の各入力点にお
いても同様である。また、出力回路以外の回路4
1,492を流れる電流によつても各出力回路4
1〜474,481〜484の入力点電位が変動
し、逆に出力回路以外の回路491,492の電位
も出力回路471〜474,481〜484を流れる
電流の影響を受けて変動する。このように、すべ
ての回路が同一の電源パツドに接続されているた
め、各回路に流れる電流と電源線の配線抵抗によ
つて生ずる電源線の電位変化がすべての回路の特
性に影響を与え、さらに、この電源線の電位変化
は、多ビツトの情報を同時に読出す機能を有する
半導体集積回路においてより大きな影響を与える
という欠点がある。
Each output circuit 47 1 of the conventional example shown in FIG.
47 2 , 47 3 , and 47 4 , the situation of potential changes occurring at the input points A, B, C, and D of those power sources is shown by curve 1 in FIG. That is, power pad 4
1 and the output circuit 47 1 and between each output circuit are R, and the current values input to each of the output circuits 47 1 to 47 4 are I, then point A The potential change at point B is 4IR, and at point B
7IR (=4IR+3IR), 9IR (=7IR+2IR) at point C,
At point D, it becomes 10IR (=9IR+1IR). The situation of this potential change is the same at each input point of the output circuits 48 1 to 48 4 . In addition, circuit 4 other than the output circuit
Each output circuit 4 is also affected by the current flowing through 9 1 and 49 2 .
The input point potentials of 7 1 to 47 4 , 48 1 to 48 4 fluctuate, and conversely, the potentials of circuits 49 1 and 49 2 other than the output circuits also change to the current flowing through the output circuits 47 1 to 47 4 , 48 1 to 48 4 fluctuates under the influence of In this way, since all circuits are connected to the same power supply pad, changes in the potential of the power supply line caused by the current flowing in each circuit and the wiring resistance of the power supply line affect the characteristics of all circuits. Furthermore, this change in the potential of the power supply line has a disadvantage in that it has a greater effect on semiconductor integrated circuits having the function of simultaneously reading multi-bit information.

上述した第5図の従来例は、2個の電源パツド
51,52を用いて出力回路631〜634,64
〜644と出力回路以外の回路651,652を区
分したので相互間の影響は解消されているが、出
力回路631〜634を流れる電流値Iと回路相互
間の配線抵抗値Rによる各出力回路631〜634
電源の入力点E,F,G,Hにおける電位変化の
状況は前例の場合と全く同様で第2図の曲線lで
示され、これは出力回路641〜644についても
同一であり、それらの特性に影響があるという欠
点がある。
In the conventional example shown in FIG .
Since the circuits 1 to 64 4 and the circuits 65 1 and 65 2 other than the output circuit are separated, the influence between them is eliminated, but the current value I flowing through the output circuits 63 1 to 63 4 and the wiring resistance value between the circuits are Each output circuit 63 1 to 63 4 by R
The situation of potential changes at the input points E, F, G, and H of the power supply is exactly the same as in the previous example and is shown by curve l in Fig. 2, and this is also the same for the output circuits 64 1 to 64 4 , The disadvantage is that it affects the characteristics of

〔問題点を解決するための手段〕[Means for solving problems]

本発明による集積回路記憶装置は、互いに同時
に動作する複数の第1の出力回路と、互いに同時
に動作する複数の第2の出力回路であつて前記第
1の出力回路とは同時には動作しない複数の第2
の出力回路と、第1および第2の電源パツドと、
第1および第2の接地パツドとを備え、前記複数
の第1の出力回路は第1および第2のグループに
グループ化され、前記複数の第2の出力回路は第
3および第4のグループにグループ化され、前記
第1のグループ内の第1の出力回路は前記第1の
電源パツドから延びる第1の配線と前記第1の接
地パツドから延びる第2の配線とを介して給電さ
れるように配置され、前記第2のグループ内の第
1の出力回路および前記第3のグループ内の第2
の出力回路は前記第1の電源パツドから前記第1
の配線とは独立して延びる第3の配線と前記第2
の接地パツドから延びる第4の配線とを介して給
電されるように配置され、前記第4のグループ内
の第2の出力回路は前記第2の電源パツドから延
びる第5の配線と前記第2の接地パツドから前記
4の配線とは独立して延びる第6の配線とを介し
て給電されている。
An integrated circuit storage device according to the present invention includes a plurality of first output circuits that operate simultaneously with each other, and a plurality of second output circuits that operate simultaneously with each other, but that do not operate simultaneously with the first output circuit. Second
an output circuit, first and second power pads,
first and second ground pads, the plurality of first output circuits being grouped into first and second groups, and the plurality of second output circuits being grouped into third and fourth groups. and a first output circuit in the first group is powered via a first wire extending from the first power pad and a second wire extending from the first ground pad. a first output circuit in the second group and a second output circuit in the third group;
An output circuit is connected from the first power supply pad to the first power supply pad.
a third wiring that extends independently of the wiring;
A second output circuit in the fourth group is arranged to be supplied with power via a fifth wiring extending from the second power supply pad and a fourth wiring extending from the second power supply pad. Power is supplied from the ground pad through a sixth wiring that extends independently of the fourth wiring.

かかる構成によれば、各電源線上の出力回路の
動作にもとづく電位変化を最小に抑えることがで
き、特性への影響を少なくすることができる。
According to this configuration, potential changes based on the operation of the output circuit on each power supply line can be suppressed to a minimum, and the influence on the characteristics can be reduced.

〔実施例〕〔Example〕

本発明の実施例について図面を参照して説明す
る。
Embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の集積回路記憶装置の一実施例
の有するペレツト上の回路配置を示す平面図、第
2図は本実施例と従来例のおける電源線に生じる
電源電位の変化を示すグラフである。
FIG. 1 is a plan view showing the circuit layout on a pellet of an embodiment of the integrated circuit memory device of the present invention, and FIG. 2 is a graph showing changes in power supply potential occurring in the power supply lines in this embodiment and the conventional example. It is.

2個の電源パツド1,2と2個の接地電位パツ
ド3,4は、それぞれペレツトの四隅に、かつ同
一対角線上に同種のものが配置されている。ま
た、4個の出力回路131〜134の組と他の4個
の出力回路141〜144の組は、両組が同時に動
作しないものとする。出力回路131〜134は1
3,134のグループと131,132のグループ
に分けられている。同様に、出力回路141〜1
4も141,142のグループと143,144のグ
ループに分けられている。出力回路133,134
のグループは電源パツド1から延びる電源線6と
接地電位パツド4から延びる接地線10とを介し
て給電されている。これら電源線6と接地線10
とには出力回路以外の回路17も接続されてい
る。出力回路131,132のグループと出力回路
141,142のグループは電源パツド1からさら
に延びる電源線5と接地電位パツド3から延びる
接地線9とを介して給電されている。そして、出
力回路143,144のグループは電源パツド2か
ら延びる電源線7と接地電位パツド3からさらに
延びる接地線11とを介して給電される。これら
電源線7および接地線11には出力回路以外の回
路15も接続されている。すなわち、各電源線
5,6,7には同時に動作する出力回路が2回路
ずつ(131−132または141−142,133
134,143−144)が接続されている。
The two power supply pads 1, 2 and the two ground potential pads 3, 4 are arranged at each of the four corners of the pellet and on the same diagonal. Further, it is assumed that the set of four output circuits 13 1 to 13 4 and the set of other four output circuits 14 1 to 14 4 do not operate simultaneously. Output circuits 13 1 to 13 4 are 1
It is divided into groups of 3 3 and 13 4 and groups of 13 1 and 13 2 . Similarly, the output circuits 14 1 to 1
4 4 is also divided into groups of 14 1 and 14 2 and groups of 14 3 and 14 4 . Output circuit 13 3 , 13 4
The groups are supplied with power via a power line 6 extending from the power pad 1 and a ground line 10 extending from the ground potential pad 4. These power line 6 and ground line 10
A circuit 17 other than the output circuit is also connected to. The group of output circuits 13 1 , 13 2 and the group of output circuits 14 1 , 14 2 are supplied with power via a power line 5 extending further from the power pad 1 and a ground line 9 extending from the ground potential pad 3. The group of output circuits 14 3 and 14 4 is supplied with power via a power line 7 extending from the power pad 2 and a ground line 11 further extending from the ground potential pad 3. A circuit 15 other than the output circuit is also connected to the power supply line 7 and the ground line 11. That is, each power supply line 5, 6, 7 has two output circuits (13 1 - 13 2 or 14 1 - 14 2 , 13 3 -
13 4 , 14 3 -14 4 ) are connected.

以上の配置をとることにより、本実施例におけ
る電源電位の変化は、例えば電源線5上の各出力
回路131,132,141,142の各入力点J,
M,L,Mにおいて出力回路141,142の動作
時についてみれば、各回路を流れる電流をI、各
回路相互間および電源パツド1との間の電源線5
の抵抗値Rとして、点Jでは2IR、点Kでは4IR
(=2IR+2IR)、点Lでは6IR(=4IR+2IR)、点
Mでは7IR(=6IR+1IR)となり第2図の曲線m
に示され、従来例の場合の曲線lに対して大幅に
減少している。また、出力回路以外の回路17に
対する影響についても、電源線6上の出力回路1
3,134の入力点N,Pについてみれば、第2
図の曲線nで示すように点Nでは2IR、点Pでは
3IR(=2I+1IR)となり、従来例のC点、D点に
おける変化値に比較して大幅に改善されているこ
とが分る。
By adopting the above arrangement, changes in the power supply potential in this embodiment can be controlled, for example, at each input point J of each output circuit 13 1 , 13 2 , 14 1 , 14 2 on the power supply line 5
Looking at the operation of the output circuits 14 1 and 14 2 in M, L, and M, the current flowing through each circuit is I, and the power line 5 between each circuit and between the power supply pad 1
The resistance value R is 2IR at point J and 4IR at point K.
(=2IR+2IR), 6IR (=4IR+2IR) at point L, 7IR (=6IR+1IR) at point M, and the curve m in Figure 2.
, which is significantly reduced compared to the curve 1 for the conventional example. Also, regarding the influence on circuits 17 other than the output circuit, the output circuit 1 on the power supply line 6
Looking at the input points N and P of 3 3 and 13 4 , the second
As shown by curve n in the figure, 2IR at point N and 2IR at point P.
3IR (=2I+1IR), which is a significant improvement compared to the change values at points C and D in the conventional example.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、互いに同時に
動作する複数の第1出力回路を第1、第2グルー
プに分け、互いに同時に動作するが第1出力回路
とは同時には動作しない複数の第2出力回路を第
3、第4グループに分け、第1グループの出力回
路を第1電源パツドおよび第1接地パツドからそ
れぞれ延びる配線により給電し、第2グループの
出力回路および第3グループの出力回路を上記第
1電源パツドおよび第2接地パツドからそれぞれ
延びる配線により給電し、そして第4グループの
出力回路を第2電源パツドおよび第2接地パツド
からそれぞれ延びる配線により給電しており、こ
れによつて、出力回路に流れる電流と電源線の配
線抵抗によつて生ずる電源線の電位変化を小さく
しており、同一電源線に接続されている回路相互
間の特性に与える影響を軽減することができる効
果がある。
As explained above, the present invention divides a plurality of first output circuits that operate simultaneously with each other into first and second groups, and provides a plurality of second output circuits that operate simultaneously with each other but do not operate simultaneously with the first output circuit. The circuits are divided into third and fourth groups, and the output circuits of the first group are supplied with power by wiring extending from the first power supply pad and the first ground pad, respectively, and the output circuits of the second group and the output circuits of the third group are supplied with power as described above. Power is supplied by wiring extending from the first power supply pad and the second grounding pad, respectively, and power is supplied to the output circuits of the fourth group by wiring extending from the second power supply pad and the second grounding pad, respectively. It reduces potential changes in the power line caused by the current flowing in the circuit and the wiring resistance of the power line, and has the effect of reducing the effect on the characteristics of circuits connected to the same power line. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の集積回路記憶装置の一実施例
の有するペレツト上の回路配置を示す平面図、第
2図は本実施例と従来例における電源線に生じる
電源電位の変化を示すグラフ、第3図は従来の集
積回路記憶装置(DIP型)内部のペレツトとリー
ド線の配置例を示す図、第4図および第5図は従
来の集積回路記憶装置のペレツトの配置例を示す
平面図である。 1,2……電源パツド、3,4……接地電位パ
ツド、5,6,7,8……電源線、9,10,1
1,12……接地線、131〜134,141〜1
4……出力回路、15,16,17……出力回
路以外の回路、J,K,L,M,N,P……出力
回路の電源の入力点、l、m,n……電位変化の
曲線。
FIG. 1 is a plan view showing the circuit arrangement on a pellet of an embodiment of the integrated circuit storage device of the present invention, and FIG. 2 is a graph showing changes in power supply potential occurring in the power supply line in this embodiment and the conventional example. FIG. 3 is a diagram showing an example of the arrangement of pellets and lead wires inside a conventional integrated circuit storage device (DIP type), and FIGS. 4 and 5 are plan views showing examples of the arrangement of pellets in a conventional integrated circuit storage device. It is. 1, 2... Power pad, 3, 4... Ground potential pad, 5, 6, 7, 8... Power line, 9, 10, 1
1, 12... Ground wire, 13 1 ~ 13 4 , 14 1 ~ 1
4 4 ... Output circuit, 15, 16, 17... Circuit other than the output circuit, J, K, L, M, N, P... Input point of the power supply of the output circuit, l, m, n... Potential change curve.

Claims (1)

【特許請求の範囲】[Claims] 1 互いに同時に動作する複数の第1の出力回路
と、互いに同時に動作する複数の第2の出力回路
であつて前記第1の出力回路とは同時には動作し
ない複数の第2の出力回路と、第1および第2の
電源パツドと、第1および第2の接地パツドとを
備え、前記複数の第1の出力回路は第1および第
2のグループにグループ化され、前記複数の第2
の出力回路は第3および第4のグループにグルー
プ化され、前記第1のグループ内の第1の出力回
路は前記第1の電源パツドから延びる第1の配線
と前記第1の接地パツドから延びる第2の配線と
を介して給電されるように配置され、前記第2の
グループ内の第1の出力回路および前記第3のグ
ループ内の第2の出力回路は前記第1の電源パツ
ドから前記第1の配線とは独立して延びる第3の
配線と前記第2の接地パツドがら延びる第4の配
線とを介して給電されるように配置され、前記第
4のグループ内の第2の出力回路は前記第2の電
源パツドから延びる第5の配線と前記第2の接地
パツドから前記4の配線とは独立して延びる第6
の配線とを介して給電されることを特徴とする集
積回路記憶装置。
1 A plurality of first output circuits that operate simultaneously with each other, a plurality of second output circuits that operate simultaneously with each other but that do not operate simultaneously with the first output circuit, first and second power pads and first and second ground pads, the plurality of first output circuits are grouped into first and second groups, and the plurality of second output circuits are grouped into first and second groups;
output circuits are grouped into third and fourth groups, and a first output circuit in the first group has a first wiring extending from the first power pad and a first wiring extending from the first ground pad. A first output circuit in the second group and a second output circuit in the third group are arranged to be supplied with power via a second wiring, and a first output circuit in the second group and a second output circuit in the third group are connected to the a second output in the fourth group arranged to be supplied with power via a third wire extending independently of the first wire and a fourth wire extending from the second ground pad; The circuit includes a fifth wire extending from the second power supply pad and a sixth wire extending from the second ground pad independently of the fourth wire.
An integrated circuit storage device characterized in that power is supplied through the wiring.
JP1268187A 1987-01-21 1987-01-21 Integrated circuit storage device Granted JPS63179560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1268187A JPS63179560A (en) 1987-01-21 1987-01-21 Integrated circuit storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1268187A JPS63179560A (en) 1987-01-21 1987-01-21 Integrated circuit storage device

Publications (2)

Publication Number Publication Date
JPS63179560A JPS63179560A (en) 1988-07-23
JPH0573272B2 true JPH0573272B2 (en) 1993-10-14

Family

ID=11812121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1268187A Granted JPS63179560A (en) 1987-01-21 1987-01-21 Integrated circuit storage device

Country Status (1)

Country Link
JP (1) JPS63179560A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01139437U (en) * 1988-03-18 1989-09-22

Also Published As

Publication number Publication date
JPS63179560A (en) 1988-07-23

Similar Documents

Publication Publication Date Title
JP3433731B2 (en) I / O cell arrangement method and semiconductor device
JPS62244144A (en) Semiconductor device
JPH0621320A (en) Semiconductor integrated circuit device
JPS63299513A (en) Output circuit
JPH05308136A (en) Master slice integrated circuit
US5751051A (en) Semiconductor device equipped with electrostatic breakdown protection circuit
JPH03133174A (en) Semiconductor storage device
JPH09306940A (en) Semiconductor device
JPH0573272B2 (en)
JP2917703B2 (en) Semiconductor integrated circuit device
KR930010104B1 (en) Semiconductor integrated circuit
US6060946A (en) Semiconductor device having improved immunity to power supply voltage fluctuations
JPS58124262A (en) Integrated circuit device
JPS6161256B2 (en)
JPH04177846A (en) Semiconductor device
JPH0377666B2 (en)
JPH0550143B2 (en)
JP2919265B2 (en) Semiconductor device
JPH0448773A (en) Semiconductor integrated circuit device
JPH0774259A (en) Semiconductor memory device
JPH0416945B2 (en)
JPH0749803Y2 (en) Pin layout structure of integrated circuit
JPH0626224B2 (en) Package for integrated circuit
JP2003318263A (en) Semiconductor device
JPS63107316A (en) Clock distribution structure of gate array

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees