JPS63107316A - Clock distribution structure of gate array - Google Patents

Abstract

PURPOSE:To decrease skew more by providing a clock bus wiring so as to surround a block receiving a signal and applying wiring from a clock driver so as to be a lattice thereby decreasing the equivalent distribution capacitance and wire resistance of the clock bus wiring. CONSTITUTION:The clock bus 3 through which a clock signal is supplied from the clock driver 1 is wired to surround the circuit block 2 such as a D-FF or plural circuit blocks 2. The clock bus 3 consists of a 1st layer wiring shown in solid lines and a 2nd layer wiring shown in dotted lines. A clock signal is supplied to a clock terminal of each circuit block 2 through the 1st lateral wire and the 2nd longitudinal layer wire connected to the clock bus 3. Since each wiring series is connected by resistive components 34, 35 in the equivalent circuit of the clock bus 3 of the circuit above, the difference from the transmission time of clock signals between the wire series is small and the dispersion in the chip of the clock skew is lowerd. Moreover, since the wiring is formed substantially as a lattice, the current is distributed and this structure is advantages to the migration of the wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a structure for distributing a clock to a gate array.

[Conventional technology]

In recent years, among semiconductor integrated circuits, the market for gate arrays has been rapidly expanding because desired circuit functions can be realized in a short lead time, and switching speeds and scale have rapidly increased. It is coming.

Among these gate arrays, CMOS gate arrays in particular are becoming larger in scale due to their low power consumption.
Gate arrays with 20 to 40 gates are currently on the market. Conventional gate arrays of this type have 70 D-7 lips (hereinafter referred to as D
-FF), shift register, counter circuit, etc., are almost always used.
A circuit is configured by wiring (not shown) between these circuit blocks 2. Clock signals may be supplied externally or generated internally, and such clock signals are supplied to each circuit block 2 via a clock driver 1.

Selection of circuit block 2 of gate array and circuit block 2
Wiring between the two is generally done automatically using CAD technology. FIG. 5 shows an example of wiring results for automatic selection of circuit block 2 and clock signal supply. The selected circuit block 2, such as the clock driver 1 or D-FF, which requires clock input, is connected in the horizontal direction by the first layer wiring shown by the solid line, and in the vertical direction is connected by the 2i wiring shown by the dotted line.
It is connected by the iith wiring. In the circuit realized as the gate array shown in FIG. 4, wiring resistance and
The electrical equivalent circuit from the clock driver 1 is represented as shown in FIG. 6, including parasitic wiring capacitance, block input capacitance, through-hole resistance, etc. Therefore, when looking at the wiring for supplying the clock as a whole, it is necessary to consider it as a distributed constant circuit. In FIG. 6, 20 to 23 represent nodes in the middle of the clock wiring, 30 to 33 represent resistances such as wiring resistances and through-hole resistances, and 40 to 43 represent wiring capacitances and input terminal capacitances of each block.

[Problem that the invention seeks to solve]

Therefore, in the conventional clock signal supply wiring, nodes 20 and 2
Comparing the transmission time of the clock signal at node 21 and node 21,
is larger, and similarly comparing the contacts 21 and 22, the transmission time of the clock signal at the node 22 is longer. That is,
A problem arises in that the longer the wiring, the greater the difference in clock signal transmission time between the immediate vicinity of the clock driver 1 and a location further away from the clock driver 1.

Generally, in a circuit using a clock signal, the smaller the difference in clock signal transmission time between circuit blocks as described above, the better; if it becomes large, the gate array will no longer be able to perform the intended circuit function. This difference in transmission time is generally called skew.

Aluminum is generally used as the wiring material in gate arrays, and although the layer resistance of aluminum is not very large, the through-hole resistance in multilayer wiring can be as large as several ohms to several tens of ohms. The problem with skew is that as the chip size increases, the wiring becomes longer and the number of through holes increases, so the problem worsens rapidly.

Therefore, an object of the present invention is to provide a clock signal distribution structure with small clock skew.

[Means for solving the starting point]

The clock distribution structure of the present invention has clock bus wiring surrounding blocks to which clock signals are supplied, and this clock bus wiring is connected to clock terminals of each circuit block. Preferably, the clock bus wiring is arranged in a grid pattern.

According to the present invention, the equal number of songs distributed in the clock bus wiring and the wiring resistance are reduced, so that skew can be further reduced.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an example of wiring according to an embodiment of the present invention. A clock bus 3 that supplies clock signals from a clock driver 1 is wired so as to surround a circuit block 2 or a plurality of circuit blocks 2 such as a D-FF. The clock bus 3 is composed of a first layer wiring shown by a solid line and a second layer wiring shown by a dotted line. A clock signal is supplied to the clock terminal of each circuit block 2 by the wiring connected to the clock bus 3 through the first layer wiring in the horizontal direction and the 2r@th wiring in the vertical direction. If the circuit of Fig. 1 is expressed as a number, such as Kvass 3, it will look like the equivalent circuit diagram of the second prisoner. In the figure,
30-33.30'-33'.

30" to 33" and 34.35 represent resistance components due to wiring, through holes, etc. 40～43゜40′～
43', 40'' to 43'' represent capacitance 1 components such as wiring capacitance and block input capacitance.

34 and 35 represent connection points between the clock buses 3. Therefore, even though each wiring series is connected by the resistance component 34.35, the difference in clock signal transmission time between the wiring series becomes small, and the variation in the clock skew within the chip is reduced.

In addition, since the wiring is essentially in the form of a grid, the current
It also has the advantage of being advantageous against wiring misalignment because it is dispersed.

FIG. 3 is a block diagram showing another embodiment of the present invention. The clock driver 1 is an example in which one or more of the circuit blocks 2 such as D-FFs are provided outside the wiring of the recessed clock bus 3. In this case as well, the skew from the clock driver 1 can be suppressed within the chip by wiring in a grid pattern, similar to the embodiment shown in FIG.

In one embodiment shown in FIG. 1, the clock driver is located almost in the center, so there is almost no difference in skew at the periphery, whereas in the other embodiment shown in AfJ3, the clock driver is located on the outside of the clock bus 3 wiring. Because of the presence of the clock driver 1, the clock skew becomes much larger in areas far from the clock driver 1, but the clock bus 3 suppresses black and white noise to a certain extent. Further, in a gate array, an input/output block with a large output capacity, which is usually provided on the periphery of a chip, can be used as the clock driver 1, and there is an advantage that the lock driver 1 can be configured to be powerful and drive a large number of loads.

〔Effect of the invention〕

As explained above, the present invention provides a gate array with less clock skew by setting the clock bus wiring so as to surround the processors to which signals are supplied, and by wiring from the clock driver in a grid pattern. can be realized.

Furthermore, since concentration of current can be avoided by wiring in a grid pattern, it is also advantageous for wiring migration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the wiring structure of a clock bus 1 according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the clock path wiring structure shown in FIG. 1, and FIG. FIG. 4 is a circuit conceptual diagram showing a conventional clock signal supply structure, FIG. 5 is a block diagram showing a conventional clock signal supply structure, and FIG. FIG. 6 is an equivalent circuit diagram of the clock signal supply structure shown in FIG. 5; 1...Black, driver, 2...Circuit block, 3...Clock lotus, 20-23
・・・・・・Node of clock wiring, 30~35.30'
~33', 30''~33''... Parasitic resistance, 40
~43,40"~43",40"~43"...
Parasitic Capacity Camellia / Figure 2, Figure 3, Figure 4, Figure 15, Figure O

Claims (1)

[Claims] 1. A semiconductor integrated circuit has a clock driver, a circuit block, and a clock bus to which a clock signal supplied from the clock driver is applied, and the clock bus is connected to one or more of the circuit blocks. A gate array clock distribution structure characterized by wiring that surrounds the gate array. 2. The gate array clock distribution structure according to claim 1, wherein the clock buses are arranged in a grid pattern.