JPH0445573A - Master slice type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To change the resistance value by the wiring process alone by fixing the source region of a Pch transistor to vdd potential, and connecting the drain regions of one or more Pch transistors with an input terminal electrically. CONSTITUTION:The signal inputted from outside a chip is inputted from an input terminal 104 to the gate electrode of Pch transistor 102 and the gate electrode of an Nch transistor 103, and is connected to the following stage from a terminal 105. For a Pch transistor for pull-up, in the condition that the source diffusion area is fixed to high potential vdd and that the gate electrode is fixed to low potential vss, the drain diffusion area is electrically connected to the input terminal. Accordingly, the resistance value of a transistor for pull up is constant. Thereupon, in the logical circuit based the potential vss, in the case that there is no input signal, the resistance value, which makes the potential vdd into potential vss, can be changed by wiring process alone according to the quantity of the currents of the input signal of the circuit, while maintaining the potential of the input terminal always at vdd. Moreover, by the arrangement structure of the transistor by this invention, the resistance value can be changed with no influence on the wiring of other logical constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a master slice integrated circuit, and more particularly to the configuration of a pull-up resistor transistor.

(Prior Art) In a master slice type gate array that realizes a dedicated logic circuit by changing only the wiring process, if the realized dedicated logic circuit is a circuit that operates based on the potential of vs5,
In order to input a fixed input voltage unrelated to the operation of the circuit at an input terminal where the input potential to the circuit is not fixed, a resistor existing outside the chip or a fixed resistor or a fixed transistor existing inside the chip is used at the input terminal. There is a method of electrically supplying the potential of vdd using only one.

(Problem M to be solved by the invention) However, when a resistor external to the chip is electrically connected to the input terminal using the conventional method, the wiring around the chip becomes complicated, and the mounting efficiency including the chip becomes difficult. decreases. In addition, when electrically connecting to the input terminal using only one resistor and transistor existing inside the chip, the resistance value of the resistor or transistor connected to the input terminal can be determined by a dedicated logic circuit using a master slice type gate array. The problem is that it is difficult to change only the wiring process when realizing this.

The present invention is intended to solve these problems, and its purpose is to provide a transistor whose resistance value can be changed only by the wiring process when realizing a dedicated logic circuit with a master slice type gate array. The purpose is to provide configuration.

(Means for Solving the Problems) A master slice type semiconductor integrated circuit device of the present invention includes: a) a master slice type gate in which basic cells configuring logic and basic cells configuring input/output logic are regularly arranged; In the basic cells constituting the input/output logic in the array, b) a Pch l- whose input terminal, into which a signal from outside the chip is input, and a gate electrode are electrically connected by metal wiring;
C) a plurality of Pch transistors each having an electrically isolated source diffusion region and an electrically isolated drain diffusion region and whose gate electrode is fixed at the potential of vss; d) the channel direction of the Pch transistor is arranged parallel to the direction of the metal wiring electrically connecting the input terminal and the gate electrode; e) a plurality of the Pch transistors with gate electrodes fixed at vss;
The source region of at least one of the Pch transistors among the h transistors is fixed at a potential of vdd, and the drain region of the at least one Pch transistor is electrically connected to the input terminal.

(Embodiment) FIG. 1 shows a logic circuit diagram of a conventional structure of a pull-up transistor, an input terminal, and a transistor electrically connected to the input terminal. Signals input from outside the chip are input from the input terminal 104 to the gate electrode of the Pch transistor 102 and the gate ti of the Nch transistor 103.
The drain diffusion region is electrically connected to the input terminal while the input voltage is fixed at b vdd and the gate electrode is fixed at the potential vss. Therefore, the resistance value of the pull-up transistor is constant.

FIG. 2 shows a logic circuit diagram of the pull-up transistor of the present invention, and FIG. 3 shows a layout diagram of the pull-up transistor of the present invention. 201 in FIG. 2 is 202.204.2.
Shows the entire multiple pull-up transistors of 05*
P c h ) The potential vdd of the transistor 202 is
Vdd 207 connected to the source region 7 corresponds to the drain region of the diffusion region 307 in FIG. Each second
Terminals 203.206.208.209 in the figure correspond to the source or drain regions of the diffusion regions 306.305 in FIG. In addition, in FIG. 3, gate electrodes 302, 303, and 304 are supplied with a potential of vss. In the present invention, metal wiring for connecting the input terminal, the gate electrode of the Pch transistor, and the gate electrode of the Nch transistor 301 (hereinafter referred to as input metal wiring layer), the diffusion region 305.3 of the Pch transistor
06.307 is arranged in a direction in which the channel directions are parallel. Further, FIG. 3 shows an example in which the source region of the diffusion region 307 is fixed at the potential of vdd.

FIG. 4 shows a layout example of two Pch transistors connected in series according to the invention, and FIG. 5 shows a layout example of two Pch transistors connected in parallel according to the invention. In FIG.
The transistor has its channel direction aligned with the input metal wiring.
1. Also, 406 is metal wiring,
407 indicates a, and 501, 5021.9 in Figure 5
゜507 is 401.4022. in Figure 4. ,．． Corresponds to 407. In Figure 4, the two Pch transistors are connected by a pattern 409 consisting of metal wiring, connecting the drain region of diffusion region #5405 and the source region of diffusion region 404, and consisting of vias and metal wiring. 40
The drain region of the diffusion region 404 is connected to the input metal wiring 401 by the pattern No. 8. Since the Pch transistor is an element with resistance, by connecting it in series, Vdd
The resistance value of the diffusion region and the front input metal interconnection 1I401 having a potential of is twice the resistance value of the Pch transistor. In FIG. 5, the source region of the diffusion region 505 and the source region of the diffusion region 504 are connected by a pattern 508 composed of two Pch transistors and a metal wiring. be done 5
The drain region of the diffusion region 505 according to the pattern 09,
The drain region of the diffusion region 504 is connected to the input metal layer! ll
1501. Due to the parallel connection, the resistance value between the diffusion region having the potential of vdd and the input metal wiring layer 501 becomes 172 times the resistance value of the Pch transistor.

The pattern 408, 409, 508, 509 can be manufactured by only a wiring process in a master slice type semiconductor integrated circuit device. Further, the pattern is a simple pattern extending only in the direction perpendicular to the input metal wiring layer, so that the resistance value can be changed without affecting the wiring constituting other logics.

(Effects of the Invention) As described above, according to the present invention, when there is no input signal in a logic circuit based on the potential V-SS, the potential of the input terminal is always kept at Vdd, and the input signal of the circuit is The resistance value for changing the potential vdd to the potential vss can be changed only by the wiring process in accordance with the 'R flow rate. Further, the arrangement structure of the transistor of the present invention has the effect that the resistance value can be changed without affecting the wiring of other logic configurations.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram of a conventional pull-up transistor, an input terminal, and a transistor electrically connected to the input terminal. FIG. 2 is a logic circuit diagram of the pull-up transistor of the present invention, and FIG. 3 is a layout diagram of the pull-up transistor of the present invention. FIG. 4 is a diagram showing a layout example of two Pch transistors connected in series according to the present invention, and FIG. 5 is a diagram showing a layout example of two Pch transistors connected in parallel according to the present invention. 101.202.204.205 , , Pull-up Pch transistor 104 , , Input terminal 105 , , Output terminal 102 , , Input signal receiving Pch transistor 103 , , Input signal receiving Nchl-transistor 203, 206, 207, 208, 209 Pch transistor source region and diffusion region terminal for pull-up 301.401.501 , Input metal wiring 30
2.303.304.402.403.502.503
,, Pch transistor gate a for pull-up
i 305, 306, 307, 404, 405.504.5
05 ,, Pull-up Pch transistor diffusion region 308.407.507 309.310.311. 506, Metal wiring 408.409.508, Wiring pattern for parallel connection, Via 312, 406, Series, Applicant Seiko Epson Corporation Representative Patent attorney Kizobe Suzuki 1 person Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] a) In a basic cell forming the input/output logic in a master slice type gate array in which basic cells forming the logic and basic cells forming the input/output logic are arranged regularly. b) Pch transistors and Nch transistors in which an input terminal into which a signal from outside the chip is input and a gate electrode are electrically connected by metal wiring, and c) an electrically isolated source diffusion region and an electrically isolated source diffusion region. d) a plurality of Pch transistors each having a drain diffusion region with a gate electrode fixed at a potential of vss, and d) a channel direction of the Pch transistor electrically connecting the input terminal and the gate electrode; e) a plurality of the Pcs whose gate electrodes are fixed at vss;
The source region of one or more of the Pch transistors among the h transistors is fixed to the potential of vdd, and one or more of the Pch transistors
A master slice type semiconductor integrated circuit device, characterized in that a drain region of a channel transistor and the input terminal are electrically connected.