JPH0520514A - Ic card - Google Patents

Ic card

Info

Publication number
JPH0520514A
JPH0520514A JP3169773A JP16977391A JPH0520514A JP H0520514 A JPH0520514 A JP H0520514A JP 3169773 A JP3169773 A JP 3169773A JP 16977391 A JP16977391 A JP 16977391A JP H0520514 A JPH0520514 A JP H0520514A
Authority
JP
Japan
Prior art keywords
input
card
memory
terminal
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3169773A
Other languages
Japanese (ja)
Inventor
Atsushi Okuma
敦 大熊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seikosha KK
Original Assignee
Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seikosha KK filed Critical Seikosha KK
Priority to JP3169773A priority Critical patent/JPH0520514A/en
Publication of JPH0520514A publication Critical patent/JPH0520514A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772Physical layout of the record carrier
    • G06K19/07732Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

PURPOSE:To provide the IC card in which the storage capacity of one IC card is increased and the number of terminals of the IC card is made approximately equal to that in the case of one IC card by providing plural IC memories in one IC card. CONSTITUTION:When an IC card 1 provided with two IC memories 2 and 3 is set to an external input/output means 13, IC memories to be used are selected in accordance with the inserting direction of the IC card, and a switching means switches first input/output terminals 5 to 7 and second input/output terminals 10 to 12 to an address input terminal and a data output terminal. Thus, the number of terminals of the IC card provided with two IC memories is approximately equal to that of the IC card provided with one IC memory.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、選択可能な複数のIC
メモリを有するICカードに関するものである。
BACKGROUND OF THE INVENTION The present invention relates to a plurality of selectable ICs.
The present invention relates to an IC card having a memory.

【0002】[0002]

【従来の技術】従来のICカードは、カード1枚につき
ICメモリを1つ有するものである。
2. Description of the Related Art A conventional IC card has one IC memory for each card.

【0003】[0003]

【発明の効果】上記のものでは、カード1枚の記憶容量
がICメモリ1個の記憶容量しかもたなかった。そこで
カードの両面にICメモリを設けて記憶容量を増加させ
ることが考えられるが、その場合ICカードの端子数が
2倍に増加してしまう。
In the above, the storage capacity of one card was only the storage capacity of one IC memory. Therefore, it is conceivable to provide an IC memory on both sides of the card to increase the storage capacity, but in that case, the number of terminals of the IC card will double.

【0004】本発明の目的は、端子数の増大を招来する
ことなく記憶容量を増加することにある。
It is an object of the present invention to increase the storage capacity without increasing the number of terminals.

【0005】[0005]

【課題を解決するための手段】カードの両面にICメモ
リを設け、カードに設けた2組の入出力端子が外部の2
組の端子(アドレス信号出力端子とデータ信号入力端
子)と接続する際の2通りの組合わせによって、カード
の両面に設けた2つのICメモリからどちらか一方のI
Cメモリを選択することにより、上記目的を達成してい
る。
Means for Solving the Problems IC memories are provided on both sides of a card, and two sets of input / output terminals provided on the card are external
Two IC memories provided on both sides of the card can be used to select either one of the I and
The above object is achieved by selecting the C memory.

【0006】[0006]

【実施例】以下、この発明を図面に示す一実施例に基い
て具体的に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to an embodiment shown in the drawings.

【0007】図1において、1はICカード、2および
3はICメモリでICカードの両面にそれぞれ設けてあ
る。4〜12はICカードの端子で、4はICメモリ2
のVDD電源端子、5〜7は第1の入出力端子であり、I
Cメモリ2を使用するときはアドレス入力端子としてI
Cメモリ3を使用するときはデータ出力端子として動作
する。8はICメモリ2とICメモリ3とに共通な電源
端子でアースと接続する。9はICメモリ3のVDD電源
端子、10〜12は第2の入出力端子で、ICメモリ2
を使用するときはデータ出力端子としてICメモリ3を
使用するときはアドレス入力端子として動作する。13
は外部入出力手段を構成するカード装着部で、ICメモ
リ内のデータを利用する電気機器の一部に設けられてい
る。14はVDD電源端子である。15〜17はアドレス
信号出力端子でアドレス信号をICカードへ送る。18
は電源端子でアースしてある。19〜21はデータ信号
入力端子でICカードより出力したデータ信号を受け取
る。22は電源端子でアースしてある。
In FIG. 1, 1 is an IC card, and 2 and 3 are IC memories, which are provided on both sides of the IC card. 4 to 12 are terminals of the IC card, 4 is the IC memory 2
VDD power supply terminal, 5 to 7 are first input / output terminals, and
When using the C memory 2, I is used as an address input terminal.
When the C memory 3 is used, it operates as a data output terminal. Reference numeral 8 is a power supply terminal common to the IC memory 2 and the IC memory 3 and is connected to the ground. Reference numeral 9 is a VDD power supply terminal of the IC memory 3, and 10 to 12 are second input / output terminals.
When the IC memory 3 is used, it operates as a data output terminal, and when the IC memory 3 is used, it operates as an address input terminal. Thirteen
Is a card mounting portion that constitutes an external input / output means, and is provided in a part of an electric device that uses data in the IC memory. 14 is a VDD power supply terminal. Reference numerals 15 to 17 are address signal output terminals for sending address signals to the IC card. 18
Is grounded at the power supply terminal. Data signal input terminals 19 to 21 receive the data signal output from the IC card. 22 is a power supply terminal which is grounded.

【0008】図2は上記ICメモリと入出力端子との間
に設けた切換手段及び全体の配線を示してある。同図に
おいて、23および24は切換手段を構成する切換回路
である。25〜36は切換回路を構成する3ステートゲ
ートである。電源端子14とICメモリ2の電源端子4
が接続しICメモリ3の電源端子9が電源端子14と接
続しない場合、切換回路23は第1の入出力端子5〜7
をICメモリ2のアドレス入力端子に切換え、切換回路
24は第2の入出力端子10〜12をICメモリ2のデ
ータ出力端子に切換える。また、電源端子14とICメ
モリ3の電源端子9が接続しICメモリ2の電源端子4
が電源端子14と接続しない場合、切換回路23は第1
の入出力端子5〜7をICメモリ3のデータ出力端子に
切換え、切換回路24は第2の入出力端子10〜12を
ICメモリ3のアドレス入力端子に切換える。なお、図
1と同一番号は同一のものとする。
FIG. 2 shows switching means provided between the IC memory and the input / output terminal and the entire wiring. In the figure, reference numerals 23 and 24 are switching circuits which constitute switching means. Numerals 25 to 36 are three-state gates forming a switching circuit. Power supply terminal 14 and power supply terminal 4 of IC memory 2
And the power supply terminal 9 of the IC memory 3 is not connected to the power supply terminal 14, the switching circuit 23 operates the first input / output terminals 5-7.
To the address input terminal of the IC memory 2, and the switching circuit 24 switches the second input / output terminals 10 to 12 to the data output terminal of the IC memory 2. Further, the power supply terminal 14 and the power supply terminal 9 of the IC memory 3 are connected to each other, and the power supply terminal 4 of the IC memory 2 is connected.
Is not connected to the power supply terminal 14, the switching circuit 23
The input / output terminals 5 to 7 are switched to the data output terminals of the IC memory 3, and the switching circuit 24 switches the second input / output terminals 10 to 12 to the address input terminals of the IC memory 3. The same numbers as in FIG. 1 are the same.

【0009】つぎに動作について図1および図2を参照
にして説明する。
Next, the operation will be described with reference to FIGS. 1 and 2.

【0010】最初に、ICカード1を図1のの向きで
カード装着部13に挿入する場合の動作を説明する。
First, the operation of inserting the IC card 1 into the card mounting portion 13 in the direction shown in FIG. 1 will be described.

【0011】この場合、電源端子14はICメモリ2の
電源端子4と接続しICメモリ2に電源を供給するが、
ICメモリ3の電源端子9は電源端子14と接続しない
ためICメモリ3には電源が供給されない。すなわちI
Cメモリ2が選択される。電源端子4がVDDとなること
により、切換回路23、24内の3ステートゲート2
5、27、29、31、33、35が開き、3ステート
ゲート26,28,30,32,34,36は閉じる。
上記の動作により第1の入出力端子5〜7はアドレス信
号入力端子に、第2の入出力端子10〜12はデータ出
力端子に切り換わる。よって電気機器内のCPU(図示
せず。)からのアドレス信号を第1の入出力端子5〜7
で受け取りICメモリ2に送りICメモリ2からのデー
タ出力を第2の入出力端子10〜12よりデータ入力端
子19〜21へ送る。
In this case, the power supply terminal 14 is connected to the power supply terminal 4 of the IC memory 2 to supply power to the IC memory 2.
Since the power supply terminal 9 of the IC memory 3 is not connected to the power supply terminal 14, no power is supplied to the IC memory 3. Ie I
The C memory 2 is selected. When the power supply terminal 4 becomes VDD, the 3-state gate 2 in the switching circuits 23 and 24
5, 27, 29, 31, 33, 35 are opened and the three-state gates 26, 28, 30, 32, 34, 36 are closed.
By the above operation, the first input / output terminals 5 to 7 are switched to address signal input terminals and the second input / output terminals 10 to 12 are switched to data output terminals. Therefore, the address signal from the CPU (not shown) in the electric device is transmitted to the first input / output terminals 5 to 7
The data output from the IC memory 2 is sent from the second input / output terminals 10-12 to the data input terminals 19-21.

【0012】次に、ICカード1を図1のの向きでカ
―ド装着部13に挿入する場合の動作を説明する。
Next, the operation of inserting the IC card 1 into the card mounting portion 13 in the direction shown in FIG. 1 will be described.

【0013】この場合、電源端子14はICメモリ3の
電源端子9と接続しICメモリ3に電源を供給するが、
ICメモリ2の電源端子4は電源端子14と接続しない
ためICメモリ2には電源が供給されない。すなわちI
Cメモリ3を選択する。電源端子9がVDDになることに
より切換回路23、24内の3ステートゲート25、2
7、29、31、33、35が閉じ、3ステートゲート
26,28,30,32,34,36は開く。上記の動
作により第1の入出力端子5〜7はデータ出力端子に、
第2の入出力端子10〜12はアドレス信号入力端子に
切り換わる。よってアドレス信号を第2の入出力端子1
0〜12で受け取りICメモリ2に送りICメモリ2か
らのデータ出力を第1の入出力端子5〜7よりデータ入
力端子19〜21へ送る。
In this case, the power supply terminal 14 is connected to the power supply terminal 9 of the IC memory 3 to supply power to the IC memory 3.
Since the power supply terminal 4 of the IC memory 2 is not connected to the power supply terminal 14, no power is supplied to the IC memory 2. Ie I
C memory 3 is selected. When the power supply terminal 9 becomes VDD, the three-state gates 25, 2 in the switching circuits 23, 24
7, 29, 31, 33, 35 are closed and the three-state gates 26, 28, 30, 32, 34, 36 are open. By the above operation, the first input / output terminals 5 to 7 are data output terminals,
The second input / output terminals 10 to 12 are switched to address signal input terminals. Therefore, the address signal is sent to the second input / output terminal 1
The data output from the IC memory 2 is sent from the first input / output terminals 5 to 7 to the data input terminals 19 to 21.

【0014】[0014]

【発明の効果】以上詳述したように本発明のICカード
はICメモリを複数設けることによりICカード1枚の
記憶容量を増大でき、しかもICカードの端子数はほと
んど増やさないですむ。
As described in detail above, the IC card of the present invention can increase the storage capacity of one IC card by providing a plurality of IC memories, and the number of terminals of the IC card hardly increases.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す構成図である。FIG. 1 is a configuration diagram showing an embodiment of the present invention.

【図2】ICカード内の回路図である。FIG. 2 is a circuit diagram inside the IC card.

【符号の説明】[Explanation of symbols]

2、3 ICメモリ 5、6、7 第1の入出力端子 10、11、12 第2の入出力端子 13 外部入出力手段 15、16、17 アドレス信号出力端子 19、20、21 データ信号入力端子 23、24 切換手段 2, 3 IC memory 5, 6, 7 First input / output terminal 10, 11, 12 Second input / output terminal 13 External input / output means 15, 16, 17 Address signal output terminal 19, 20, 21 Data signal input terminal 23, 24 switching means

Claims (1)

【特許請求の範囲】 【請求項1】 アドレス信号出力端子とデータ信号入力
端子が対向する面上に構成してある外部入出力手段に装
着可能なICカードにおいて、 両面のそれぞれにICメモリを設け、 一方の面に設けたアドレスまたはデータの第1の入出力
端子と、 他方の面に設けたアドレスまたはデータの第2の入出力
端子と、 上記アドレス信号出力端子と上記第1の入出力端子が接
続し、かつ上記データ信号入力端子と上記第2の入出力
端子が接続する場合と、上記アドレス信号出力端子と上
記第2の入出力端子が接続し、かつ上記データ信号入力
端子と上記第1の入出力端子が接続する場合との違いに
よりいずれか一方の面のICメモリを選択するととも
に、この選択されたICメモリのアドレス入力およびデ
ータ出力を第1および第2の入出力端子のいずれかに選
択的に接続する切換え手段とを具備したICカード。
Claim: What is claimed is: 1. An IC card mountable on an external input / output means, wherein an address signal output terminal and a data signal input terminal are formed on opposite surfaces, and IC memories are provided on both surfaces. An address or data first input / output terminal provided on one surface, an address or data second input / output terminal provided on the other surface, the address signal output terminal, and the first input / output terminal Is connected and the data signal input terminal is connected to the second input / output terminal, and the address signal output terminal is connected to the second input / output terminal, and the data signal input terminal is connected to the second input / output terminal. The IC memory on either side is selected according to the difference from the case where one input / output terminal is connected, and the address input and data output of the selected IC memory are IC card and a switching means for selectively connecting to one of two output terminals.
JP3169773A 1991-07-10 1991-07-10 Ic card Pending JPH0520514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3169773A JPH0520514A (en) 1991-07-10 1991-07-10 Ic card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3169773A JPH0520514A (en) 1991-07-10 1991-07-10 Ic card

Publications (1)

Publication Number Publication Date
JPH0520514A true JPH0520514A (en) 1993-01-29

Family

ID=15892600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3169773A Pending JPH0520514A (en) 1991-07-10 1991-07-10 Ic card

Country Status (1)

Country Link
JP (1) JPH0520514A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0836630A (en) * 1994-07-25 1996-02-06 Sharp Corp Ic card

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0836630A (en) * 1994-07-25 1996-02-06 Sharp Corp Ic card

Similar Documents

Publication Publication Date Title
US5420813A (en) Multiport memory cell circuit having read buffer for reducing read access time
US6459313B1 (en) IO power management: synchronously regulated output skew
US5045714A (en) Multiplexer with improved channel select circuitry
KR950012663A (en) Semiconductor device with boundary scan test circuit
US6272053B1 (en) Semiconductor device with common pin for address and data
JP2747223B2 (en) Semiconductor integrated circuit
JPH0142167B2 (en)
JPH025284A (en) Mode selector for highly integrated memory
JPH0378718B2 (en)
US6737891B2 (en) Tri-directional, high-speed bus switch
US4291247A (en) Multistage logic circuit arrangement
EP0440176B1 (en) Semiconductor memory device
US5982220A (en) High speed multiplexer circuit
US5239214A (en) Output circuit and data transfer device employing the same
US5491431A (en) Logic module core cell for gate arrays
JPH0520514A (en) Ic card
EP0289035B1 (en) MOS Gate array device
US5691653A (en) Product term based programmable logic array devices with reduced control memory requirements
JP2003123475A (en) Device connecting processor to memory element and memory element
JPH06103749A (en) Semiconductor device
JPH05129907A (en) Signal delay device
JPH0514138A (en) Latch circuit with temporary latch function
JPS62192085A (en) Bit processing circuit
JPH04313892A (en) Address control circuit of memory
JPS64723B2 (en)