JPH0360054A - Gate array - Google Patents
Gate arrayInfo
- Publication number
- JPH0360054A JPH0360054A JP1195531A JP19553189A JPH0360054A JP H0360054 A JPH0360054 A JP H0360054A JP 1195531 A JP1195531 A JP 1195531A JP 19553189 A JP19553189 A JP 19553189A JP H0360054 A JPH0360054 A JP H0360054A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- external buffers
- external
- groups
- gate array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000007257 malfunction Effects 0.000 abstract description 4
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
、本発明は、ゲートアレイに関し、特にゲートアレイの
配線構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array, and particularly to a wiring structure of a gate array.
こ従来の技術〕
′＄Ｊ３図は従来のゲートアレイの一例を示す半導体チ
ップの部分平面図である。従来、この種のゲートアレイ
は、同図に示すように、半導体チップの半導体基板１２
の各辺に沿って、中央部に形成された集積回路の駆動用
として外部バッファ２ｄが複数個並べて形成されている
。また、この外部バッファ２ｄの電源として、電源線１
０及び１１が形成されており、各々の外部バッファに供
給部１０ａ及びｌｌａで電源を供給している。さらに、
この半導体チップである半導体基板１２の周囲には、入
出力端子であるポンディングパッド１が多数設けられて
いる。2. Description of the Prior Art FIG. 3 is a partial plan view of a semiconductor chip showing an example of a conventional gate array. Conventionally, this type of gate array has a semiconductor substrate 12 of a semiconductor chip, as shown in the figure.
A plurality of external buffers 2d are formed in parallel along each side for driving the integrated circuit formed in the center. In addition, as a power source for this external buffer 2d, the power line 1
0 and 11 are formed, and power is supplied to each external buffer by supply parts 10a and lla. moreover,
A large number of bonding pads 1, which are input/output terminals, are provided around the semiconductor substrate 12, which is a semiconductor chip.
上述した従来のゲートアレイでは、外部バッファの出力
バッファあるいは出力状態での双方向バッファにおいて
、しばしば、同時動作で電源線に過電流が流れるという
問題がある。このため、電源線の電位が一時的に変動し
、その影響で入力バッファあるいは入力状態での双方向
バッファにノイズが混入したり、正しい電位の入力信号
が供給されなくなり、誤動作につながるという問題があ
る。In the conventional gate array described above, there is often a problem that an overcurrent flows in the power supply line due to simultaneous operation in the output buffer of the external buffer or in the bidirectional buffer in the output state. Therefore, the potential of the power supply line fluctuates temporarily, which may cause noise to enter the input buffer or the bidirectional buffer in the input state, or an input signal with the correct potential may not be supplied, leading to malfunction. be.
本発明の目的は、かかる問題を解消するゲートアレイを
提供することである。It is an object of the present invention to provide a gate array that eliminates such problems.
本発明のゲートアレイは、半導体チップの周辺に沿って
並べて形成された複数の外部バッファとこれら外部バッ
ファを複数のグループに分け、この分けられたグループ
の一つあるいはいくつかのグループにある外部バッファ
を共通に接続するそれぞれの電源線とを有している。The gate array of the present invention includes a plurality of external buffers arranged along the periphery of a semiconductor chip, these external buffers are divided into a plurality of groups, and external buffers in one or several of the divided groups are arranged. and respective power supply lines that are commonly connected to each other.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図及び第２図は本発明のゲートアレイの実施例を示
す半導体チップの部分平面図である。このゲートアレイ
は、まず、第１図に示すように、半導体基板１２に形成
された外部バッファ２及び２ａに供給する電源線を３本
に形成したことである６また、この３本の電源線の内、
電源線３が供給部３ａで電源を供給するのを外部バッフ
ァ２とし、電源線４が供給部４ａで電源を供給するのを
外部バッファ２ａとして、外部バッファを二つのグルー
プに分割したことである。なお、電源線５は、電源線３
と４とは異なる電位を供給するもので、外部バッファ２
及び２ａに共通に供給するものである。1 and 2 are partial plan views of a semiconductor chip showing an embodiment of the gate array of the present invention. As shown in FIG. 1, this gate array is constructed by forming three power supply lines to supply external buffers 2 and 2a formed on a semiconductor substrate 126. Of these,
The external buffers are divided into two groups: the external buffer 2 is the one where the power line 3 supplies power through the supply section 3a, and the external buffer 2a is where the power line 4 supplies power through the supply section 4a. . Note that the power line 5 is the same as the power line 3.
and 4 supply different potentials, and the external buffer 2
and 2a.
一方、別の例として、第２図に示すように、外部バッフ
ァが外部バッファ２ｂと２０との二つのグループに分か
れており、外部バッファ２ｂでは、電源線６及び７によ
り供給部６ａ及び７ａで供給され、外部バッファ２Ｃで
は、電源線８及び９により供給部８ａ及び９ａで供給さ
れている。On the other hand, as another example, as shown in FIG. 2, the external buffer is divided into two groups, external buffers 2b and 20. In the external buffer 2C, the power is supplied to supply sections 8a and 9a by power lines 8 and 9.
このように、本発明のゲートアレイは、外部バッファを
種類毎に分割し、それぞれに適合する電位を供給する電
源線を設けたことである。In this manner, the gate array of the present invention has the external buffer divided into different types and power supply lines for supplying potentials suitable for each type.
以上説明したように本発明は、半導体基板に形成された
外部バッファを複数のグループに分割し、この分割され
たグループの一つあるいはいくつかのグループの外部バ
ッファに供給する電源線を設けることによって、外部バ
ッファの同時動作による他への影響を低減し、誤動作の
ないゲートアレイが得られるという効果がある。As explained above, the present invention divides an external buffer formed on a semiconductor substrate into a plurality of groups, and provides a power supply line to supply the external buffer of one or several of the divided groups. This has the effect of reducing the influence on others due to the simultaneous operation of external buffers, and providing a gate array without malfunctions.
第１図及び第２図は本発明のゲートアレイの実施例を示
す半導体チップの部分平面図、第３図は従来のゲートア
レイの一例を示す半導体チップの部分平面図である。
１・・・ポンディングパッド、２．２ａ、２ｂ、２Ｃ１
２ｄ−・・外部バッファ、３．４．５．６．７．８．９
．１０．１１・・・電源線、３ａ、４ａ、５ａ、６ａ、
７ａ、８ａ、９ａ、１０ａ、ｌｌａ・・・供給部、１２
・・・半導体基板。1 and 2 are partial plan views of a semiconductor chip showing an embodiment of a gate array of the present invention, and FIG. 3 is a partial plan view of a semiconductor chip showing an example of a conventional gate array. 1...ponding pad, 2.2a, 2b, 2C1
2d--external buffer, 3.4.5.6.7.8.9
．． 10.11... Power line, 3a, 4a, 5a, 6a,
7a, 8a, 9a, 10a, lla...supply section, 12
...Semiconductor substrate.
Claims (1)
部バッファと、これら外部バッファを複数のグループに
分け、この分けられたグループの一つあるいはいくつか
のグループにある外部バッファを共通に接続するそれぞ
れの電源線とを有することを特徴とするゲートアレイ。A plurality of external buffers are formed side by side along the periphery of a semiconductor chip, and these external buffers are divided into a plurality of groups, and each of the external buffers in one or several of the divided groups is commonly connected. A gate array characterized in that it has a power supply line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1195531A JPH0360054A (en) | 1989-07-27 | 1989-07-27 | Gate array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1195531A JPH0360054A (en) | 1989-07-27 | 1989-07-27 | Gate array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0360054A true JPH0360054A (en) | 1991-03-15 |
Family
ID=16342640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1195531A Pending JPH0360054A (en) | 1989-07-27 | 1989-07-27 | Gate array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0360054A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5404035A (en) * | 1992-06-11 | 1995-04-04 | Mitsubishi Denki Kabushiki Kaisha | Multi-voltage-level master-slice integrated circuit |
| US5434436A (en) * | 1992-10-28 | 1995-07-18 | Mitsubishi Denki Kabushiki Kaisha | Master-slice type semiconductor integrated circuit device having multi-power supply voltage |
-
1989
- 1989-07-27 JP JP1195531A patent/JPH0360054A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5404035A (en) * | 1992-06-11 | 1995-04-04 | Mitsubishi Denki Kabushiki Kaisha | Multi-voltage-level master-slice integrated circuit |
| US5552618A (en) * | 1992-06-11 | 1996-09-03 | Mitsubishi Denki Kabushiki Kaisha | Multi-voltage-lever master-slice integrated circuit |
| US5434436A (en) * | 1992-10-28 | 1995-07-18 | Mitsubishi Denki Kabushiki Kaisha | Master-slice type semiconductor integrated circuit device having multi-power supply voltage |
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