JPH0322460A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable selection of an arbitrary potential without narrowing the width of a power wire for each side by providing a power line independent for each side and a plurality of power lines laid around the outer peripheral part of a semiconductor chip and by disposing input-output interface blocks in the outer peripheral part of the chip. CONSTITUTION:A bus line of a power source and ground wires is constructed of a third power wire 8, a first power wire 9 formed around the third power wire 8, a second power wire 10 surrounding the first power wire 9 and an internal ground wire 11 and an external ground wire 12 formed on the innermost and outermost sides of a semiconductor chip 1. Input-output interface blocks take a power supply from the first power wire 9 or the second power wire 10 and simultaneously supplies a potential to the third power wire 8. By a mesh structure of a power source constructed of the third power wire 8 and each input-output interface block, it is possible to change the potential in such a manner that the potential of 5 volts is inputted to a power bus line of one side while the one of 1 volt is inputted to the power bus line of the other.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the layout of semiconductor integrated circuits, and particularly to the layout of power supply bus lines.

[Conventional technology]

FIG. 3 is a plan view of a semiconductor chip showing an example of the layout of a conventional semiconductor integrated circuit. Conventionally, the layout of power supply bus lines in this type of semiconductor integrated circuit has been
As shown in the figure, all the power lines and ground lines (Garland lines 2, 7, first and second power lines 2, 3, 5, 6) are arranged around one principal surface of the semiconductor chip 1. Is there a power supply line with a semi-fixed potential for each side, regardless of the input/output interface blocks arranged on this semiconductor chip 1? It was formed by either.

[Problem to be solved by the invention]

In the above-mentioned conventional power bus line layout, in CMOS integrated circuits where the layout must be done with particular consideration to latch-up resistance, when different potentials are required on each side of the power bus line, the entire periphery of the chip is A system in which the power supply line goes around once has the drawback that a sufficient power supply line width cannot be secured, which is disadvantageous to electromigration. Further, since the power supply impedance appears high, there is a disadvantage that it is disadvantageous for simultaneous operation. Furthermore, in the power line system where the potential is fixed for each side, the potential is fixed for each side, which has the disadvantage of limiting the number of power supply pins and input/output interface blocks that can be placed. An object of the invention is to provide a semiconductor integrated circuit having a power bus line layout that solves this problem.

[Means to solve the problem]

A semiconductor integrated circuit of the present invention includes a logic gate element group formed in the center and first and second power supply lines extending around the logic gate element group. a third power line extending parallel to each side of the first and second power lines and having at least one side; and a third power line and the first and second power lines. and a connecting means for connecting.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a semiconductor chip showing an embodiment of the layout of a semiconductor integrated circuit according to the present invention.

The layout of this semiconductor integrated circuit, in this case the bus line of the power supply and ground line, does not have a particular potential,
This is a power supply line whose potential is determined by the input/output interface block placed there. Specifically, as shown in the figure, a third power line 8, a first power line 9 surrounding the third power line 8, and a third power line 9 are connected to each other. A second power supply line 10 surrounds the semiconductor chip 1, and an internal ground line 11 and an external ground line 12 formed on the innermost and outermost sides of the semiconductor chip 1.

In addition, the input/output interface block receives power from the first power line 9 or the second power line 10, and at the same time,
A potential is supplied to the third power supply line 8. As a result, even if multiple buffers operate simultaneously on one side of the first and second power supply lines 9 and 10, the mesh structure of the power supply is occluded by the third power supply line 8 and each input/output interface block. This makes it possible to reduce noise on the power supply. Furthermore, in the conventional technology, this third power line 8
are connected at each corner, or the potential is determined by a block dedicated to supplying potential to the third power supply line 8. Figures 2 (a), (b), and (C) show the underlying surface of the semiconductor chip, the first aluminum wiring surface above the underlying surface, and the second aluminum wiring surface above the underlying surface of the semiconductor chip, showing the respective layer surfaces of section A in FIG. 1. FIG. 3 is a plan view of an aluminum wiring surface. The underlying surface of this semiconductor integrated circuit is, for example, the underlying surface of section A in FIG.
), the N-channel transistor region 18,
A substrate contact 16 and an N-well contact 17 are formed between the p-channel transistor region 15 and the p-channel prebuffer 14, respectively, to prevent latch-up. Further, an N-channel pre-buffer 13 is formed adjacent to the p-channel pre-buffer 14. On the other hand, on the first aluminum wiring surface on this base surface, as shown in FIG. 2(b), a first aluminum wiring area 19 and a substrate contact 16 are formed.
Also, a first aluminum contact 20 and a second aluminum contact 21 connected to the N-well contact 17 are shown.

Furthermore, on the second aluminum wiring surface formed on the first aluminum wiring surface, as shown in FIG. From the side, the internal ground line 12, the buffer wiring area 22, the third power line 8, the fourth power line 23 connected to the first aluminum contact 20, the first power line 9, and the second power line 10. , a fourth power supply line, a fifth connection line 24 connected to the second aluminum contact 21, and an external ground line, respectively. Here, the second
By utilizing the first aluminum wiring area 19 shown in FIG. 3(b), wiring is performed in accordance with the function of each manual output buffer. That is, for example, the potential of the third power supply line 8 is
If you want to have the same potential as the power supply line 9 of
The third power supply line 8 and the first power supply line 9 are short-circuited by through-hole contact through regions B and C of the aluminum wiring region 19. Furthermore, if it is desired that the third power line 8 and the second -5 6- power line 10 be at the same potential, they may be short-circuited via the D region and the C region using a through-hole contact.

In this way, there is an advantage that the power supply potential input to the integrated circuit can be arbitrarily changed by providing the third power supply line. For example, the potential input to the power bus line on one side can be changed to 5 volts, and the potential input to the power bus line on the other side can be changed to 1 volt.

〔Effect of the invention〕

As explained above, the present invention provides an independent power supply line for each side and a plurality of power supply lines that go around the outer periphery of the chip. This has the effect of providing a semiconductor integrated circuit in which a potential can be arbitrarily selected for each side without narrowing the width of the power supply line by applying a potential to an independent power supply line for each side.

[Brief explanation of drawings]

FIG. 1 shows a layout (a) of a semiconductor integrated circuit according to the present invention;
(b) and (c) are plan views of a base surface of a semiconductor chip showing each layer surface of part A in FIG. 1, a first aluminum wiring surface on the base surface, and a second aluminum wiring surface above it; FIG. 3 is a plan view of a semiconductor chip showing an example of the layout of a conventional semiconductor integrated circuit. 1... Semiconductor chip, 2... Ground line, 3.9.
...First power line, 4.10...Second power line, 5.
... lth power supply line for external drive buffer, 6 ... second power supply line for external drive buffer, 7 ... ground line for external drive buffer, 8 ... third power supply line, 11. ...External ground line, 12...Internal ground line, 13...
N channel prebuffer, 14...P channel prebuffer, 15...P channel transistor region, 16...substrate contact, 17...N
Well contact, 18...N-channel transistor region, l9...l-th aluminum wiring region, 20...
First aluminum contact, 21... Second aluminum contact, 22... Bribuffer wiring area, 23...
Fourth power line, 24...Fifth power line. 9

Claims (1)

[Claims] In a semiconductor integrated circuit having a logic gate element group formed in the center and first and second power supply lines formed around the logic gate element group, the first and second power supply lines It is characterized by having a third power line formed parallel to each side and having at least one side or more, and a connecting means for connecting the third power line to the first and second power lines. Semiconductor integrated circuit.