JP2508205B2 - Master-slice type semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice semiconductor device, and more particularly to a master slice semiconductor device having a plurality of different types of power supply bus lines.

[Conventional technology]

A master slice type semiconductor device, especially a gate array, has elements such as transistors and resistors necessary for circuit configuration embedded in an array on a semiconductor substrate, and a metallization pattern and power supply bus for each product type to form a desired circuit therein. This is a method of combining common patterns between product types such as lines. By this method, a semiconductor device can be designed and manufactured with a small number of steps. In recent years, however, different types of circuits have been mounted on the same chip to provide higher flexibility in terms of use conditions and functions.
For example, even in a CMOS gate array, higher functions and versatility have been pursued by mixing digital circuits and analog circuits or combining low voltage operation circuits and high voltage interface circuits.

[Problems to be Solved by the Invention]

When different types of circuits are mounted on the same chip in the above-mentioned conventional gate array, a plurality of power supply bus lines are required to prevent the difference in power supply potential between circuits and the sneak of power supply noise. . Considering the point that it is possible to arrange a desired circuit in any place in the chip from the degree of freedom of product design as a gate array,
These plurality of bus lines must be arranged equally in the chip. However, since the ratio of each type of circuit to the entire chip varies depending on the type of product, the power supply capacity of each bus line must have a margin assuming that the corresponding circuit is used in the entire chip. The area occupied by the chip itself is also considerably large. Further, since the connection points between the plurality of bus lines and the circuit block differ depending on the circuit type, the wiring of the power supply wiring in the circuit becomes complicated, which is an obstacle to the design of the gate array.

[Means for solving the problem]

The master slice type semiconductor device of the present invention uses a transistor array and a power supply bus line having a common pattern shape among a plurality of types, and a metallized pattern of an individual shape for each type according to a desired circuit function in the transistor array. In the master slice type semiconductor device having different types of circuit blocks configured as described above, the power bus lines having the common pattern shape are different from the power bus lines of different types formed in the same wiring layer and the different types. Variable power supply bus line that becomes a power supply bus line of a unique type for each product type by connecting to any of the different power supply bus lines. Connected by a connection pattern formed on a wiring layer different from the bus line, Circuit block is intended to be supplied through the through hole of the power corresponding to the kind of the variable power supply bus line.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of the first embodiment of the present invention. The gate array chip 10 is roughly divided into an internal cell array region 11 and an interface cell array region 12, and two different potential V _DD bus lines are arranged on the interface cell array. Between these high V _DD bus line 131 and low V _DD bus line 132, a power supply bus line (hereinafter referred to as variable V _DD bus line) 133 that can be connected to either 131 or 132 is arranged.
In this embodiment, the variable V _DD bus line is divided into four on one chip, and the V _DD potential can be selected for each side on the chip, but further subdivision is possible if necessary. is there.

FIG. 2 shows a case where the circuit block 121 is arranged in the interface cell array portion (part) of the chip of FIG. 1 and a low V _DD power supply is supplied. Low V _DD bus line 131 and variable V _DD
The bus line 133 is connected to the connection pattern 14 and a through hole (not shown) at the end of the cell array.

The variable V _DD bus line 133 and the circuit block 121 are connected by the through hole 15. Since the power supply to the circuit blocks is carried out only through the variable V _DD bus line 133 even high V _DD even low V _DD, thereby the through hole at the time of the circuit block design consideration for installation on the variable V _DD bus line 133 It is only necessary, and the design man-hours can be greatly reduced. Furthermore, if this variable V _DD bus line is not adopted, the wiring width required for all V _DD bus lines is (high V _DD bus line width + variable V _DD bus line width
_DD bus line width) + (low V _DD bus line width + variable V _DD bus line width), the present invention reduces the occupied area of all V _DD bus lines by (variable V _DD bus line width). You can

In this embodiment, any of the bus lines 131 to 133 and the connection pattern 14 may serve as the lower wiring layer.

FIG. 3 shows a part of the chip interface section of the second embodiment of the present invention. High V _DD interface circuit 220 and low V _DD interface circuit 221 are adjacent to each other
_{The DD} bus lines are placed separately. Each interface circuit is divided into an output circuit section 222 and an input circuit section 223. The connection between each input circuit section and the power supply bus line is made by through holes 151 and 152, and each output circuit section and the power supply bus line are through hole. Connected at 153,154. One of the two variable V _DD bus lines 233 has a connection pattern
141 and through holes (not shown) are connected to the high V _DD bus line 231, and the other of the variable V _DD bus lines 233 is connected to the low V _DD bus line 232 by a connection pattern 142 and through holes (not shown). . If the variable V _DD bus line is connected in this way, the input circuit section will be at the same potential as the output section if V _{DD is} supplied only from the variable bus line 233, and the input circuit with low V _DD and high V _DD The metallization pattern shape of can be unified, and the design man-hour can be reduced.

Also in this embodiment, any of the bus lines 231 to 233 and the connection patterns 141 and 142 can be used as the lower layer wiring.

〔The invention's effect〕

As described above, according to the present invention, in a master slice type semiconductor device having different types of power supply bus lines, a specific power supply bus line can be formed by connecting to one of the power supply bus lines according to the type of chip. By providing the variable power supply bus line that can be provided, the following effects can be achieved.

(1) Since redundant bus lines can be eliminated, the area occupied by the power supply bus lines in the chip can be reduced.

(2) For circuit blocks that are connected to different power supply bus lines depending on the type of chip, only the connection with the variable power supply bus line needs to be considered when connecting the circuit blocks to the bus lines during design. It is possible to reduce the complexity of turning around and reduce the number of designing steps.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are plan views of a first embodiment of the present invention, and FIG. 3 is a plan view of a second embodiment of the present invention. 10 …… Gate array chip, 11 …… Internal cell array area, 12 …… Interface cell array area, 131 ……
High V _DD bus line, 132 …… Low V _DD bus line, 133 …… Variable V _DD bus line, 14,141,142 …… Connection pattern, 15,15
1 to 154 …… Through hole, 121,220,221 …… Interface circuit block.

Claims (1)

(57) [Claims] 1. A type in which a transistor array and a power supply bus line having a common pattern shape among a plurality of types and a metalized pattern of an individual shape for each type according to a desired circuit function are used in the transistor array. In the master slice type semiconductor device having different circuit blocks, the power supply bus line having the common pattern shape is one of a plurality of different kinds of power supply bus lines and the different kind of bus lines formed in the same wiring layer. And a variable power source bus line which is a power source bus line of a unique type for each product type, and the variable power source bus line is different from any of the different types of power source bus lines. The circuit blocks are connected according to the connection pattern formed on the wiring layer, Master slice type semiconductor device for a power supply that from the variable power supply bus lines, characterized in that it is supplied through the through hole.