JPH03108760A - Cmos gate array - Google Patents

Abstract

PURPOSE:To supply a power supply line and a ground line to a part of a traisistor line used as a wiring area and thereby to make it possible to use it as a transistor area by a method wherein a power supply and a ground potential supplied to a different transistor line are supplied to the part of the transistor line used as the wiring area. CONSTITUTION:In a totally-spread-over type CMOS gate array which has a plurality of transistor lines 5, and a first power source and ground zones 3 and 4 prepared beforehand irrespective of the presence or absence of transistors 1 and 2 disposed to construct a logic circuit 7 on the transistor lines 5, and at a right angle to the transistor lines 5, wirings 8 and 9 for supplying a power supply and a ground potential to a transistor line 10 located under a wiring area 6 not connected directly to the first power source and the ground zones 3 and 5 from the transistor lines 5 having a second power source 11 and a ground line 12 connected directly to the first power source and the ground zones 3 and 4 prepared beforehand, are provided. Since transistors in the wiring area 6 are made usable, according to this constitution, the degree of integration can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS gate array, and more particularly to a wiring structure for increasing the degree of integration in a full-coverage CMOS gate array.

[Conventional technology]

An example of the structure of a conventional all-over CMOS gate array will be described with reference to FIG. As the planar structure of this gate array is shown in FIG.
Channel transistors 1 and N-channel transistors 2 are lined up, and a potential is supplied from the second power supply line 11 to the P-channel transistor 1 via a prepared "first power supply line 3", and the first ground band 4 is connected to the second power supply line 11. from the second ground line 12 through the N-channel transistor 2
The transistor array 5 becomes usable by supplying a potential to the top, and the second power supply line 11 connects the P-channel transistor 1 to the second ground line 12 to the N-channel transistor 2. A wiring region 6 is formed above the transistor.

A logic circuit 7 having the same logic is constructed by combining a pair of P-channel transistors 1 and N-channel transistors 2, and this logic (1) (2) circuit T is connected to the first layer wiring 8. By connecting it to the second layer wiring 9, etc., one functional circuit is constructed.

Here, the wiring such as the first layer wiring 8 that connects the logic circuits T is formed on the wiring area 6, and the width of the wiring area 6 is equal to the width of the transistor array 5 on which the second power supply line 11 and the ground line 12 are arranged. This is a region surrounded by other transistor rows 5. In addition, if wiring cannot be done only in this area, the width of the wiring area is increased by setting the wiring area 6 above the transistor array 10 without arranging the second power supply line 11 or the ground line 12 on the transistor array. Therefore, the width of the wiring region is the same as that of P channel transistor 1. Alternatively, it expands by the transistor width of N-channel transistor 2.

[Problem to be solved by the invention]

Since the conventional all-over CMOS gate array is configured as described above, the wiring area 6 is expanded by the width of the transistor, and even though it is a wiring area, the part not used for wiring is also 6D, and the transistor in this area is Further, there were problems such as the fact that a part of the transistor array under the wiring area 6 could not be used in advance.

The present invention has been made to solve the above problems, and provides a CMOS gate array that can be used as a transistor region by supplying a power supply line and a ground line to a part of the transistor row used as a wiring region. The purpose is to

[Means to solve the problem]

The CMOS gate array according to the present invention is an all-over type CMOS gate array in which power supply and ground potential supplied to different transistor rows are supplied to a part of the transistor row used as a wiring area to form transistors. It is.

[Effect]

In the CMOS gate array according to the present invention, the transistors under the wiring area can be used by applying a potential to the transistors that are not used in the wiring area from the power supply line and the ground line of other transistor areas through wiring.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing the structure of a CMOS gate array according to an embodiment of the present invention. In this embodiment, as shown in FIG. 1, transistor arrays 5 are spread over the entire surface of the internal chip, and P-channel transistors 1. A first power supply band 3. is connected to each N-channel transistor 2. A conventional gate in which a part of the ground band 4 to which a potential is supplied forms a usable transistor array 5, and a part of the first power supply band 3 and the ground band 4 to which a potential is not supplied forms a wiring region 6. The first layer wiring 8. The first power supply band 3 is supplied to different transistor arrays 5 depending on the wiring such as the second layer wiring 9.
．． By supplying the potential of the ground band 4, a usable transistor array is formed in the lower wiring area 6 where no wiring is provided, thereby configuring the logic circuit 7. In addition, the first layer wiring 8 is placed on a part of the transistor row 10 under the wiring area 6 in advance.
The first power supply band 3. is supplied to different transistor arrays 5 depending on the wiring such as the second layer wiring 9. By supplying the potential of the ground band 4, a partially usable transistor array is formed, and then the logic circuits T are interconnected.

As described above, according to the configuration of the above embodiment, the first power supply band 3. The transistor row 5 having the second power supply line 11 and the ground line 12 directly connected to the ground band 4 is connected to the transistor row under the wiring area 6 which is not directly connected to the first power supply band 3 and the ground band 4. By supplying power and ground potential to the layer wiring 8 and the second layer wiring 9, etc., transistors not used in the wiring area 6 can be used. Thereby, the degree of integration can be improved.

〔Effect of the invention〕

As described above, according to the present invention, the power supply and ground potential are supplied to the wiring from other transistor rows to the transistor row under the wiring area, which could not be used conventionally, so that the CMOS with high integration This has the effect of providing a gate array.

[Brief explanation of drawings]

(5) (6) FIG. 1 is a plan view showing a CMOS gate array according to an embodiment of the present invention, and FIG. tJ2 is a plan view showing a conventional CMOS gate array. 1-...-p channel transistor 211+111・
N-channel transistor, 3, first power supply band, 4
...First ground band, 5...Transistor row having a power supply and ground line, 6...Wiring area,
T...Logic circuit, 8...First layer wiring, 9...
・Second layer wiring, 10th row...Transistor row under wiring area, 11...Second power supply line, 12...φ2nd
Grand line.

Claims (1)

[Claims] A first power supply and a ground band prepared in advance are connected to a plurality of transistor rows and at right angles to the transistor rows, regardless of the presence or absence of transistors arranged on the transistor rows to form a logic circuit. In the fully-covered CMOS gate array, the first power source prepared in advance, a second power source directly connected to the ground band, and a ground line connected from the transistor array to the first power source and the ground band. Power supply to transistor columns under wiring areas that are not directly connected,
A CMOS gate array characterized by having wiring for supplying a ground potential.