JPH0382140A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the size of a semiconductor chip by a method wherein a logical gate is made to build in a feeder cell. CONSTITUTION:In a feeder cell 10 with a dummy gate, a feeder cell for adding a desired potential to a well and a substrate is formed of a well feeder contact 9 and a substrate feeder contact 10, while 4 MOS transistors Tr1 to Tr4 are formed of first to third Al wirings 1 to 3, first to third polycrystalline silicon gates 4 to 6, a P-type diffused layer 7 and an N-type diffused layer 8. These four transistors constitute jointly a logical cell (a 2-input NAND circuit) and the logical gate acts as a logical gate for backup use at the time of abnormality of other logical gate. That is, by using the logical gate built in the feeder cell as a dummy gate for logical backup use, for example, part or the whole of a region which is used for merely the feeder cell can be used commonly as the region of the logical gate and the dead space of a semiconductor chip can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device equipped with a logic gate and a power supply cell, and particularly relates to a semiconductor integrated circuit device having a logic gate and a power supply cell. The present invention relates to a semiconductor integrated circuit device.

[Prior Art] Usually, in a semiconductor integrated circuit device in which a large number of transistors are arranged, power supply cells are arranged for supplying a predetermined potential to a plurality of locations on a semiconductor body, and a power supply cell is arranged in a semiconductor substrate and a power supply cell formed in the substrate. It is electrically isolated from the well, thereby stabilizing the function of the transistor formed in the well.

On the other hand, in semiconductor integrated circuit devices equipped with logic gates, in case a defect occurs in the logic gate during the manufacturing process, so-called logic debugging dummy gates (dummy logic gate)
are arranged at a predetermined ratio to the number of regular logic gates, making it easy to correct logic when a defect occurs in a logic gate, and increasing the yield of semiconductor integrated circuit devices.

Here, FIG. 5 shows an example of a conventional layout of a power supply cell and a dummy gate for logic debugging in a semiconductor integrated circuit device. For example, 1 as shown in the figure.
In a semiconductor integrated circuit device with 1000 logic gates arranged on an m square chip, 10 stages of cell rows are provided.
Ten power supply cells 20 are arranged per cell column at intervals of 100 μm. In a semiconductor integrated circuit device of this scale, dummy gates 30 for logic debugging are arranged at a ratio of about 30 for every 1000 logic gates to prevent defects in logic gates that may occur during the manufacturing process. I try to make sufficient logical corrections.

[Problem to be solved by the invention] In recent years, in the field of manufacturing semiconductor devices, there has been a demand for higher integration to improve the functionality of logic integrated circuits, and this has led to reductions in semiconductor chip size5 and further reductions in chip size. Therefore, it is desired to reduce the cost of semiconductor integrated circuit devices. However, in a semiconductor integrated circuit device as shown in FIG. 5, which has not only a power supply cell but also a dummy gate for logic debugging in case of an abnormality in the logic gate, the power supply cell and the dummy gate are separated from each other. Since the semiconductor chip was formed in the region of 1, the dead space of the chip inevitably increased, and the above-mentioned demand for higher integration could not be met.

The present invention has been made in view of the above circumstances, and provides a highly integrated semiconductor integrated circuit device that is capable of sufficiently correcting the logic even if a defect occurs in a logic gate, and is compact and highly integrated while maintaining these functions. The main purpose of the present invention is to provide a semiconductor integrated circuit device that enables the size of semiconductor chips to be reduced by reducing the size of semiconductor chips.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In the semiconductor integrated circuit device of the present invention, which includes a logic gate and a power supply cell, the logic gate is built into the power supply cell.

[Function] In a semiconductor integrated circuit device equipped with a power supply cell having a built-in logic gate, the logic gate built in the power supply cell can be used, for example, as a dummy gate for logic debugging, so that it can be used only in the power supply cell in the past. A part or all of the area that was not used can be shared as a logic gate area, and the dead space of the semiconductor chip can be reduced.

[Embodiments] Hereinafter, embodiments of the semiconductor integrated circuit device of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing the configuration of a power supply cell (hereinafter simply referred to as "power supply cell with dummy gate") incorporating a dummy gate for logic debugging according to the present invention.

This power supply cell 100 with a dummy gate includes a first aluminum wiring 1, a second aluminum wiring 2, and a third aluminum wiring 11A3.
, first polysilicon gate 4, second polysilicon gate 5, third polysilicon gate 6, P diffusion layer 7, N
Diffusion layer 8. The main components are a well power supply contact 9 and a substrate power supply contact 10.

That is, this power supply cell 100 with a dummy gate forms a power supply cell that applies a desired potential to the well and the substrate by the well power supply contact 9 and the substrate power supply contact 10, while the first to third aluminum wirings 1 to 3 , 1st to 3rd
Four MOS transistors (Tr units) are formed by the polysilicon gates 4 to 6, the P diffusion layer 7, and the N diffusion layer 8. These four transistors work together to configure a logic gate (2-input NAND circuit), and other logic gates (
It acts as a backup logic gate in the event of an abnormality (not shown).

Specifically, in FIG. 1, a first P-channel transistor Tr1 is formed in region I, and a second P-channel transistor Tr is formed in region (2). On the other hand, first and second N-channel transistors Tr, Tr4 are formed in regions (1) and (2), respectively, and the four transistors Tr--. By this combination, one two-input NAND circuit is configured within the power supply cell 100 with a dummy gate. Here, a''h in the figure indicates a contact hole.

Figure 2 shows the circuit configuration of the power supply cell with dummy gate shown in Figure 1, especially the NA as a dummy gate for logical depacking.
This is an equivalent circuit showing the configuration of the ND circuit portion. A and B in the diagram
indicates a dummy gate input terminal, and C indicates a dummy gate output terminal.

The power supply cell with a dummy gate having the above configuration has a configuration in which the power supply cell is substantially arranged within the dead space of the dummy gate for logic debugging, so that high integration and further miniaturization of the chip size can be achieved.

For example, as shown in FIG. 4(a), the area (1+2/3 gate area) required when one power supply cell and one dummy gate for logic debugging are provided separately is reduced in this embodiment. By applying a power supply cell with a dummy gate, only one gate area becomes sufficient.

Incidentally, in the power supply cell with a dummy gate shown in FIG.
The middle part of the aluminum wiring 1 that performs this can be brought into contact with the well to supply power, while the middle part of the aluminum wiring 3 that performs voltage application (for example, OV) to the diffusion N8 of the N-channel transistors Tr, Tr4. Since power can be supplied by contacting the well power supply contact 9 to the substrate, a well power supply contact 9 is placed under the aluminum wirings 1 and 3 (dead space) that are electrically connected to the respective diffusion layers 7 and 8.
, substrate power supply contact 1o can be formed respectively.

Here, the effect when the power supply cell with a dummy gate according to the present invention is actually applied to an integrated circuit device having a size of 1++a square and 1000 gates will be specifically explained.

Suppose now that the area S2 required for arranging conventional power supply cells and the area S1 required for arranging one dummy gate for logic debugging are
Let's consider a case where the ratio of S1:82 is approximately 2:3 (the area S required for arranging the power supply cell with a dummy gate of the present invention is equal to the area s1 required for a conventional dummy gate for logic debugging). ).

In a 1000 gate scale integrated circuit device of 1 + w + angle,
The power feeding cells are usually arranged at intervals of 100 μm in the vertical and horizontal directions, and approximately 100 cells in total are required. On the other hand, when an integrated circuit device of this scale is used as a logic integrated circuit, the number of logic debugging dummy gates required for logic modification is about 30, as described above.

Therefore, in the conventional system shown in FIG. 5, when considering the size S of the dummy gate for logic debugging as a reference (one gate area), the area required for the conventional power supply cell arrangement is: 100XS, = 100X-81 ...approximately 67 gate area 0 The area required for arranging the dummy gate for logic debugging is:
...Approximately 30 gate areas Therefore, in order to provide one semiconductor chip with the functions of a power supply cell and a dummy gate for logic debugging.

A total of about 97 gate areas are required.

On the other hand, when the power supply cell with dummy gates according to the present invention is applied to the 1000-gate integrated circuit device, about 30 out of about 100 power supply cells are used as the logic debugging dummy gates.

The remaining approximately 70 cells may be used as conventional power feeding cells. Therefore.

0 The area required for the conventional power supply cell arrangement is 70 x S
3 = 70 X-81...approximately 47 gate area 0 The area required for arranging the dummy gate for logic debugging is:
... Approximately 30 gate areas Therefore, in order to provide a single semiconductor chip with the functions of a power supply cell and a dummy gate for logic debugging, a total area of approximately 77 gates is required.

As can be seen from the above, when the power supply cell with dummy gates according to the present invention is applied to an integrated circuit device with approximately 1000 gates, the area is approximately 20 gates, that is, the area in which 20 power supply cells with dummy gates can be arranged. This makes it possible to reduce

Note that the chip area reduced by applying the power supply cell with a dummy gate according to the present invention increases in proportion to the scale (number of gates) of the integrated circuit device.

The more highly integrated the circuit device becomes, the greater the effect becomes.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, according to the semiconductor integrated circuit device of the present invention.

For example, when providing a logic gate and a power supply cell, since the logic gate is built into the power supply cell, the dead space of the power supply cell can be effectively used, and the chip size can be reduced due to high integration. , a reduction in the cost of semiconductor integrated circuit devices is achieved.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the configuration of a power supply cell incorporating a logic debugging dummy gate according to the present invention. FIG. 2 is a circuit diagram showing the circuit configuration of a dummy gate built into the power supply cell of FIG. 1. FIG. 3 is an explanatory diagram illustrating the size relationship between a power supply cell incorporating a semiconductor integrated circuit bag to which the present invention is applied, a conventional power supply cell and a conventional dummy gate, and FIG. 5 shows a power supply cell and a dummy gate. FIG. 2 is a layout block diagram of a conventional semiconductor integrated circuit device separately provided with a gate. 9...well power supply contact, 10...substrate power supply contact, 20...power supply cell, 30...dummy gate for logic debugging, 100...power supply cell with dummy gate, A, B...Dummy gate input terminal, C...Dummy gate output terminal, Trl, Tr2.
...P-channel transistor, Tr, Tr4...
...N-channel transistor. (a) Figure 3 Figure (b) Figure

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device comprising a logic gate and a power supply cell, characterized in that the power supply cell has a built-in logic gate. 2. The semiconductor integrated circuit device according to claim 1, wherein the logic gate built into the power supply cell is a dummy logic gate used only when another logic gate is abnormal. 3. The logic gate built into the above power supply cell has 2 input NA
3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is an N circuit.