JPS6226853A - Complementary mos semiconductor integrated circuit device - Google Patents
Complementary mos semiconductor integrated circuit deviceInfo
- Publication number
- JPS6226853A JPS6226853A JP60166482A JP16648285A JPS6226853A JP S6226853 A JPS6226853 A JP S6226853A JP 60166482 A JP60166482 A JP 60166482A JP 16648285 A JP16648285 A JP 16648285A JP S6226853 A JPS6226853 A JP S6226853A
- Authority
- JP
- Japan
- Prior art keywords
- contact
- source
- circuit block
- logic circuit
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000000295 complement effect Effects 0.000 title claims description 7
- 239000002184 metal Substances 0.000 abstract description 17
- 229910052751 metal Inorganic materials 0.000 abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、相補ＭＯＳ形半導体集積回路装置のパターン
レイアウトに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern layout of a complementary MOS type semiconductor integrated circuit device.
第２図のパターンレイアウトは、従来の一般的ら配置法
で設計した２人力ＮＡＮＤのパターンレイアウトであり
、シリコン基板をＮ型とすｎば、１６はＰウェル領域と
Ｎ型基板の境界を表わし、図中の原点（０，０）から１
６の境界線上までがＮチャンネル側で境界線１６より遠
い方がＰチャンネル側である。Ｎチャンネル側について
見ると、電源供給の金属配線２からソース領域１３へ、
コンタクト６を介して、電位を供給し、多結晶性シリコ
ン８，９がゲート電極となってチャンネルが構成さｎる
１８，１９は、ソース領域１３に対して直列に配置さｎ
ｌ ドレイン領域１４からコンタクト７を介して金属配
線１５に接続さｎる。The pattern layout in Figure 2 is a two-man NAND pattern layout designed using the conventional general layout method, where the silicon substrate is N-type and 16 represents the boundary between the P-well region and the N-type substrate. , 1 from the origin (0,0) in the figure
The area up to the boundary line 16 is the N channel side, and the area further from the boundary line 16 is the P channel side. Looking at the N-channel side, from the power supply metal wiring 2 to the source region 13,
A potential is supplied through the contact 6, and the polycrystalline silicon 8 and 9 serve as gate electrodes to form a channel.N 18 and 19 are arranged in series with the source region 13.
l Connected from the drain region 14 to the metal wiring 15 via the contact 7.
次にＰチャンネル側において、電源供給の金属配線１か
らコンタクト３を介してソース領域１０に電位を供給し
、多結晶シリコン８がゲート電極となってチャンネル２
０が構成さｎｌ ドレイン領域１１からコンタクト４を
介して金属配線１５に接続さｆＬる。また電源供給の金
属配線１は、コンタクト５を介して、ソース領域１２に
電位を供給し、多結晶シリコン９が、ゲート電極となっ
てチャンネル２１が構成さｎドレイン領域１１からコン
タクト４を介して金属配線１５に接続さｎる。Next, on the P channel side, a potential is supplied from the metal wiring 1 for power supply to the source region 10 via the contact 3, and the polycrystalline silicon 8 becomes the gate electrode, and the channel 2
0 is configured nl and is connected from the drain region 11 to the metal wiring 15 via the contact 4 fL. Further, the power supply metal wiring 1 supplies a potential to the source region 12 via the contact 5, and the polycrystalline silicon 9 serves as a gate electrode to form a channel 21. Connected to metal wiring 15.
このようにＮチャンネル側は、ソースに対して、チャン
ネル領域１８．１９が、直列に配置さｎドレインへ、Ｐ
チャンネル側は、ソースに対してチャンネル領域２０．
２１が並列に配置さｎドレインへそしてドレイン同志を
金属で接続し２人力ＮＡＮＤが構成さｎる。In this way, on the N-channel side, the channel regions 18 and 19 are arranged in series with the source, and the P
On the channel side, the channel region 20.
21 are arranged in parallel to n drains, and the drains are connected with metal to form a two-man power NAND.
以後の説明を簡単にするために、パターンレイアクトさ
れた相補ＭＯＳ形半導体集積回路装置を、論理回路ブロ
ックと称す。To simplify the following explanation, the complementary MOS type semiconductor integrated circuit device subjected to pattern layout will be referred to as a logic circuit block.
上述した従来のパターンレイアウトは、ブロックの高さ
を一定にし、その範囲内に配置、配線する。そしてレイ
アウト上で、論理回路ブロック内の各工程と設計ルール
を満足するように、論理回路ブロックの外枠１７（第２
図）を決める。レイアウトでは、論理回路ブロックを外
枠１７のみで表現して配置、配線する。In the conventional pattern layout described above, the height of the blocks is kept constant, and the blocks are arranged and wired within that range. Then, on the layout, the outer frame 17 (second
Figure). In the layout, the logic circuit blocks are expressed only by the outer frame 17 and arranged and wired.
このように論理回路ブロックを設計し、配置を行うため
論理回路ブロックの配置終了後も、１つ１つが′Ｉ！源
供給源をもっている。そのため、電源供給領域の面積が
大きくなり、半導体集積回路装置の高密度設計を妨げる
パターンレイアウトである。Because the logic circuit blocks are designed and placed in this way, even after the logic circuit blocks are placed, each one is 'I! have a source of supply. Therefore, the area of the power supply region becomes large, resulting in a pattern layout that impedes high-density design of semiconductor integrated circuit devices.
本発明は、論理回路ブロックを配置した時に１つの論理
回路ブロックに１対の電源供給源を有するという問題点
を解決するパターンレイアウトを提供するものである。The present invention provides a pattern layout that solves the problem of having one pair of power supply sources in one logic circuit block when logic circuit blocks are arranged.
つまり、１つの論理回路ブロックと１つの論理回路ブロ
ックをミラー状態で重ね合わせて、配置した時にお互い
のＮチャンネル側の１つのソース供給源と、Ｐチャンネ
ル側の１つのソース供給源が、同電位同志で重なゆ合う
ように、ソース供給位置を考慮してパターンレイアウト
した論理回路ブロックである。In other words, when one logic circuit block and one logic circuit block are placed one on top of the other in a mirror state, one source supply source on the N-channel side and one source supply source on the P-channel side are at the same potential. This is a logic circuit block whose pattern is laid out in consideration of the source supply position so that they overlap each other.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例のパターンレイアウト図で
あり、２人力ＮＡＮＤを表わしている。ここでは、Ｎ型
基板使用と限定し説明を行う。FIG. 1 is a pattern layout diagram of an embodiment of the present invention, and represents a two-manpower NAND. Here, the explanation will be limited to the use of an N-type substrate.
第１図の論理回路ブロックの大きさを示す外枠１７の原
点（０，０）からＰウェル領域とＮ型基板の境界を示す
１６までの領域がＮチャンネル側で、境界線１６より原
点から見て遠ざかる領域がＰチャンネル側である。The area from the origin (0,0) of the outer frame 17 indicating the size of the logic circuit block in FIG. 1 to 16 indicating the boundary between the P well region and the N type substrate is the N channel side, and from the origin The area that you see and move away from is the P channel side.
Ｎチャンネル側について見ると、電源供給の金属２より
、コンタクト６を介してソース領域１３に電位が供給さ
れる。この時、ソース領域へのコンタクト６の中心は、
外枠１７上に配置し、多結晶性シリコン８，９がゲート
電極となって構成されるチャンネル領域１８．１９が直
列に接続さ几、ドレイン領域１４からコンタクト７を介
して金属１５に接続される。Looking at the N-channel side, a potential is supplied from the power supply metal 2 to the source region 13 via the contact 6. At this time, the center of the contact 6 to the source region is
Channel regions 18 and 19 disposed on the outer frame 17 and configured of polycrystalline silicon 8 and 9 as gate electrodes are connected in series, and connected from the drain region 14 to the metal 15 via the contact 7. Ru.
次に、Ｐチャンネル側において、電源供給の金属１から
コンタクト３を介してソース領域１０に電位を供給する
。この時、コンタクト３の中心は、論理回路ブロックの
外枠１７上に配置する。Next, on the P channel side, a potential is supplied from the power supply metal 1 to the source region 10 via the contact 3. At this time, the center of the contact 3 is placed on the outer frame 17 of the logic circuit block.
多結晶性シリコン８がゲート電極となって構成されるチ
ャンネル領域２０を介してドレイン領域１１からコンタ
クト４を介して金４１５に接続さｎる。また電源供給の
金Ｍ４１よりコンタクト５を介してソース領域１２に接
続さｎ１多結晶性シリコン９がゲートＩＩＥ極となって
構成さｎるチャンネル領域２１を介してドレイン領域１
１からコンタクト４を介して金属１５に接続さｎる。こ
のように配置することで本発明の一実施例である２人力
ＮＡＮＤが構成される。Polycrystalline silicon 8 serves as a gate electrode and is connected to gold 415 from drain region 11 through contact 4 through channel region 20 . Further, the gold M41 for power supply is connected to the source region 12 via the contact 5, and the drain region 1 is connected to the drain region 12 via the channel region 21, where the polycrystalline silicon 9 serves as the gate IIE pole.
1 to metal 15 via contact 4. By arranging them in this manner, a two-manpower NAND which is an embodiment of the present invention is constructed.
以上説明したように本発明は、１つの論理回路ブロック
の異電源のソース位置を同一の垂直線上に配置し、さら
に異電源のソースの水平方向の位置を任意の論理回路ブ
ロックで一定とすることによって、レイアウト設計にお
いて、工つの論理回路ブロックとミラー状態で任意の論
理回路ブロックを電源側で重ね合わせることで、Ｎチャ
ンネル側、Ｐチャンネル側のソース領域は、それぞれ重
なり合い、２つの論理ブロックへ１対の電源供、給源で
まかなうことが可能となり、２つの論理回路ブロックで
１つのソース領域が削減さｎ、従来より高密度設計可能
な半導体集積回路を提供できる。As explained above, the present invention arranges the sources of different power sources of one logic circuit block on the same vertical line, and furthermore, makes the horizontal position of the sources of different power sources constant for any logic circuit block. Therefore, in the layout design, by overlapping any logic circuit block on the power supply side in a mirror state with the logic circuit block of the construction, the source regions on the N-channel side and the P-channel side overlap, respectively, and one logic circuit block is divided into two logic blocks. It is now possible to supply power with a pair of power sources, and one source area can be reduced with two logic circuit blocks, making it possible to provide a semiconductor integrated circuit that can be designed with higher density than before.
第１図は、本発明の相補ＭＯＳ形半導体集積回路装置の
パターンレイアウトであり、第２図は、従来例で示す平
面図である。
１．２・・・・・・電源供給用の金属、３，４，５，６
．７・・・・・・コンタクト、８，９・・・・・・多結
晶シリコン、１０．１２．１３・・・・−・ソース領ｊ
ｒＬ １１，１４・・・・・・ドレイン領域、１５・
・・・・・出力用金属、１６・・・・・・Ｐウェル領域
とＮ基板との境界、１７・・・・・・論理回路ブロック
の外枠、１８，１９，２０．２１・・・・・・チャンネ
ル領域。FIG. 1 is a pattern layout of a complementary MOS semiconductor integrated circuit device of the present invention, and FIG. 2 is a plan view of a conventional example. 1.2... Metal for power supply, 3, 4, 5, 6
．． 7... Contact, 8, 9... Polycrystalline silicon, 10.12.13... Source region j
rL 11, 14...Drain region, 15.
... Output metal, 16 ... Boundary between P well region and N substrate, 17 ... Outer frame of logic circuit block, 18, 19, 20.21 ... ...Channel area.
Claims (1)
において、相補ＭＯＳ形の論理回路ブロックのＮ型、Ｐ
型のソース位置が論理回路ブロックと、ミラー状態で同
一の論理回路ブロックまたは他の論理回路ブロックとを
重ね合わせた時に、Ｎ型ソース、Ｐ型ソースがそれぞれ
完全に重なるよう配置することを特徴とした相補ＭＯＳ
形半導体集積回路装置。In the pattern layout of a complementary MOS type semiconductor integrated circuit device, N type and P type of complementary MOS type logic circuit block
The type source position is characterized in that when a logic circuit block is overlapped with the same logic circuit block or another logic circuit block in a mirror state, the N-type source and the P-type source are arranged so that they completely overlap each other. Complementary MOS
type semiconductor integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60166482A JPH0758762B2 (en) | 1985-07-26 | 1985-07-26 | Complementary MOS semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60166482A JPH0758762B2 (en) | 1985-07-26 | 1985-07-26 | Complementary MOS semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6226853A true JPS6226853A (en) | 1987-02-04 |
| JPH0758762B2 JPH0758762B2 (en) | 1995-06-21 |
Family
ID=15832216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60166482A Expired - Fee Related JPH0758762B2 (en) | 1985-07-26 | 1985-07-26 | Complementary MOS semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758762B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6352440A (en) * | 1986-08-22 | 1988-03-05 | Fujitsu Ltd | Laying-out method for integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5964047A (en) * | 1982-03-22 | 1984-04-11 | ペー・エフ・コスメテイック | Face massage apparatus |
| JPS6074644A (en) * | 1983-09-30 | 1985-04-26 | Fujitsu Ltd | Cmos gate array |
-
1985
- 1985-07-26 JP JP60166482A patent/JPH0758762B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5964047A (en) * | 1982-03-22 | 1984-04-11 | ペー・エフ・コスメテイック | Face massage apparatus |
| JPS6074644A (en) * | 1983-09-30 | 1985-04-26 | Fujitsu Ltd | Cmos gate array |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6352440A (en) * | 1986-08-22 | 1988-03-05 | Fujitsu Ltd | Laying-out method for integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0758762B2 (en) | 1995-06-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |