JPS61191047A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the integration degree of the entire chip, by arranging cells so that the parts of the outer frames of the cells agree with the facing sides, and overlapping at least one contact hole of each cell with the other contact hole of another cell. CONSTITUTION:The shapes of metal layers 42 and 52 in P-channel regions 2 and 22 of first and second standard cells 41 and 51 have a U-shape and an L shape. Likewise, the shapes of metal layers 43 and 53 in N-channel regions have an L shape. The cells 41 and 51 are arranged so that the parts of outer frames 44 and 54 of the cells agree with facing sides. Then a contact hole 72 in a P<+> source region 52 of the cell 41 is overlapped with a contact hole 271 in a P<+> type source region 25 of the cell 51. In comparison with a conventional device, the width of the cell line can be shortened by the amount of one source region and by the amount of a gap L between the source regions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, which is composed of a plurality of standard cells.

[Technical background of the invention]

As is well known, when a standard type automatic wiring program is executed, mask patterns for standard cells are designed in advance, and those cells are placed and routed by an automatic placement and wiring program according to logical connection descriptions.

Here, conventional examples of mask-shaped mother turns of standard cells are shown in FIGS. 4 and 5. However, the example is complementary type (C) M
Uses an OS circuit.

In FIG. 4, reference numeral 1 denotes a first standard cell constituting a NAND gate consisting of a P channel region 2 and an N channel region 3, and is surrounded by an outer frame 4. As shown in FIG. Said P
In the channel region 2, Pl source regions 5□ and 5□ connected to a power supply potential (VDD) are provided, respectively, and a p+ type drain region 6 is provided. A contact hole 71 with a constant width is provided in the source region 51p52.
Contact holes 73 having the same width are provided in p72 and drain region 6, respectively. The source regions 5□, 5
2 are connected through a contact hole '1+72 by a metal layer 8 that is at a power supply potential or a ground potential. on the other hand,
The N channel region 3 is provided with a N1 north region 9 that is at ground potential, and is also provided with an N''W drain region 10 connected to the drain region 6. Contact holes 74 #75 are provided in the region 10, respectively. Also, in the P channel region 2 and the N channel region 3, dart electrodes 11, 11 made of polycrystalline silicon are formed along the longitudinal direction of the cell 1. Note that 12 in the figure is a metal layer connected to the drain region 10 via a contact hole 74;
3 is a diffusion layer region.

In FIG. 5, reference numeral 21 indicates a second inverter comprising a P channel region 22 and an N channel region 23.
This standard cell is surrounded by the outer frame 24. The P channel region 22 is provided with a P+ type source region 25 and a P+ type drain region 26, which are connected to a power supply potential. The source, drain/region 25°2
6 has a contact hole 271.6 having a constant width. ．． 2y2 are provided respectively. Further, in the source region 25, a metal layer 28 having a power supply potential or a ground potential is formed in the contact hole 21.
1. On the other hand, the N-channel region 23 includes a joint-shaped source region 29 connected to the ground potential;
and a joint type drain region 30 are provided. Contact holes 273 and 274 having a constant width are provided in the source and drain regions 29 and 30. Further, in the P channel region 22 and the N channel region 23, an r-to electrode 31 made of polycrystalline silicon is provided overflowing in the longitudinal direction of the cell 21. Note that 32 in the figure is a metal layer connected to the source region 29 via the contact hole 273.

Conventional 1 For example, a semiconductor integrated circuit device composed of an outer frame 4 of a first cell 1 and a second cell 2, as shown in FIG. (a part of the outer frame 24 of 2 overlaps), and channel regions Z and XZ of the same type
(or 3.23) are arranged horizontally in a row.

[Problems with background technology]

However, the outer frame 4 of the first cell 1 and the second cell 21
Since the structure is such that a part of the outer frame 24 of the
Two contact holes 72.271 are arranged in parallel.

Also adjacent. In each source region 52.25 of the P channel regions 2, 22, these source regions 5z.

It becomes necessary to leave a gap based on the design criteria of No. 25. As a result, the degree of integration of the entire chip decreases.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is a semiconductor integrated circuit device that can reduce wasted areas caused by automatic placement and improve the degree of integration of the entire chip without changing the conventional automatic placement and routing program. The purpose is to provide

[Summary of the invention]

The present invention provides a diffusion layer provided on at least one of the left and right sides and serving as a power supply potential, a metal layer connected to the diffusion layer through at least one contact hole and serving as a power supply potential or a ground potential, and By arranging a plurality of cells having an outer frame passing through the center so that a portion of the outer frame of each cell coincides with the opposite side, at least one contact hole of each cell is overlapped and The aim is to improve the degree of integration of the entire chip.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

Here, the semiconductor integrated circuit device shown in FIG.
The standard cell shown in FIG. 3 and the second standard cell shown in FIG. In addition, Figure 2 is Figure 4 (conventional)
Furthermore, since FIG. 3 corresponds to FIG. 5, the same members are given the same reference numerals, explanations thereof will be omitted, and only the differences will be explained.

In FIG. 2, the metal layer 42 in the P-channel region 2 of the first standard cell 41 has a U-shape, and the metal layer 43 in the N-channel region 3 has an L-shape. Also,
The outer frame (single-dot chain (2) 44 is a P+ type source region 51 * 5
It is provided so as to pass through the center of the t-base contact hole 71r72 and the center of the contact hole 74 of the f-base source region 9, respectively.

In FIG. 3, the metal layer 52 of the P channel region 22 and the metal layer 53 of the N channel region 23 of the second standard cell 51 each have an L-shape. Further, the outer frame (dotted chain line) 54 is provided so as to pass through the center of the contact hole 27! of the P" deaf source region 25 and the center of the contact hole 274 of the ! type source region 29. The method of connecting the metal layer to the source region via the contact hole is the same as the conventional method.

The device of the present invention includes a first standard cell 41 in FIG.
82 standard cells 51 shown in FIG. 3 are arranged so that parts of the outer frames 44 and 54 of the cells 41 and 51 coincide with each other on opposing sides, as shown in FIG.

According to the present invention, each standard cell 41,
51 are arranged so that parts of the outer frames 44 and 54 of the cells 41 and 51 coincide with each other on opposite sides, so that the contact hole of the P+ type source region 5z of the cell 41 is 1z and P+ type source region 25 of cell 51
The contact holes 271 overlap, and the distance between one source region and the source regions is 1! compared to the conventional method. l! The width of the cell row can be reduced by L. In fact, for example, the width of a cell row in which 50 cells in FIG. 4 and 50 cells in FIG. A total of 100 cells in Figures 2 and 3 in the same proportion.
The widths of cell rows arranged in individual columns were compared. As a result, there will be some differences in how they are arranged, but the width of the source area) will be 2
The width decreases by 5 to 40W. Furthermore, when expressed in terms of the number of cells, the width of the cell row is reduced by 7 to 14 cells in FIG. 2, and expressed as a percentage, the width of the cell row is reduced by 19 to 35% compared to the conventional method. In conclusion, the present invention is significantly superior to the conventional technology.
It can be confirmed that the degree of integration of the entire chip can be improved.

Incidentally, in the above embodiment, a case has been described in which the source region 52 of the first standard cell 31 and the source region 25 of the second standard cell 44 have the same shape.
The shape is not limited to this, as long as the shape of the dovetails is the same.

In the above embodiment, a case has been described in which the cell is composed of two types of standard cells, but the present invention is not limited to this, and the cell may be composed of three or more types of standard cells. However, source regions having substantially the same shape must be symmetrically provided on opposite sides of adjacent cells.

In the above embodiment, a case has been described in which the source regions of the P-channel region related to the first standard cell are provided on both sides of the cell, but the present invention is not limited to this, and even when the source regions are provided on the right side of the cell. Similarly, a source region may also be provided on the right side of the second standard cell.

In the above embodiment, a case was described in which two types of standard cells are arranged so that a part of their respective outer frames coincide with each other on opposite sides. An example of the semiconductor integrated circuit device is the one shown in FIG. In this device, the first standard cell 31 shown in FIG. 2 and the second standard cell 41 shown in FIG. It is a close-up of the According to the apparatus shown in FIG. 7, although it is inferior to the above embodiment,
Compared to the conventional method, the cell width can be reduced by the amount of void.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a semiconductor integrated circuit device that can improve the degree of integration of the entire chip.

[Brief explanation of the drawing]

FIG. 1 is a pattern plan view of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a top view of a first standard cell according to the same device. FIG. 3 is a pattern plan view of a second standard cell related to the same device, FIG. 4 is a no+turn plan view of a first standard cell related to a conventional semiconductor integrated circuit device, and FIG. 5 is a pattern plan view related to the same device. FIG. 6 is a pattern plan view of a conventional semiconductor integrated circuit device, and FIG. 7 is a pattern plan view of an improved semiconductor integrated circuit device. It is a turn top view. 2...P channel area, 3...N channel area, 5
,．． 52.9,25,29...source area, 6°70
．． 26.30...Drain region, 21-7. . 271-274...Contact hole, 11,3
J..."') % pole, 41 * 51... standard cell, 44.54... outer frame, 42, 43,
52.53... Gold layer. Fig. 1 43 '33 @2 Fig. 3 Fig. 4 Fig. 5 Fig. 12 3z Fig. 6 Ii! Figure 7

Claims (2)

[Claims] (1) In a semiconductor integrated circuit device formed by using a cell library of MOS circuits consisting of logic blocks registered in advance on a graphic processing device, and performing automatic placement and wiring by an electronic computer based on predetermined connection information. , a diffusion layer serving as a power supply potential provided on at least one of the left and right sides, a metal layer serving as a power supply potential or a ground potential connected to this diffusion layer via at least one contact hole, and passing through the center of the contact hole. 1. A semiconductor integrated circuit device comprising a plurality of standard cells each having an outer frame arranged so that a part of the outer frame of each cell coincides with the opposite side. (2) A semiconductor integrated circuit device according to claim 1, characterized in that diffusion layers serving as a power supply potential are provided on both sides of the standard cell.