JPH01278743A - Cmos integrated circuit - Google Patents

Abstract

PURPOSE:To contrive the improvement of the integration degree of a CMOS integrated circuit by a method wherein at least two adjacent standard cells are arranged holding at least one of source regions in common. CONSTITUTION:An inner-cell power supply wiring Vcc and an innercell grounding wiring GND are respectively arranged on the upper and lower sides of a prescribed rectanguilar region within a semiconductor chip. Standard cells, which are respectively arranged with a source region of a P-channel MOS transistor connected to the wiring Vcc consisting of a first-layer metal film 103 through contacts 102 and a source region of an N-channel MOS transistor connected to the innercell wiring GND consisting of a first-layer metal film 103 through contacts 102, are provided on the right side of the rectangular region. Moreover, at least two adjacent standard cells a1 and a2 are arranged holding one of the source regions in common. Thereby, as the two standard cells not only are merely arranged in contact to each other, but also can be arranged superposing a part of a width W, the integration degree of a CMOS integrated circuit is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS integrated circuit, and particularly to a standart cell type CMOS integrated circuit.

[Conventional technology]

In chip layout technology for integrated circuits, this is a standard method in which cells with a constant height (standard cells) corresponding to functional circuits such as inverters, NAND, NOR, etc. are used and arranged in an array to layout the entire chip. A technology called cell array is known. An example of a conventional standard cell is shown in FIG. The in-cell power supply wiring ■cc and the in-cell ground wiring GND formed of the first layer metal film are arranged on the upper and lower sides of the rectangular area, respectively, and between them, the n-channel region is arranged in the upper half and the n-channel region is arranged in the lower half. By connecting the transistors made in each region inside the cell, a two-man NAND gate is constructed, with the input being a polycrystalline silicon film and the output being a second-layer metal film that can be taken out in the vertical direction of the cell. defines the cell outline. Furthermore, as shown in FIG. 5, such cells are arranged in an array, wiring areas are provided between cell columns, and wiring is formed between the cells to form a chip.

[Problem to be solved by the invention]

The conventional standard cell type CM mentioned above.

S integrated circuits have completely separated transistor areas and wiring areas, as well as inverters and NANDs.

Because a cell is formed for each functional circuit such as NOR, and the cells are placed completely separated, the area is 1.3~1.3~1.3 mm compared to a hand-designed integrated circuit. It has the drawback that it is about 1.5 times larger and the degree of integration is lower.

[Means to solve the problem]

The CMOS integrated circuit of the present invention has an in-cell power supply wiring and a ground wiring arranged respectively on the upper side and the lower side of a predetermined rectangular area in a semiconductor chip, and has an in-cell power wiring and a ground wiring arranged on the right (or left) of the rectangular area.
pMOS connected to the in-cell power supply wiring on each side
In a CMO8 integrated circuit having a standard cell formed by arranging a source region of an nMO3) transistor connected to a source region of a transistor and a ground wiring within the cell, at least two adjacent standard cells are connected to at least one of the source regions. They are arranged so that one side is shared.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a pattern diagram showing a cell array according to a first embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram.

In this embodiment, two two-manufactured NAND gates are arranged next to each other, and the in-cell power supply wiring VCC is arranged on the upper and lower sides of a predetermined rectangular area in the semiconductor chip.
and a ground wiring GND, and an in-cell power supply wiring V made of a first layer metal film on the right side of the above-mentioned rectangular area. pMO3)-transistor source region connected to 0 through contact 102 and intra-cell ground wiring G consisting of the first layer metal film.
In a CMOS integrated circuit having a standard cell formed by arranging a source region of an nMOS transistor connected to ND by a contact 102, at least two adjacent standard cells a1 and a2 each share one of the aforementioned source regions. It is said that it is arranged as follows.

Note that the polycrystalline silicon films 101-1 to 101-4 are MO
S) - gate electrode of transistor, second layer metal film 1
05-1, 105-2 is drain head mounted 104-1, 10
These are output lines connected to 4-2, respectively.

Standard cell a1 has almost the same pattern as shown in FIG. 4, and standard cell a2 has a pattern that is mirror-symmetrical to al.

Therefore, it is not only possible to simply arrange two of al and a2 adjacent to each other, but also to overlap the parts of the width W, so that the degree of integration is improved.

FIG. 3 is a pattern diagram of cell rows showing a second embodiment of the present invention. In this embodiment, three two-man-powered NAND gates are arranged side by side, and the standard cells b1 to b3 all have the same shape. Overlapping area on the left and right (width W
) is formed. For this reason, in the first embodiment, there is an overlapping area only on one side of the cell, so when multiple cells are lined up, only adjacent mirror-symmetric cells can be overlaid, or the present example Since there are overlapping areas on both sides, there is an advantage that overlapping processing can be performed on as many pieces as necessary.

Although the NAND gate has been described above, it is clear that the present invention can also be applied to a NOR gate.

〔Effect of the invention〕

As explained above, in the present invention, by forming the source regions of pMOS transistors or nMO transistors vertically aligned with the right side or left side of the standard cell, the source regions of adjacent cells can be used in common.
By overlapping cells, the width of the cell column can be made smaller than the previous cell column (or more cells can be placed in the - column).
This has the effect of improving the degree of integration of MOS integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a pattern diagram showing a cell array according to the first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram, FIG. 3 is a pattern diagram showing a cell array according to the second embodiment, and FIG. 4 is a pattern diagram showing a cell array according to the second embodiment. A pattern diagram of a standard cell in a conventional example, and FIG. 5 is a plan block diagram of a semiconductor chip showing a conventional example. 100n, 100p, 20On, 200p. 300n, 300p...diffusion layer formation region, 101-1
〜101-4, 201-1〜201-6゜301...
Polycrystalline silicon film, 102, 202° 302... contact, 103, 203, 303... first layer metal film,
104-1, 104-2, 204-1, 304... through hole, 105-1, 105-2, 205-1. =
205-2, 205'-3°305-...Second layer metal film, a, al, a3. bl. b3... Standard cell, GND... In-cell ground wiring, Vcc... In-cell power supply wiring.

Claims (1)

[Claims] A pMOS transistor having an in-cell power supply wiring and a ground wiring arranged respectively on the upper and lower sides of a predetermined rectangular area in a semiconductor chip, and connected to the in-cell power supply wiring on the right (or left) side of the rectangular area, respectively. and a source region of an nMOS transistor connected to the intra-cell ground wiring, wherein at least two adjacent standard cells have at least one of the source regions A CMOS integrated circuit characterized by being arranged in a shared manner.