JPH0290649A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to make large the widths of main powersupply wiring layers and to supply stably a potential to basic cells in a master slice system of a gate array, in which the basic cells are arranged in a configuration that transistors oppose to one another, by a method wherein the main power-supply wiring layers are arranged between the basic cells. CONSTITUTION:101 to 104 are P-channel transistors, 105 to 108 are N-channel transistors, 109 is a wiring layer to supply the potential of a VSS, 110 are wiring layers (the wiring layer to correspond to the 109 is a main power-supply wiring layer and the wiring layers to correspond to the 110 are branch power-supply wiring layers) to supply the potential of the VSS to a diffused region constituting the N-channel transistors through vias, 111 is a main power-supply wiring layer of a VDD and 112 are branch power-supply wiring layers of the VDD. The main power-supply wiring layers are arranged between basic cells and a potential can be supplied to the diffused region constituting the transistors in the basic cells by the branch power-supply wiring layers and the vias. In case the main power supply wiring layers are arranged between the basic cells, there is no need to consider wiring regions in the cells and the potential can be supplied stably because the widths (W1) of the wiring layers are decided by the distance between the basic cells.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a method for supplying power to basic cells used in a master slice gate array.

[Prior Art] Currently, in master slice type gate arrays that realize dedicated logic by changing the wiring process, the power supply wiring layer accompanying the power supply to the basic cells connects the logic circuits to inverters, NANDs, Since it is configured by N0R1,
VDD to Pch transistor, V to Nch transistor
The wiring for supplying the potential of VDD, which is intended to supply the potential of SS, is located perpendicularly to the gate electrode of the transistor over the diffusion region that is a component of the Pch transistor in the basic cell, and similarly, The wiring for supplying the potential of vSS is located perpendicular to the gate electrode on the diffusion region of the Nch transistor, and two power supply wiring layers are present in the basic cell. [Problems to be Solved by the Invention] When a basic cell has two power supply wiring layers to the transistors of the basic cell as in the past, the wiring within the basic cell required to configure a logic element in the basic cell. For the purpose of enlarging the area, the width distance of the power supply wiring layer is limited. Also,
There is a possibility that the power supply wiring layer becomes an obstacle to the wiring layer within the basic cell that constitutes the logic element. Therefore, it is difficult with conventional power supply methods to increase the width of the power supply wiring layer and supply a uniform and stable potential to the basic cells of the entire chip for semiconductor integrated circuits with large chip sizes. be. The present invention solves the above-mentioned problems, and provides a power supply that stably supplies potential to the basic cells without interfering with the wiring layer within the basic cells that constitute the logic elements in the master slice gate array. The purpose is to provide a supply method. [Means for Solving the Problems] The semiconductor integrated circuit device of the present invention has a master slice type gate array in which basic cells constituted by PCh transistors and Nch transistors are regularly arranged. A PCh in which other basic cells constitute a basic cell in a direction parallel to the gate electrode in that basic cell with respect to the cell.
Shape where transistor and Pch transistor face each other, N
The basic cells in which the ch transistor and the Nch transistor are located opposite each other and are adjacent to the Nch transistor side of the basic cell in a direction parallel to the gate electrode in the basic cell share a wiring layer that supplies the potential to the Nch transistor. However, it is characterized in that basic cells adjacent to the Pch transistor side share a wiring layer that supplies a potential to the Pch transistor. [Embodiment] Figure 1 shows the arrangement structure of the basic cell and power supply wiring layer in the present invention.
transistors, 105 to 108 are Nch transistors, 109 is a wiring layer that supplies the potential of vSS, 110 is V
A wiring layer that supplies the potential of SS to the diffusion region constituting the Nch run disk via vias (hereinafter, the wiring layer corresponding to 109 will be referred to as the main power supply wiring layer, and the wiring layer corresponding to 110 will be referred to as the main power supply wiring layer, ), 111 is a VDD main power supply wiring layer, and 112 is a VDD main power supply wiring layer. Conventionally, the wiring for supplying potential was located on the diffusion region of the transistor, and there were two power supply wiring layers in the basic cell, but P
When basic cells are arranged in such a way that a channel transistor and a Pch transistor or an Nch transistor and an Nch transistor face each other, the main power supply wiring layer is arranged between the basic cells as shown in the present invention, and the main power supply wiring layer and vias are used to connect the basic cells to each other. A potential can be supplied to a diffusion region that constitutes a transistor within a cell. When the main power supply wiring layer is placed between basic cells, the width (Wl) of the wiring layer is determined by the distance between the basic cells, so there is no need to consider the wiring area within the cell as in the conventional case, and the potential can be stabilized. It is possible to set it large so that it can be supplied. In addition, if the power supply wiring layer is located within the basic cell, it is impossible to set the intracell wiring layer at the position shown in 113 or 6118, but in the embodiment shown in Fig. 1, the area excluding the main power supply wiring layer is Can be set to Figure 2 shows the layout structure of the basic cells and power wiring layer when the distance between the basic cells is small. In Figure 2, the transistors in the basic cells are connected directly from the main power wiring layer via vias, as in the conventional case. Since a potential is supplied to the constituent diffusion regions, it is impossible to set the intra-cell wiring layer at a position passing above 211 in the figure perpendicularly to the gate electrode in the basic cell, but this implementation In the example, the width of the main power wiring layer (
W2) can be set large, and the potential can be stably supplied. [Effects of the Invention] As described above, according to the present invention, in a master slice type gate array in which basic cells are arranged in such a shape that Pch transistors and Pch transistors, and Nch transistors and Nch transistors face each other, A power supply method in which a main power wiring layer is placed between cells allows the width of the main power wiring layer to be increased, making it possible to stably supply potential to the basic cells and setting the main power wiring layer. This has the effect that the wiring area within the basic cell can be enlarged.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the arrangement structure of basic cells and power wiring layers in the present invention, and FIG. 2 is a diagram showing an example of the arrangement of basic cells and power wiring layers when the distance between basic cells is small. 101, 102. 202. 105. 206. 203, l 06°207. 09, 209 1 Ol 210 11 ・ ・ ・ ・ l 2 ・ ・ ・ 13 to 118 103, 104.201°...Pch transistor 107.108.205, ..Nch transistor...vSS main power wiring layer...vSS Sub-power wiring layer...VDD main power wiring layer...VDD sub-power wiring layer...Position of the power wiring layer when the power wiring layer is set on the via 119.211...Via wl, w2...・More than the width of the main power wiring layer Applicant: Seiko Epson Corporation

Claims (1)

[Claims] In a master slice type gate array in which basic cells composed of Pch transistors and Nch transistors are regularly arranged, one basic cell is connected to another basic cell in a direction parallel to the gate electrode in that basic cell. The cell is located in a shape in which Pch transistors and Pch transistors that constitute a basic cell face each other, and Nch transistors and Nch transistors that form a basic cell face each other, and are located on the Nch transistor side of the basic cell in a direction parallel to the gate electrode in the basic cell. A semiconductor integrated circuit device characterized in that adjacent basic cells share a wiring layer for supplying a potential to an Nch transistor, and basic cells adjacent to the Pch transistor side share a wiring layer for supplying a potential to a Pch transistor.