JP2879855B2 - Semiconductor integrated circuit and its design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] Regarding a semiconductor integrated circuit and a method of designing the same, to achieve high integration easily by extending the current layout method by sharing elements without overlapping cells For this purpose, the side of a standard cell that can be shared with an adjacent standard cell has an attribute of being sharable. For a standard cell having this attribute, the standard layout pattern of the original cell In addition, a layout pattern for sharing is also prepared. When the standard cells can be shared between adjacent cells, a layout pattern for sharing is used as the layout pattern of the adjacent cells, and these are closely arranged. Configuration.

[Industrial applications]

 The present invention relates to a semiconductor integrated circuit and a method for designing the same.

In order to shorten the development period of LSI, it is common to use the standard cell method for not only custom products but also general-purpose products, but on the other hand, improvement of integration density is an essential condition in terms of yield, cost reduction, etc. Has become.

[Conventional technology]

In a conventional general standard cell layout method, cells corresponding to logic gates such as NAND and NOR are created as a single element that constitutes an element (cell). The cell generally has a rectangular shape, in which necessary transistors, connection conductors, electrode windows, and the like are formed, and the outer peripheral portion is, as it were, a blank. Therefore, even if a plurality of such rectangular cells are closely arranged on the substrate, a short circuit accident does not occur due to the connection of certain portions of adjacent cells to each other.

However, for example, in the case of a CMOS cell, the periphery is particularly rectangular.
The source region of the MOS transistor comes to the long side, and these are connected to V _cc and V _ss of the power supply and become the same potential, so that in many cases, contact or short-circuit may occur.

If contact / short circuit is allowed, the margin around the periphery becomes insoluble, and a part of the margin can be further overlapped. In this way, the degree of integration can be further improved.

However, overlay has some problems. In other words, there is no problem in superimposing a part of the periphery (however, this is based on the data, and the mask is created by taking a logical sum). Or
It is necessary to check whether or not. By the way, the standard cell method is characterized in that it is only necessary to look at the periphery of the cell and there is no need to pay attention to the internal pattern, but it is troublesome to check the internal pattern near the periphery for superposition. .

[Problems to be solved by the invention]

As described above, in the layout method of the standard cell system, the cells may be arranged side by side, and the cells can be treated as simple boxes. However, when superimposing,
If it is necessary to recognize the pattern inside the cell when arranging the cell, it becomes very difficult to handle the current arrangement and wiring tool.

An object of the present invention is to improve such a point, and an object of the present invention is to achieve high integration easily by extending a current layout method by sharing elements without overlapping cells.

[Means for Solving the Problems] In the present invention, a side that can be shared between cells is provided with the attribute, and a cell having this attribute is used when a single cell is used as usual, and when one cell is adjacent to an adjacent cell. When the parts are used in common, respective layout patterns are prepared correspondingly.

Referring to FIG. 1, A1 to A4 indicate various types of standard cells, A1 is a NOR gate, and A2 is a NAND gate.
The gate, A3 is an inverter, and A4 is a clocked inverter, all of which are CMOS type.

In the present invention, in the conventional standard cell shown in FIGS. A1 to A4, the side (indicated by an arrow) that can be shared with an adjacent cell is given an attribute indicating that. The cell having this attribute is also provided with a cell pattern as shown in FIGS. This B1 corresponds to A1, B2 corresponds to A2, and so on.

As it is apparent from the comparison to FIG. 1 A1 and B1, B1 is excised left portion of the A1 (part of the left from the center of the contact window C _1), the gate electrode G ₁ was slightly modified (contact windows C but _two, the contacts were to perform in the above / bottom gate electrode C ₁₎ is intended. B2 and A2, …… etc. follow this.

[Action]

By preparing the standard cell pattern in this way, when a plurality of standard cells are closely arranged, the required area is reduced, and the degree of integration can be improved.

This will be described with reference to FIG. 2. (a) is a layout laid out by a conventional method, and a NAND gate having a margin around the periphery is shown.
A1 and inverter A3 are closely arranged. (B) shows common patterns B1 and B3 for patterns A1 and A3. When A1 and A3 can be shared, B1 and B3 are used, and they are brought into close contact with each other to obtain the state shown in FIG. 2 (c). In this way, the area occupied by the dotted frame region F can be reduced as compared with the conventional method shown in FIG.

〔Example〕

More specifically to FIG. 1, W ₁ a CMOS NOR gate of FIG A1 is n-well, W ₂ is p-well are both rectangular, p-type diffusion region DA _1, n-type diffusion region DA ₂ in this There are formed, they become the source S and the drain D of the p-channel MOS transistor Q _1, the source S and the drain D of Q _2, n-channel MOS transistors Q ₃ and Q _4. Transistors Q ₁ and Q ₂ series, Q ₃
And Q ₄ are a parallel, source S of Q ₁ is the power V _cc by a metal wiring L _1, a source S of Q ₃ and Q ₄ are connected by metal wiring L ₂ to the power source V _ss. Gates G ₁ and G ₂ have two inputs and output O
UT is taken from the drain D of the drain Q ₂ 'and Q _3, Q _4.

The metal wirings L ₁ and L ₂ are the same in the hatched portions, and when a plurality of cells are arranged adjacent to each other, they are commonly formed in these cells as shown in FIGS. n-well W
_{The same} applies to ₁ (rectangular shape, the left, right, and upper sides are the outer peripheral edge of the cell, and the lower side is a dotted line) and p-well W ₂ (also a rectangular shape similar to W ₁ ) when multiple cells are arranged adjacently Figure 2
As shown in (a) (c), these cells n-well W ₁ and the p well W ₂ is formed as a series of ones.

As shown in FIG. 1 Al to A4, the left cell, right side is the source region S, the power supply V _cc, often connected to V _ss. If adjacent cells have source regions that are both connected to V _cc or V _ss , they can be shared (communicate between source regions)
May do it. Therefore, in the common patterns B1 to B4, the common sides are cut at the center line of the contact window with the power supply, and the width is reduced by the cut amount. At this time, the contact window of the gate electrode is often in the way, but this can be dealt with by changing the position of the contact window.

FIG. 3 is also an example in which the area occupied by the cell array is reduced according to the present invention, and a conventional cell array corresponding thereto is shown in FIG. (A) the only F _1, can reduce the required area by F ₂ in (b).

〔The invention's effect〕

As described above, according to the present invention, in the design of the standard cell system, a part of the elements is shared without overlapping the cells, the effect of improving the integration density of the LSI is achieved, and the chip area is reduced. , Improve yield,
In addition, it greatly contributes to cost reduction.

Further, in the present invention, when sharing is performed, a pattern for sharing is used, and it is only necessary to bring the patterns into close contact. Therefore, as in the case of overlapping, the pattern inside the cell is checked to determine whether or not overlapping is possible. There is no necessity, and the inside can be treated as a dark box like a conventional standard cell.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a standard cell pattern of the present invention, FIG. 2 is an explanatory view of an arrangement procedure of standard cells, FIG. 3 is a plan view showing an arrangement example of the present invention, and FIG. FIG. In FIG. 1, A1 to A4 are the original patterns of the standard cell, B1
B4 is a pattern for sharing.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-96250 (JP, A) JP-A-1-278743 (JP, A) JP-A-58-119649 (JP, A) JP-A-63-1988 215062 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 21/82, 27/118

Claims (4)

(57) [Claims] If the first standard cell and the first standard cell can share an edge with an adjacent first standard cell, the edge can be shared with the edge of the first standard cell that can be shared. And a second standard cell having a cell pattern that can be shared with an adjacent standard cell, the second standard cell being provided in correspondence with the first standard cell having the attribute. A semiconductor integrated circuit, wherein cells are arranged adjacent to each other. 2. The first standard cell according to claim 1, wherein the second standard cell is cut at a center line of a contact window of a power supply on a side to be shared, and a position of a contact window of a gate electrode is set to be different from that of the first standard cell. Is a semiconductor integrated circuit characterized by being different. 3. When the first standard cell and the first standard cell can share an edge with an adjacent first standard cell, the first standard cell can be shared with an edge of the first standard cell that can be shared. And a second standard cell having a cell pattern that can be shared with an adjacent standard cell, provided in correspondence with the first standard cell having the attribute. A method for designing a semiconductor integrated circuit, wherein two standard cells are arranged adjacent to each other. 4. The second standard cell according to claim 3, wherein a side to be shared is cut by a center line of a contact window of a power supply, and a position of a contact window of a gate electrode is set to be equal to that of the first standard cell. A method for designing a semiconductor integrated circuit, wherein the semiconductor integrated circuit is formed differently.