JP2000040809A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the illegal circuit copy by mixedly providing an apparent layout pattern of an actual chip incorporating normally on- and normally off- type transistors and dummy circuits different in logic operation. SOLUTION: N1, N2, P1, P2 are n- and p-type transistors usually forming a circuit constituting an NAND gate having inputs A, B and output C, the threshold voltages of N1, P1 are set lower than usual, N1 is set to a normally on-type and P1 is set to a normally off-type to thereby obtain an inverted value of the input B from the output C, irrespective of the value of the input A. The apparent layout pattern of an actual chip provides an NAND gate with inputs A, B and output C but actually a dummy circuit operating as an inverter with inputs A, B and output C can be constituted. It is possible that a circuit analyzed by connecting adequate signals causing a malfunction to the input A of the dummy circuit cannot normally operate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of preventing an illegal circuit copy of a semi-custom LSI such as a gate array.

[0002]

2. Description of the Related Art In a conventional semiconductor device, a circuit is formed by wiring a plurality of transistors arranged on a chip. A case of a gate array, which can easily copy a circuit, will be described. FIGS. 9 and 10 show an example of a circuit and a layout pattern of a basic cell of a conventional gate array.

In FIG. 9, N1 and N2 are N-type MOS transistors (hereinafter referred to as N-type transistors), P1 and P1.
P2 is a P-type MOS transistor (hereinafter referred to as a P-type transistor). In FIG. 10, N + is an N + diffusion region forming sources and drains of N-type transistors N1 and N2, P + is a source of P-type transistors P1 and P2,
The P + diffusion region forming the drain and PLY are polysilicon forming the gate of each transistor. This basic cell is composed of N-type transistors N1 and N2 and P-type transistors P1 and P2. In the circuit diagram of FIG. 9, the circles indicate terminals that can be drawn out of the basic cell. A desired circuit is formed by wiring between terminals.

[0004]

However, in the conventional semiconductor device, it is possible for a third party to copy a circuit by analyzing the structure of the transistor and the wiring between the transistors based on the layout pattern of the actual chip.
In particular, in a conventional gate array, a circuit is configured by basic cells and wiring arranged regularly in an array,
Since the layout pattern is very simple, a third party can easily copy the circuit mounted on the gate array by analyzing the structure of the basic cell and the wiring between the basic cells from the layout pattern of the actual chip. There was a problem that it was possible.

[0005] In view of the above, it is an object of the present invention to provide a semiconductor device in which illegal circuit copying is difficult.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an apparent layout pattern and logic of a real chip in which a transistor constituting a logic circuit incorporates always-on and always-off transistors. A semiconductor device including a dummy circuit that operates differently.

[0007]

In the semiconductor device of the present invention, the circuit analyzed from the layout pattern of the actual chip differs from the original circuit in the logical operation by mixing the dummy circuits incorporating the always-on and always-off transistors. In this case, illegal circuit copying can be prevented. The always-on and always-off transistors have different process parameters such as impurity concentration.
Since the formation method is the same as that of a normal transistor, it is difficult to determine the always-on type and always-off type transistor from the layout pattern of the actual chip to determine the dummy circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 and FIG. 2 show an example of a circuit and layout pattern of a dummy circuit basic cell constituting a dummy circuit in a gate array. In FIG. 1, N1 and N2 are N-type transistors and P1 and P2 are P-type transistors.
P1 is a transistor whose threshold voltage is always on or off, which is different from normal. A dummy circuit can be formed by using one or more dummy circuit basic cells and wiring the transistors of each cell according to the circuit. Further, a dummy circuit can be formed by using a dummy circuit basic cell and a normal basic cell together.

In FIG. 2, N1 + and N2 + are N + forming sources and drains of N-type transistors N1 and N2.
The diffusion regions P1 + and P2 + are P-type transistors P1 and P2.
P + diffusion region forming the source and drain of P2, PLY
Is polysilicon forming the gate of each transistor. N1 + and P1 + indicated by broken lines are N + and P + diffusion regions having different impurity concentrations from those of the normal region, and form transistors N1 and P1 that have a threshold voltage different from the normal and are always on or always off. N2 + and P2 + are N + and P + diffusion regions forming normal transistors N2 and P2. In a normal basic cell, diffusion regions N1 +, P
1+ is the same as N2 + and P2 +, and is formed as a normal diffusion region. The diffusion regions N1 + and P1 + of the always-on or always-off transistor have different impurity concentrations, but since the formation method is the same as that of a normal diffusion region, N1 + and P1 + have different impurity concentrations from the normal layout pattern of the actual chip. It is difficult to determine that the region is a diffusion region. Therefore, it is difficult to distinguish between the always-on type transistor and the always-off type transistor based on the layout pattern of the real chip to determine the normal basic cell and the dummy circuit basic cell.

In FIG. 2, N + diffusion regions N1 + and N2 +
+ And P + diffusion regions P1 + and P2 + are formed as separate regions, but as shown in FIG. 3, N1 + and N2 +
If P1 + and P2 + are formed as continuous regions, the apparent layout pattern of the actual chip can be the same as that shown in FIG. 10 shown in the conventional example.
In this case, the circuit of the dummy circuit basic cell is a circuit similar to that of FIG. 9 in which the sources or drains of the N-type transistors N1 and N2 and the P-type transistors P1 and P2 are connected.

The arrangement pattern of always-on and always-off transistors in the dummy circuit basic cell is shown in FIG.
The present invention is not limited to the example shown in FIG. 2, and may be any type. For each transistor, any one of an always-on type, an always-off type, and a normal transistor can be selected to configure a dummy circuit basic cell. For example, the diffusion region N2 in FIG.
+ And P2 + are also diffusion regions having different impurity concentrations from normal,
Transistors N1 and N2 are always on, transistor P
1 and P2 may be of the always-off type to constitute a dummy circuit basic cell. Note that the transistor N
If N1 and N2 and P1 and P2 are formed of the same type of transistor, the diffusion regions N1 + and N2 + and the diffusion regions P1 + and P2 + become diffusion regions having the same impurity concentration, and as shown in FIG. Can be formed as one continuous diffusion region, which facilitates the formation of the diffusion region. 1 and 2 of FIG.
One to three transistors are always on or always off transistors.
A basic cell for a dummy circuit can also be configured.

In the basic cell for a dummy circuit shown in FIGS. 1 and 2, the gates of the transistors N1, P1 and N2, P2 are common gates formed of the same polysilicon. A structure in which each gate is separated may be used. Although the dummy circuit basic cell shown in FIGS. 1 and 2 is composed of four transistors, the dummy circuit basic cell can also be composed in a similar manner with other transistor configurations such as a six-transistor configuration.

FIGS. 4 to 8 show examples of the configuration of a dummy circuit using the basic cell for a dummy circuit described above. In the following description, the threshold voltage of a normally-on P-type transistor is described as “higher than normal” because it has a positive value than the threshold voltage of a normal P-type transistor. The threshold voltage of a p-type transistor is
It has been described as "lower than normal" because it has a value in the minus direction from the threshold voltage of a normal P-type transistor. Also,
In FIGS. 4 to 8, the always-on and always-off transistors are surrounded by broken lines.

FIG. 4 shows an example of a dummy circuit of a NAND gate.
Shown in In FIG. 4, N1 and N2 are N-type transistors, and P1 and P2 are P-type transistors, which are circuits that usually constitute NAND gates for inputs A, B and output C. In the circuit of FIG. 4, the threshold voltage of the N-type transistor N1 is set to be lower than normal and the threshold voltage of the P-type transistor P1 is set to be lower than normal to be always off so that the input is always off. Regardless of the value of A, a value obtained by inverting the input B is obtained from the output C. Therefore, the circuit of FIG. 4 becomes a NAND gate of inputs A, B and output C in the apparent layout pattern of the real chip, but can actually constitute a dummy circuit which operates as an inverter of input B and output C. If an appropriate dummy signal that causes a malfunction is connected to the input A of the dummy circuit, it becomes difficult for the circuit analyzed from the apparent layout pattern of the real chip to operate normally.

FIG. 5 shows another example of the dummy circuit of the NAND gate. In FIG. 5, N1, N2, and N3 are N-type transistors, and P1, P2, and P3 are P-type transistors, which are circuits that normally form a three-input NAND gate of inputs A, B, C, and output D. In the circuit shown in FIG. 5, the N-type transistor N1 is always on and the P-type transistor P1 is always off, so that the dummy circuit actually operates as a NAND gate for inputs B, C and output D regardless of the value of input A. Can be configured. In the circuit of FIG. 5, the N-type transistors N1 and N2 are always on,
If the P-type transistors P1 and P2 are always off, a dummy circuit that operates as an input C and output D inverter can be configured regardless of the values of the inputs A and B. In the above dummy circuit, if a dummy signal causing a malfunction is connected to the input A or the inputs A and B, it becomes difficult for the circuit analyzed from the real chip to operate normally. Similarly, a dummy circuit of a multi-input NAND gate can be formed.

FIG. 6 shows an example of a NOR gate dummy circuit. In FIG. 6, N1 and N2 are N-type transistors,
P1 and P2 are P-type transistors.
This circuit constitutes a NOR gate of B and output C. FIG.
In this circuit, the threshold voltage of the N-type transistor N1 is set higher than usual so that the normally-off type and the P-type transistor
By setting the threshold voltage of 1 higher than usual and making it always on, a value obtained by inverting input B is obtained from output C regardless of the value of input A. Therefore, the circuit shown in FIG. 6 serves as a NOR gate for the inputs A and B and the output C in the apparent layout pattern of the real chip, but can actually constitute a dummy circuit which operates as an inverter for the input B and the output C. If a dummy signal that causes a malfunction is connected to the input A of the dummy circuit, it becomes difficult for the circuit analyzed from the actual chip to operate normally.

FIG. 7 shows another example of a NOR gate dummy circuit.
Shown in In FIG. 7, N1, N2 and N3 are N-type transistors, P1, P2 and P3 are P-type transistors,
Usually, it is a circuit constituting a three-input NOR gate of inputs A, B, C and output D. In the circuit of FIG. 7, the N-type transistor N1 is always off and the P-type transistor P1 is always on, so that the dummy circuit actually operates as a NOR gate for the inputs B and C and the output D regardless of the value of the input A. Can be configured. If the N-type transistors N1 and N2 are always off and the P-type transistors P1 and P2 are always on in the circuit of FIG.
, A dummy circuit that operates as an input C and output D inverter can be configured. In the above dummy circuit, if a dummy signal causing a malfunction is connected to the input A or the inputs A and B, it becomes difficult for the circuit analyzed from the real chip to operate normally. Further, similarly, a dummy circuit of a multi-input NOR gate can be formed.

FIG. 8 shows an example of a dummy circuit of the inverter. In FIG. 8, N1 is an N-type transistor, P1 is P-type transistor.
This is a type transistor, and is a circuit that normally forms an input A and output B inverter. In the circuit of FIG. 8, the N-type transistor N1 is always on and the P-type transistor P1 is always off, so that the output B is always low regardless of the value of the input A. Therefore, the circuit shown in FIG. 8 can be used as an inverter for input A and output B in an apparent layout pattern of a real chip, but can actually constitute a dummy circuit in which output B is always low. Also, if the N-type transistor N1 is always off and the P-type transistor P1 is always on in the circuit of FIG. 8, a dummy circuit in which the output B is always high regardless of the value of the input A can be configured. If a dummy signal causing a malfunction is connected to the input A in the above dummy circuit, it becomes difficult for the circuit analyzed from the real chip to operate normally.

The above-described dummy circuit is constituted by using a dummy circuit basic cell. For example, a dummy circuit is mixed in a combinational circuit, or an output of the dummy circuit is input to a clock terminal, a set, and a reset terminal of a flip-flop. As a result, the circuit analyzed from the layout pattern of the actual chip has a different logical operation from the original circuit and does not operate normally. Therefore, it is possible to prevent the circuit mounted on the gate array from being illegally copied. In addition, by mounting multiple types of dummy circuit basic cells with different arrangement patterns of always-on and always-off transistors in the gate array and configuring the circuit by mixing multiple types of dummy circuits, illegal circuit copy Can be made more difficult.

Further, the present invention can be applied not only to a gate array but also to a standard cell or a full-custom LSI. By constructing the dummy circuit described above, and configuring the circuit by mixing the dummy circuits, illegal circuit copy can be prevented.

[0021]

According to the present invention as described above,
Semi-custom LS for semiconductor devices, especially gate arrays
In I, by incorporating always-on or always-off transistors and mixing dummy circuits having different logic operations from the apparent layout pattern of the actual chip, illegal circuit copying can be prevented, and its practical effects can be prevented. Is big.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a circuit of a dummy circuit basic cell according to an embodiment of the present invention.

FIG. 2 is a layout diagram showing an example of a layout pattern of a basic cell for a dummy circuit according to the embodiment of the present invention.

FIG. 3 is a layout diagram showing an example of a layout pattern of a basic cell for a dummy circuit according to the embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a dummy circuit according to the present invention.

FIG. 5 is a circuit diagram showing an example of a dummy circuit according to the present invention.

FIG. 6 is a circuit diagram showing an example of a dummy circuit according to the present invention.

FIG. 7 is a circuit diagram showing an example of a dummy circuit according to the present invention.

FIG. 8 is a circuit diagram showing an example of a dummy circuit according to the present invention.

FIG. 9 is a circuit diagram of a basic cell of a conventional gate array.

FIG. 10 is a layout diagram of a basic cell of a conventional gate array.

[Explanation of symbols]

 N1, N2... N-type transistor P1, P2... P-type transistor N +, N1 +, N2 +... N + diffusion region P +, P1 +, P2 +.

Claims (3)

[Claims] 1. A semiconductor device comprising a dummy circuit which incorporates always-on and always-off transistors in a logic circuit and has a different logic operation from an apparent layout pattern of a real chip. 2. The semiconductor device according to claim 1, further comprising a dummy circuit basic cell in which a normally-on and always-off transistor is incorporated in the basic cell of the gate array. 3. The semiconductor device according to claim 1, further comprising a plurality of types of dummy circuits each including a normally-on type transistor and a normally-off type transistor.