JPH0420117A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PURPOSE:To decrease the occupied area and to prevent malfunction by providing a control member having a function supplying a current in a forward direction when a prescribed voltage is applied between a terminal of an integrated circuit connecting at least one of both power supplies and the power supply to the semiconductor integrated circuit. CONSTITUTION:A member 8(9) having a function of supplying a current to an inverter circuit when a prescribed level difference is caused between a power terminal of a CMOS circuit and a power supply is provided between the power terminal of the CMOS circuit comprising 1st and 2nd MOS TRs 30, 31 and each power supply. As a concrete example of the members 8, 9, diodes are provided in opposite direction to the polarity of the power supply. The output timing of a feedback use inverter is retarded more than the output timing of a drive inverter in comparison with a latch circuit using an inverter circuit not employing the diodes and the contention time in a latch circuit is decreased. Thus, the operating margin in the latch circuit is improved, malfunction is avoided and the occupied area is reduced.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to the structure of a semiconductor integrated circuit, and in particular aims to improve the operating margin in a latch circuit, eliminate malfunctions, and reduce the area occupied by the latch circuit itself. A CMOS type semiconductor integrated circuit provided between a first power source and a second power source different from the first power source, wherein a terminal of the integrated circuit connected to at least one of the two power sources and a second power source different from the first power source. A control member is provided that has a function of allowing current to flow in the forward direction when a predetermined voltage is applied between the control member and the power source.

[Industrial application field]

The present invention relates to the structure of a semiconductor integrated circuit, and more particularly to the structure of a CMOS type semiconductor integrated circuit used in a latch circuit.

[Conventional technology]

Latch circuits are one of the most commonly used functional elements in semiconductor integrated circuits, along with NAND gate circuits and NOR gate circuits.

Now, the conventional technology for latch circuits is shown in Figures 6 to 1.
The structure and operation will be explained according to Figure 1.

That is, in the conventional latch circuit shown in FIG.
The transistors constituting the launch circuit are all composed of N-channel transistors of the same size and P-channel transistors of the same size, and both transistors are often composed of a gate array.

Here, saying that the N-channel transistors are all the same size means that the gate lengths and widths of all the transistors are all the same.

The advantage of such a latch circuit is that another transmission gate 11 is provided between the input side transmission gate 10 and the feedback inverter 4.
Although it has an excellent operating margin, it has the disadvantage that a total of eight transistors are used, which increases the area occupied by the entire latch circuit.

The configurations of the drive inverter circuit 3 and the feedback inverter circuit 4 used in the conventional latch circuit are shown in FIGS. 7 and 8, respectively.

On the other hand, FIG. 9 shows another example of a conventional latch circuit, and in the example of FIG. 9, the transmission gate 11 is omitted compared to the latch circuit of FIG.
Accordingly, the transistor of the feedback inverter 6 is formed to have a longer gate length and a shorter gate width than the transistor of the drive inverter 5.

That is, in the conventional example described above, the drive capability of the transistor of the feedback inverter is reduced so that a current does not flow more than that of the transistor of the drive inverter.

This latch circuit has the advantage that the area occupied by the latch circuit itself is reduced compared to the above-mentioned conventional example because the number of transistors used is six, but the transmission gate 10 on the input side Since there is no other transmission gate between the feedback inverter 6 and the feedback inverter 6,
If the gate length of each transistor is not made long, the operating margin will be reduced, and conversely, if the gate length is made long, the area occupied by the latch circuit will increase accordingly.

Also, to briefly explain the operation of a conventional latch circuit, data is held in a circuit as shown in FIG. 6 in a conventional latch circuit.

In this state, when inputting data manually, the transmission gate 10 is turned on and the transmission gate 11 is turned off to input data, and when data is to be held, the transmission gate 10 is turned off and the transmission gate 11 is turned on.

As a result, a loop as shown by arrow A is formed and data is retained.

The reason why the sound does not occur unless the transmission gate 11 is turned off during data input is that when both transmission gates are turned on, the drive inverter 3' and the feedback inverter 4 compete with each other.
There is a possibility that an intermediate potential will be output to the output section of the transmission gate 10.

Now, when the latch circuit is to output a signal H, the drive inverter 3 must recognize that the input is H.

However, if the intermediate potential is output due to the influence of the feedback inverter 4, the inverter 3 will output an L input signal.
There is a possibility that it will be recognized as such.

Therefore, an extra transmission gate 11 is provided,
You can turn this off when typing (.

In FIG. 9, instead of using the transmission gate 11, the drive capacity of the feedback inverter 6 is set to be smaller than the drive capacity of the drive inverter 5°, and the amount of current flowing is set to be small. The input of the inverter 5 never becomes an intermediate potential, and the correct level is always recognized.

Here, the layout of the inverter circuit used in the conventional latch circuit shown in FIG. 9 is shown in FIG. 12.

That is, the substrate 20 uses the P-type diffusion layer 22 as a source and
A first MOS transistor 30 having a P-type diffusion layer 23 as a drain and a gate 26 is provided, and an N-type diffusion layer 21 for substrate contact is further provided connected to the source region 22. Each layer has an electrode, for example ■. ,
A contact 24 is provided for making a connection with.

On the other hand, on the other substrate 20', a second MOS transistor 31 is provided, which has the N-type diffusion layer 27 as a source, the N-type diffusion layer 28 as a drain, and a common gate 26. 27, a P-type diffusion layer 29 for substrate contact is provided, and each layer has an electrode different from the above, for example (3). Contacts 25 for connection with are provided as appropriate.

As can be seen from the above layout, the area occupied by the transistor had to be large.

[Problem to be solved by the invention]

An object of the present invention is to provide a semiconductor integrated circuit capable of improving the above-mentioned drawbacks in the prior art, and providing a latch circuit that occupies a smaller area than a conventional latch circuit, while still providing an operational margin of the conventional latch circuit. The present invention aims to provide a semiconductor integrated circuit that can provide a launch circuit with a better operating margin.

[Problem to be solved by the invention]

In order to achieve the above object, the present invention employs the following technical configuration.

That is, a CMOS type semiconductor integrated circuit provided between a first power source and a second power source different from the first power source,
A semiconductor integrated circuit provided with a control member having a function of allowing current to flow in the forward direction when a predetermined voltage is applied between a terminal of the integrated circuit connected to at least one of the power supplies and the power supply. It is.

In the present invention, the control member may be provided between each terminal of the integrated circuit connected to both power supplies and the power supply.

[For production]

In the present invention, a control member is provided which has a function of allowing current to flow in the forward direction when a predetermined voltage is applied to both power supply terminals of a CMOS type O3 inverter circuit. For example, diodes are installed in the opposite direction, and when such a semiconductor integrated circuit is used, for example, as a feedback inverter, its function is the same as the conventional one, but the area occupied can be reduced and its manufacture is also easier. It becomes easier.

Furthermore, since there is a diode in the opposite direction on the electrode terminal side, when the output voltage of the inverter decreases due to leakage current, the diode becomes conductive in the reverse direction.
As a result, current flows to restore the output of the inverter and prevent malfunction.

Further, in the present invention, there is leeway in determining the size of each transistor; in other words, if the transistors are of the same size, the probability of malfunction can be reduced, and there is leeway in design.

Furthermore, in the present invention, since a member is provided that has a function of flowing current to the inverter circuit when a predetermined potential difference occurs in the current terminal of the feedback inverter, for example, when the latch circuit is turned on, a predetermined potential difference occurs. Since the feedback inverter is not turned on until the time is reached, it is possible to reduce the number of times when the drive inverter and the feedback inverter are in a conflicting state where they are turned on at the same time.

〔Example〕

Specific examples of the semiconductor integrated circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 shows an example in which an example of a semiconductor integrated circuit 1 according to the present invention is applied to a latch circuit.
A member 8.9 is provided which has the function of allowing current to flow through the inverter circuit only when a predetermined potential difference occurs between both power supply terminals of the S circuit and each power supply.

As a specific example of the member 8.9, FIG. 1 shows an example in which the diode is installed in the opposite direction to the power source.

Such a diode has a reverse breakdown voltage of 0.5~
It is preferable that it is adjusted to be 1.5■,
Therefore, in the specific example described above, current is caused to flow through the inverter circuit when the potential difference between the anode and cathode of the diode reaches the breakdown voltage.

Therefore, in the latch circuit using the semiconductor integrated circuit of the present invention, the timing of the output of the feedback inverter can be delayed from the timing of the output of the drive inverter, compared to the latch circuit using the inverter circuit without a diode. Therefore, the contention time in the latch circuit in the prior art described above can be reduced.

Although this specific example uses a diode as the member 8.9, it is also possible to use an appropriate resistor or FET transistor.

Although the semiconductor integrated circuit according to the present invention has been shown as being used in a latch circuit as an example, the semiconductor integrated circuit according to the present invention is not limited to such uses, and may require functions similar to those described above. Needless to say, the present invention can be applied to any circuit configuration.

Next, an example of a structure for carrying out the above specific example of the present invention will be explained in more detail with reference to FIG.

FIG. 4 shows the layout of a semiconductor integrated circuit according to the present invention.

In FIG. 4, the same members as those shown in FIG. 12 are designated by the same reference numerals.

As is clear from a comparison with FIG. 12, in the present invention, the first transistor 30 is constituted by the P-type diffusion layers 22 and 23 and the gate 26, and the first transistor 30 is composed of the P-type diffusion layer 22 on the source side. N-type diffusion layer 21 for connection and substrate contact
A first power source, for example ■D, is connected to this.

It is preferable that the N-type diffusion layer in such a structure be formed by ion implantation with a high impurity concentration.

In this case, the impurity concentration of the N-type diffusion layer 21 is determined by the second
The concentration conditions can be the same as those of the N-type diffusion 1i27.28 constituting the source and drain of the transistor, and in this case, the manufacturing method becomes easy.

With this configuration, a diode 8 in the opposite direction is formed at the PN junction between the P-type diffusion layer 22 and the N-type diffusion layer 21.

The reverse breakdown voltage of such a diode is 0.5~
It is preferable to set it to 1.5■.

On the other hand, the second transistor 31 is formed with the same structure as the first transistor using an impurity having electrical properties different from the impurity of the first transistor 30.

A reverse diode 9 is formed at the junction between the N-type diffusion layer 27 constituting the source of the second transistor 31 and the P-type diffusion layer 29 for substrate contact.

The formation method and characteristics of the diode in the second transistor are the same as those of the first transistor 30 except for the electrical properties of the impurity.

Note that 25 in the figure is a contact for connection to a second power source, for example, VSS.

As described above, in the semiconductor integrated circuit 1 according to the present invention,
Although the diodes are provided in the opposite direction, the reverse breakdown voltage of the diodes is set to 0.5 to 1.5 mm, so that the inverter functions as a feedback inverter to statically hold the voltage.

Further, since the diode controls the current drive capability of the feedback inverter, the above-mentioned competition does not occur.

Therefore, there is a margin within which malfunctions do not occur, and when designing circuits of the same size, the operating margin is excellent.

This allows considerable leeway in designing the semiconductor integrated circuit.

Furthermore, when updating data when the semiconductor integrated circuit according to the present invention is used in a latch circuit, the current flowing to the feedback inverter is limited by the diode, so that the inversion of data in the latch circuit is different from that in the conventional latch circuit shown in FIG. This is done faster than a latch circuit.

Furthermore, when comparing the layout of the semiconductor integrated circuit l according to the present invention with the conventional latch circuit shown in FIG. Since there is no need for a contact to connect to a power source or ground, the area occupied can be reduced.

Next, FIG. 5A shows an example of a structure for specifically manufacturing the present invention.
-C will be explained.

That is, in FIG. 5A, an n-type diffusion layer 5 is first formed on a P-type substrate 50.
1 is formed, and a P'' type diffusion layer 23 for drain and a P'' type diffusion layer 22 for source are formed in the n'' type diffusion layer 51 so as to be separated from each other, and a gate 26 is placed between them. A transistor 30 is formed.

Next, an n'-type scattering layer 21 is formed between the insulating layer 52 and the P'-type scattering layer 22, and is connected to the first power source (DD) via a contact 24.

The impurity concentration of the n-type scattering layer 21 can be the same as the impurity concentration of the n+-type scattering layer 2728 of the second transistor 31, which will be described later.

On the other hand, in a region separated by the insulating layers 53 and 54 of the P-type substrate 50, an n-type scattering layer 28 for the drain and an n
The second transistor 31 is formed by providing the 2-type scattering layers 27 separated from each other and placing the gate 26 therebetween.

Further, a P9 type diffusion layer 29 is provided between the n' type scattering layer 27 and the insulating layer 54 for the source, and is connected to the second power source VSS via a contact 25.

The impurity concentration of the P'' type scattering layer 229 can be the same as that of the P'' type scattering layer 2223 in the first transistor 30 described above.

Further, the gate 26 is connected by a common wiring 55 to form an input part IN, and the P' type diffusion layer 23 for the drain of the first transistor 3o and the N' type diffusion layer 28 for the drain of the second transistor 31 are connected to the common wiring. 56 to form the output OUT.

Further, in the present invention, it is not necessary to separately form a diode, and it can be formed using the above-mentioned PN junction, so that the manufacturing method is also simplified.

In FIG. 5A above, when a predetermined voltage is applied between each terminal of the CMOS semiconductor integrated circuit connected to both power supplies of the integrated circuit and the power supply, the current flows in the forward direction. The control member, for example, a diode, is provided, but the present invention is not limited to this embodiment, and as shown in FIG. 5B or FIG. 5C. The above control member, for example a diode, may be provided only between VCC and the inverter transistor or only between VSS and the inverter transistor.

In such an embodiment, it is preferable that the control member is provided and the inner power supply section is provided with wirings 57 and 58 for making board contact.

Another application example of the semiconductor integrated circuit according to the present invention is shown in FIG.

FIG. 13 shows that the latch circuit shown in FIG. 2 can be used not only as a single unit but also as a master-slave type and as a sister circuit.

That is, the semiconductor integrated circuit according to the present invention can be used as a constituent functional element of a flippy flop or a register in a memory.

〔effect〕

If the semiconductor integrated circuit according to the present invention is used as a feedback inverter for a latch circuit, its function is the same as that of the conventional one, but the occupied area is It can be made smaller and also easier to manufacture.

Furthermore, since there is a diode in the opposite direction on the electrode terminal side, when the inverter's output decreases, the diode becomes conductive in the opposite direction, causing current to flow and restore the inverter's output to its original state. Malfunctions can be prevented.

Furthermore, according to the present invention, the probability of malfunctions occurring with the same transistor size can be reduced, giving more margin in design.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a semiconductor integrated circuit according to the present invention. FIG. 2 is a diagram showing an example in which the semiconductor integrated circuit according to the present invention is applied to a feedback inverter of a latch circuit. FIG. 3 is a circuit diagram showing the configuration of a drive inverter used in the latch circuit in FIG. 2. FIG. 4 is a diagram showing the layout of the latch circuit shown in FIG. 2. 5A to 5C are diagrams showing examples of cross-sectional structures in a specific example of the semiconductor integrated circuit according to the present invention shown in FIG. 1. FIG. 6 is a diagram showing an example of the configuration of a conventional latch circuit. FIG. 7 is a diagram showing the circuit configuration of a drive inverter used in a conventional latch circuit. FIG. 8 is a diagram showing the circuit configuration of a feedback inverter used in a conventional latch circuit. FIG. 9 is a diagram showing another example of the configuration of a conventional latch circuit. FIG. 10 is a diagram showing a circuit configuration of a drive inverter used in the latch circuit shown in FIG. 9. FIG. 11 is a diagram showing a circuit configuration of a feedback inverter used in the latch circuit shown in FIG. 9. FIG. 12 is a diagram showing the layout of the conventional latch circuit shown in FIG. 9. FIG. 13 is a diagram showing an example in which the semiconductor integrated circuit according to the present invention is applied to a register. Figure ○UT N Figure 5C shows another example of a conventional latch circuit Figure 9 Figure 10 Figure 11

Claims (1)

[Claims] 1. A CMOS semiconductor integrated circuit provided between a first power source and a second power source different from the first power source, and connected to at least one of the two power sources. 1. A semiconductor integrated circuit comprising a control member having a function of causing current to flow in the forward direction when a predetermined voltage is applied between a terminal of the integrated circuit and the power supply. 2. A CMOS semiconductor integrated circuit provided between a first power source and a second power source different from the first power source, wherein each terminal of the integrated circuit connected to both power sources and the power source are connected to each other. 1. A semiconductor integrated circuit comprising a control member having a function of causing current to flow in a forward direction when a predetermined voltage is applied between the two. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the control member is a diode having a predetermined reverse breakdown voltage and provided in a direction opposite to the power supply. 4. Constructed by forming two diffusion layers containing a first impurity having a first electrical property on a substrate containing a second impurity different from the first impurity having the first electrical property. A CMOS type semiconductor integrated circuit comprising a first MOS transistor formed on a substrate containing a first impurity and a second MOS transistor formed on a substrate containing a first impurity and two diffusion layers containing a second impurity. , each MOS
A diffusion layer containing an impurity having electrical properties different from that of the impurity contained in the diffusion layer is formed at an end of the diffusion layer on the side connected to one of the first and second power supplies in the transistor. , A semiconductor integrated circuit characterized in that each of the diffusion layers is connected to one of the power sources.