JP3060311B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a structure of a semiconductor integrated circuit, and more particularly, to improve an operation margin in a latch circuit, eliminate malfunctions, and reduce an area occupied by the latch circuit itself. In a semiconductor integrated circuit including a CMOS type drive inverter and a CMOS type feedback inverter that feeds back an output of the CMOS type drive inverter to an input side, the CMOS type feedback inverter includes a first power supply and a first power supply. And a power supply terminal of the CMOS type feedback inverter connected to at least one of the first current and the second current. The power supply terminal of the CMOS type feedback inverter supplies a current when a predetermined voltage is applied. It is configured to be connected to the power supply via a flowable control member.

[Industrial applications]

The present invention relates to the structure of a semiconductor integrated circuit,
In particular, the present invention relates to a structure of a CMOS type semiconductor integrated circuit used in a latch circuit.

[Conventional technology]

A latch circuit is one of the most frequently used functional elements in a semiconductor integrated circuit together with a NAND gate circuit or a NOR gate circuit.

Here, the conventional technology for the latch circuit is shown in FIGS.
The structure and operation will be described with reference to FIG.

That is, in the conventional latch circuit shown in FIG. 6, the transistors constituting the latch circuit are all composed of N-channel transistors of the same size and P-channel transistors of all the same size. In many cases, a transistor is configured by a gate array.

Here, that all the N-channel transistors have the same size means that the gate lengths and the widths of all the transistors are all the same.

The advantage of such a latch circuit is that since another transmission gate 11 is provided between the transmission gate 10 on the input side and the inverter 4 for feedback, the operation margin is excellent, but on the other hand, the total number of transistors is eight. Also, there is a disadvantage that the occupied area of the entire latch circuit becomes large.

The configurations of the drive inverter 3 and the feedback inverter 4 used in the conventional latch circuit are shown in FIGS. 7 and 8, respectively.

On the other hand, FIG. 9 shows another example of a conventional latch street. In the example of FIG. 9, the transmission gate 11 is omitted as compared with the latch circuit of FIG.
The transistor of the feedback inverter 6 has a longer gate length and a shorter gate width than the transistor of the drive inverter 5 accordingly.

That is, in the above-mentioned conventional example, the driving capability of the transistor of the feedback inverter is reduced so that the current does not flow more than the transistor of the driving inverter.

This latch circuit has the advantage that the occupied area of the latch circuit itself is reduced as compared with the above-mentioned conventional example because the number of transistors used is six. Since there is no other transmission gate between the feedback inverter 6 and the feedback inverter 6,
Unless the gate length of each transistor is increased, the operation margin decreases, and conversely, if the gate length is increased, the occupied area of the latch circuit increases accordingly.

The operation of the conventional latch circuit will be briefly described. In the conventional latch circuit, data is held by a circuit as shown in FIG.

In this state, when data is input, the transmission gate 10 is turned on and the transmission gate is turned on.
When the data is input with 11 turned off, the transmission gate 10 is turned off and the transmission gate 11 is turned on to hold the data.

As a result, a loop as shown by arrow A is formed and data is held.

The reason why the transmission gate 11 must be turned off when data is input is that when both transmission gates are turned on, the drive inverter
There is a possibility that the 3 'and the feedback inverter 4 compete with each other to output an intermediate potential to the output of the transmission gate 10.

Now, when trying to output the signal H in the latch circuit, the drive inverter 3 must recognize that the input is L.

However, the input signal of the inverter 3 to which the intermediate potential is output due to the influence of the feedback inverter 4 is H.
It may be recognized that it is.

Therefore, an extra transmission gate 11 is provided,
Turn this off when typing.

In FIG. 9, the drive capacity of the feedback inverter 6 is set to be smaller than the drive capacity of the drive inverter 5 'instead of not using the transmission gate 11, and the amount of current flow is set smaller. The input of the inverter 5 does not become an intermediate potential, and the correct level is always recognized.

Here, the layout of the inverter circuit used in the conventional latch circuit shown in FIG. 9 is as shown in FIG.

That is, the substrate 20 has a P-type diffusion layer 22 as a source, a P-type diffusion layer 23 as a drain, and a first
MOS transistor 30 is provided, and the source region 22
An N-type diffusion layer 21 for substrate contact is provided in connection with the substrate. Each layer is provided with a contact 24 for connection to an electrode, for example, _VDD .

On the other hand, another substrate 20 'is provided with a second MOS transistor 31 having an N-type diffusion layer 27 as a source and an N-type diffusion layer 28 as a drain, and a common gate 26 provided thereon. 27 is connected is provided with a P-type diffusion layer 29 of the substrate contact and the and the layers contact 25 for connection between the different electrodes eg V _SS is provided as appropriate.

As can be seen from the above layout, the occupied area of the transistor had to be large.

[Problems to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of providing a latch circuit having an occupied area smaller than the occupied area of the conventional latch circuit by improving the above-mentioned drawbacks in the prior art. It is an object of the present invention to provide a semiconductor integrated circuit capable of providing a latch circuit having an excellent operation margin.

[Means for solving the problem]

The present invention employs the following technical configuration to achieve the above object.

That is, in the present invention, a CMOS type drive inverter,
In a semiconductor integrated circuit having a CMOS type feedback inverter that feeds back an output of the CMOS type drive inverter to an input side, the CMOS type feedback inverter includes a first power supply and a second current. A power supply terminal of the CMOS type feedback inverter which is provided and is connected to at least one of the first power supply and the second power supply has a control member capable of flowing a current when a predetermined voltage is applied. A semiconductor integrated circuit connected to the power supply via the power supply is provided.

Preferably, in the present invention, the control member is a diode connected in reverse to the power supply.

[Action]

In the present invention, when a predetermined voltage is applied to both power supply terminal portions of the CMOS inverter circuit, a control member having a function of flowing a forward flow in a forward direction is provided. Diodes are provided in the opposite direction, and when such a semiconductor integrated circuit is used, for example, as a feedback inverter, its function is the same as that of the conventional one, but its occupation area can be reduced and its manufacture is easy. Become.

Furthermore, since a diode in the opposite direction is present on the electrode terminal side, when the output electrons of the inverter decrease due to the pre-leak current, the diode conducts in the reverse direction, whereby current flows and the output of the inverter is reduced. It can recover and prevent malfunction.

In addition, in the present invention, there is a margin in how to determine the size of each transistor, in other words, if the size of the same transistor, it is possible to reduce the probability of malfunction,
There is room for design.

Furthermore, in the present invention, since a member having a function of flowing a current to the inverter circuit when a predetermined potential difference occurs in the current terminal of the feedback inverter is provided, for example, when the latch circuit is turned on, the predetermined potential difference is provided. Since the feedback inverter is not turned on until the drive inverter and the feedback inverter are turned on at the same time, it is possible to reduce the number of times that the drive inverter and the feedback inverter are simultaneously turned on.

〔Example〕

Hereinafter, specific examples of the semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

FIG. 1 shows an example in which a specific example of a semiconductor integrated circuit 1 according to the present invention is applied to a latch circuit.
A member 8 having a function of allowing a current to flow through the inverter circuit only when a predetermined potential difference is generated between both power supply terminals of the CMOS circuit composed of the MOS transistors 30 and 31 and each power supply; 9 is provided.

FIG. 1 shows a specific example of the members 8 and 9 in which a diode is mounted in a direction opposite to a power supply.

Such a diode has a reverse breakdown voltage of 0.5 to
It is preferable that the voltage is adjusted to 1.5 V. Therefore, in the above specific example, a current flows through the inverter circuit when the potential difference between the anode and the cathode of the diode reaches the above-described breakdown voltage. It is.

Therefore, in the latch circuit using the semiconductor integrated circuit of the present invention as shown in FIG. 2 and FIG. 3, the output timing of the feedback inverter 4 is reduced in comparison with the latch circuit using the inverter circuit having no diode. This makes it possible to delay the output timing of the drive inverter 3, thereby reducing the contention time in the above-described conventional latch circuit.

In this specific example, an example is shown in which diodes are used as the members 8 and 9, but it is also possible to use appropriate resistors or FET transistors.

Although the semiconductor integrated circuit according to the present invention has been described by way of example as being used in a latch circuit, the semiconductor integrated circuit according to the present invention is not limited to such applications, and requires the same functions as described above. Needless to say, the present invention can be applied to any circuit configuration.

Next, an example of a structure for implementing the above-described embodiment of the present invention will be described in more detail with reference to FIG.

FIG. 4 shows a layout of a semiconductor integrated circuit according to the present invention.

4, the same members as those shown in FIG. 12 are denoted by the same reference numerals.

As is apparent from comparison with FIG. 12, in the present invention, the first transistor 30 comprises the P-type diffusion layers 22 and 23 and the gate 26.
And an N-type diffusion layer 21 for substrate contact connected to the P-type diffusion layer 22 on the source side, to which a first power supply, for example, _VDD is connected.

The N-type diffusion layer having such a structure is preferably formed by ion implantation so as to increase the impurity concentration.

In this case, the impurity concentration of the N-type diffusion layer 21 is set to a second
Of the N-type diffusion layers 27 and 28 constituting the source and drain of the transistor described above, and in this case, the manufacturing method becomes easy.

With such a configuration, the diode 8 in the opposite direction is formed at the PN junction between the P-type diffusion layer 22 and the N-type diffusion layer 21.

The reverse breakdown voltage of such a diode is 0.5 to
It is preferably set to 1.5V.

On the other hand, the second transistor 31 is formed with the same structure as the first transistor by using an impurity having an electric property different from that of the first transistor 30.

The diode 9 in the opposite direction is formed at the junction between the N-type diffusion layer 27 constituting the source of the second transistor 31 and the P-type diffusion layer 29 for substrate contact.

The method of forming the diode or the characteristics of the second transistor is the same as that of the first transistor 30 except that the electrical characteristics of the impurities are different.

In the drawing, 25 is a contact for connecting a second current example V _SS.

As described above, in the semiconductor integrated circuit 1 according to the present invention, the diode is provided in the reverse direction. However, since the reverse breakdown voltage of the diode is set to 0.5 to 1.5 V, the diode is statically used as a feedback inverter. Exhibits the function of maintaining voltage.

Further, since the diode controls the current driving capability of the feedback inverter, the above-mentioned competition does not occur.

Therefore, there is a margin in a range where no malfunction occurs, and when designing circuits of the same size, the operation margin becomes excellent.

This allows a considerable margin in designing a semiconductor integrated circuit.

When data is updated when the semiconductor integrated circuit according to the present invention is used for a latch circuit, the current flowing through the feedback inverter is limited by the diode,
Inversion of data in the latch circuit is performed at a higher speed than in the conventional latch circuit shown in FIG.

Further, when the layout of the semiconductor integrated circuit 1 according to the present invention is compared with the conventional latch circuit shown in FIG. 12, in the present invention, the source side of each of the first and second transistors 30 and 31 is different. In addition, since a contact for connecting to a current or a ground is not required, the occupied area can be reduced.

Next, an example of the structure when the present invention is specifically manufactured will be described with reference to FIGS. 5A to 5C.

That is, in FIG. 5A, first, an n ⁻ -type diffusion layer 51 is formed on the P ⁻ -type substrate 50, and the drain P ⁺ -type diffusion layer 23 and the source P ⁺ -type diffusion layer 22 are formed on the n ⁻ -type diffusion layer 51. Are formed apart from each other, and the gate 26 is placed therebetween to form the first transistor 30.

Next, an n ⁺ -type diffusion layer is provided between the insulating layer 52 and the P ⁺ -type diffusion layer 22.
21 is formed and connected to a first power supply V _DD via a contact 24.

The impurity concentration of the n ⁺ -type diffusion layer 21 can be the same as the impurity concentration of the n ⁺ -type diffusion layers 27 and 28 of the second transistor 31 described later.

On the other hand, the n ⁺ -type diffusion layer 28 for the drain and the n ⁺ -type diffusion layer 27 for the source are formed in a region of the P ⁻ -type substrate 50 separated by the insulating layers 53 and 54.
Are provided apart from each other, and the gate 26 is placed between them to form the second transistor 31.

Further, P ⁺ is provided between the source n ⁺ -type diffusion layer 27 and the insulating layer 54.
-Type diffusion layer 29 is provided, to which is connected to the V _SS is a second power source via a contact 25.

The impurity concentration of the P ⁺ -type diffusion layer 29 can be the same as that of the P ⁺ -type diffusion layers 22 and 23 in the first transistor 30 described above.

The gate 26 is connected to the common wiring 55 to form the input portion IN. The drain P ⁺ -type diffusion layer 23 of the first transistor 30 and the drain n ⁺ -type diffusion layer 28 of the second transistor 31 are connected to a common wiring. Connected at 56 to form output OUT.

Further, in the present invention, it is not necessary to separately form a diode, and the diode can be formed using the above-mentioned PN junction, so that the manufacturing method is simplified.

In FIG. 5A, when a predetermined voltage is applied between each terminal of the integrated circuit connected to both power supplies of the CMOS type semiconductor integrated circuit and the power supply, a current flows in a forward direction. The control member having a flowable function, for example, a diode is provided, but the present invention is not limited to such an embodiment, and the control member described above as shown in FIG. 5B or 5C. For example, a diode may be provided only between V _CC and the inverter transistor or only between V _SS and the inverter transistor.

In such an embodiment, it is preferable that the control member is provided and the inner power supply unit is provided with wirings 57 and 58 for searching for a substrate contact.

FIG. 13 shows another application example of the semiconductor integrated circuit according to the present invention.

FIG. 13 shows that the latch circuit shown in FIG. 2 can be used not only as a single unit but also as a master-slave type register.

That is, the semiconductor integrated circuit according to the present invention can be used as a constituent element of a register in a flip-flop or a memory.

〔effect〕

When the semiconductor integrated circuit according to the present invention is used as a feedback inverter of a latch circuit, its function is the same as that of a conventional inverter when it is used as a feedback inverter, but the occupied area is small. It can be made smaller and its manufacture is easier.

Furthermore, since a diode in the opposite direction is present on the electrode terminal side, when the output of the inverter decreases, the diode conducts in the reverse direction, whereby current flows and the output of the inverter is restored to the original state. Malfunction can be prevented.

Further, in the present invention, the probability of causing a malfunction with the same transistor size can be reduced, so that there is more design margin.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to the present invention. FIG. 2 is a diagram showing an example in which the semiconductor integrated circuit according to the present invention is applied to a feedback inverter of a latch circuit. FIG. 3 is a circuit diagram showing a configuration of a drive inverter used in the latch circuit in FIG. FIG. 4 is a diagram showing a layout of the latch circuit shown in FIG. 5A to 5C are diagrams showing examples of a cross-sectional structure in a specific example of the semiconductor integrated circuit according to the present invention shown in FIG. FIG. 6 is a diagram showing a configuration example of a conventional latch circuit. FIG. 7 is a diagram showing a circuit configuration of a drive inverter used in a conventional latch circuit. FIG. 8 is a diagram showing a circuit configuration of a feedback inverter used in a conventional latch circuit. FIG. 9 is a diagram showing another configuration example of the conventional latch circuit. FIG. 10 is a diagram showing a circuit configuration of a drive inverter used in the latch circuit shown in FIG. FIG. 11 is a diagram showing a circuit configuration of a feedback inverter used in the latch circuit shown in FIG. FIG. 12 is a diagram showing a layout of the conventional latch circuit shown in FIG. FIG. 13 is a diagram showing an example in which the semiconductor integrated circuit according to the present invention is applied to a master-slave register.

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit comprising: a CMOS type drive inverter; and a CMOS type feedback inverter that feeds back an output of the CMOS type drive inverter to an input side. A predetermined voltage is applied to a power supply terminal of the CMOS feedback inverter, which is provided between the power supply and the second power supply and is connected to at least one of the first power supply and the second power supply. A semiconductor integrated circuit connected to the power supply via a control member capable of flowing a current when the semiconductor integrated circuit is operated. 2. The control member according to claim 1, wherein the control member is a diode connected in reverse to the power supply.
A semiconductor integrated circuit as described in the above.