JPH01114117A - Cmos output buffer circuit - Google Patents

Abstract

PURPOSE:To apply a voltage larger than the power voltage to an output point by adding a diode in series with an output P-channel transistor(TR) and using a connection point between the diode and an N-channel TR as an output terminal. CONSTITUTION:The impurity density of a P-channel diffusion region (layer) 4 and an N-channel diffusion region (layer) 5 is selected so that the reverse dielectric strength of a diode D3 is larger than the power voltage VCC. In applying a voltage VA larger than the voltage VCC to a terminal 3 for input/output in common, the diode D3 is reversed to cut off a parasitic current and to attain normal operation in case of VA<VS (VS is the reverse dielectric strength of the diode D3). That is, the diode D3 is added in series with an output P-channel TR Q2 and the connection point between the diode D3 and the N-channel TR Q1 is used as an output terminal 3. Thus, it is possible to apply a voltage over the voltage VCC to the output point regardless of the CMOS element employed and the use of the terminal 3 for common input/output is made flexible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, particularly a CMO3 output buffer circuit provided at an input/output terminal of a CMO3 semiconductor device.

[Conventional technology]

In CMO3 semiconductor devices, the circuit formats for outputting internal signals to the outside include N-channel oven drain format, P-channel oven drain format,
There are three types of CMO5 output formats, each of which is tailored to meet your needs.

FIG. 2(a) shows a conventional CMOS output buffer circuit.

(b), in which Ql is an N-channel transistor, Q2 is a P-channel transistor, DI, D
2 are parasitic diodes formed at the drains of transistors Ql and Q2, respectively; 1°2 is a signal input to the gates of transistors Ql and Q2, respectively; 3 is the main CM
This is the output terminal of the OS output buffer circuit, and also serves as an input terminal for inputting external signals to other circuits in the CMO3 semiconductor device in which this CMOS output buffer circuit is provided. Hereinafter, this node 3 will also be referred to as an input/output terminal or an output point.

Note that although the figure shows an example using an N-substrate P-well system, the opposite case, that is, a P-substrate N-well system, is of course possible.

In such a structure, a parasitic diode, shown as Di, D2, is necessarily formed in the drain region. A diode is formed in this direction. In addition, in the P channel transistor Q2, the P channel forming the drain is
A diode is formed between the diffusion layer and the N-well. Therefore, for example, when the potential at the output point 3 is higher than Vcc, the diode D2 turns on in the forward direction, causing a large parasitic current to flow. When using this terminal only at CMOS level, the potential of node 3 is Vss x Vcc
There is no particular problem as it is only within the range of Vc.
If a voltage higher than c is applied, this structure has the problems described above.

[Problem that the invention seeks to solve]

Since the conventional CMOS output buffer circuit is configured as described above, there is a problem in that only a potential between Vss and VcCO is allowed as the potential of the input/output terminal, which limits how it can be used.

This invention was made to solve the problems of the conventional CMO3 output buffer circuit as described above.
It is an object of the present invention to provide a CMO3 output buffer circuit that can apply a voltage higher than VcC to its output point, although it is a circuit type.

[Means for solving problems]

The CMOS output buffer circuit according to the present invention has an output P
A diode is inserted between the drains of the channel and N-channel transistors in a forward direction when viewed from the power source, and the output point is taken out from the connection point between the diode and the output N-channel transistor.

[Effect]

In this invention, by adding a diode as described above, even if a voltage higher than the power supply voltage is applied to the output point, this diode reverses direction and the parasitic diode of the output P-channel transistor is turned on. In order to prevent this, the parasitic current is cut off when a voltage higher than the power supply voltage is applied to the output point, allowing normal operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a CMOS output buffer circuit according to an embodiment of the present invention, in which 4 is a P-channel transistor Q
2 is a P-type diffusion region corresponding to the drain, 5 is an N-type diffusion region formed in an island shape within the P-type diffusion region 4, and D3 is constituted by the P-type diffusion region 4 and the N-type diffusion region 5. It is a diode. Ql, Q2. DI, D2, and signal 1°2.3 are the same as in the conventional device.

The impurity concentrations of the P-type diffusion regions 4 and 2 and the N-type diffusion region 5 are selected so that the reverse breakdown voltage of the diode D3 is greater than the power supply voltage vcc. For the following explanation, the reverse breakdown voltage of this diode D3 is assumed to be V.

Next, the operation will be explained. Now, apply V to input/output terminal 3.
Assume that a voltage vA higher than CC is applied.

In the case of the conventional device, the parasitic diode D2 turns on in the forward direction, causing a large parasitic current to flow and does not operate normally, but in the case of the present invention, if VA<Vl, the diode D3 turns in the reverse direction. Parasitic current is canted off and normal operation is possible.

In the above description, the case where the circuit is used as a CMO3 output format is considered, but in this embodiment, it is also possible to use the same circuit as an N-channel open drain format. In conventional devices, the CMOS type and the N-channel oven drain type have to be made separately on the mask, and can only be used in a predetermined usage method depending on the mask.

However, according to the present invention, if the P-channel transistor Q2 is always turned off by setting the input signal 2 to the vec level, V
It becomes possible to apply a voltage higher than CC, and by doing this, N
It can perform the same operation as the channel open drain type, greatly increasing the degree of freedom in how it can be used.

Furthermore, when considering the wafer process for manufacturing the device shown in FIG.
14 or the N type diffusion layer 5 can be used in common with the P" source drain process or the N1 source drain process in the conventional process, and there is substantially no increase in the number of rewafer processes.

〔Effect of the invention〕

As described above, according to the CMOS output buffer circuit according to the present invention, a diode is added in series with the output P-channel transistor, and the connection point between the diode and the N-channel transistor is used as the output terminal. It becomes possible to apply a voltage of Vo or more to the output point,
This has the effect that the input/output terminals can be used flexibly.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a CMOS output buffer circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional CMOS output buffer circuit. In the figure, Ql is an N-channel transistor, Q2 is a P-channel transistor, Di, D2 and D3 are diodes, 1.2 is the gate input of transistors Ql and Q2, respectively, 3 is an input/output terminal, 4 is a P-type diffusion layer, 5 is N
It is a type diffusion layer.

Claims (3)

[Claims] (1) An N-channel transistor whose source is connected to a ground potential, a P-channel transistor whose source is connected to a power supply voltage, and a diode whose drain is an anode and whose cathode is connected to the drain of the N-channel transistor. 1. A CMOS output buffer circuit comprising: a CMOS output buffer circuit, wherein the output terminal is taken out from a connection point between the cathode of the diode and the drain of the N-channel transistor. (2) The diode is formed of two diffusion layers: a P-type diffusion layer corresponding to the drain of the P-channel transistor and an N-type diffusion layer formed in an island shape within the P-type diffusion layer. A CMOS output buffer circuit according to claim 1, characterized in that: (3) The CMOS output buffer circuit according to claim 1, wherein the output terminal also serves as an input terminal for inputting an external signal to a circuit other than the main circuit.