JP2623641B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a semiconductor memory device, in particular, in a semiconductor memory device in which a memory cell includes a pair of CMOS inverters, a latch-up phenomenon is suppressed and reliability and integration are improved. A memory cell includes a pair of complementary MOS inverters, and a source region of a p-channel transistor fixed to a power supply potential of the inverter and an n-channel transistor fixed to a ground potential. The distance between the source region and the drain region of the p-channel transistor serving as the output portion of the inverter is greater than the distance between the drain region of the n-channel transistor.

[Industrial applications]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a storage (memory) cell includes a pair of complementary MOS (CMOS) inverters.

In the field of static random access memory (SRAM), the use of a memory cell of a high resistance load type is leading in the degree of integration because it is advantageous for miniaturization of the cell.

However, in the case of the high-resistance load type, a direct current is applied to the high-resistance load to retain the memory, so that with the high integration, the SRAM is required.
However, there is a problem that the memory holding current increases and the power consumption becomes enormous.

On the other hand, a memory cell configured using a CMOS inverter has a very small storage retention current due to only a leak current of a p-channel transistor serving as a load, and is extremely excellent in power consumption.

Therefore, when a high resistance load type SRAM reaches the limit in terms of power consumption, there is a possibility that an SRAM in which a memory cell is configured by a CMOS inverter becomes mainstream instead of a high resistance load type SRAM.

However, in the SRAM using this CMOS inverter,
Since both a p-channel transistor and an n-channel transistor are provided in a memory cell, there is a problem of performance degradation due to a latch-up phenomenon.

FIG. 2 is a side sectional view of a CMOS semiconductor device for explaining a latch-up phenomenon (a) and an equivalent circuit diagram of the same phenomenon (b). In the figure, p-MOS is a p-channel MOS transistor and n-MOS is an n-channel. MOS transistor, p-sub is p-type substrate, n-
well is an n-type well, C _s is a substrate contact, C _w is a well contact, _Sp and _Sn are p ⁺ and n ⁺ source regions, D _p and
D _n is a p ⁺ type and n ⁺ type drain region, G is a gate, OUT is a force, V _CC is a high potential power supply, V _SS is a ground potential power supply, pnpTr is a parasitic pnp transistor, npnTr is a parasitic npn transistor, R _s
The substrate resistance, R _w represents the well resistance.

As shown in the figure, the CMOS semiconductor device has a p-MOS p ⁺
Type source region S _p and n-well and p-sub and pnp-Tr and n-MOS of the n ⁺ -type source region S _n constituted by, p-sub,
The npnTr constituted by the n-well is parasitic.

For that reason a large noise current from the power source such as high voltage DenHara V _CC enters lowers the well potential by the voltage drop of the well resistor R _w, joining the p-MOS of the p ⁺ -type source region S _p becomes the forward direction, parasitic pnpTr is emitter current injected into the parasitic pnpTr from the source region S _p is turned oN. And the parasitic p
The collector current C ₁ flows from the npTr to the substrate resistance R _s in the substrate p-sub.
Flows toward the substrate contact C _s connected to V _SS via, thereby increasing the substrate potential. The S junction is forward of the order n-MOS of the n ⁺ -type source region S _n
A current is injected from _n into the emitter of the parasitic npnTr,
r is turned ON, the flow toward the well contact C _w collector current C ₂ of the parasitic npn-Tr via the well resistor R _w within n-well, lowering the well potential. Therefore, p ^{+ of} p-MOS
Type source region S when _p is emitter injection current to the parasitic pnpTr from the source region S _p becomes stronger forward parasitic pnpTr is turned ON. Such parasitic pnpTr and npwnTr
Alternately turn on to form a positive feedback circuit, and a so-called latch-up phenomenon in which current always flows from V _CC to V _SS occurs.
The heat generated by the positive feedback current leads to destruction of the CMOS semiconductor device.

This latch-up phenomenon is more likely to occur as the performance of the parasitic bipolar transistor becomes better. To suppress this, the distance between the p-channel region and the n-channel region corresponding to the base width of the parasitic bipolar transistor must be increased. It is effective to reduce the performance of the parasitic bipolar transistor, but this undesirably leads to a reduction in the integration degree of the SRAM cell.

Therefore, there is a demand for an SRAM cell structure that can prevent the latch-up phenomenon and can achieve higher integration.

[Conventional technology]

FIG. 3 is a diagram showing an equivalent circuit of an SRAM cell constituted by using a 7CMOS inverter, in which PT ₁ and PT ₂ are p-channels.
MOS transistors, NT ₁ and NT ₂ are n-channel MOS transistors, TT ₁ and TT ₂ are transfer transistors, V _CC is a high potential power supply wiring, V _SS is a ground power supply wiring, WL is a word line, BL ₁ ,
BL ₂ is a pair of bit lines, S _p1 , S _p2 and D _p1 , D _p2 is PT _p1 , PT
source and drain regions S _n2 having a P ⁺ -type _p2, S _n2 and
D _n1 and D _n2 are source and drain regions having the n ⁺ type of NT ₁ and NT ₂ , and G ₁ , G ₂ , G ₃ and G ₄ are gate electrodes.

The Fig. 4 shows a conventional pattern layout of the SRAM cell, in the figure, A ₁₁ and A ₁₂ shown hatched, for example active region where n-type well is exposed, as well A _21, And A
₂₂ is an active region exposed by the p-type semiconductor substrate, FOX is a field oxide film that defines and separates the active region, Al ₁ and Al ₂ indicated by dashed lines are aluminum patterns, H _{1 to} H ₈ are contact windows, SD _n1 and SD _n2 are n ⁺ type sources of TT ₁ and TT ₂ /
A drain region is shown, and other reference numerals indicate the same object as in FIG.

As shown in FIG. 4, in the conventional SRAM cell,
PT _1, PT active regions A ₁₁ and A ₁₂ or the like is formed ₂ has parallel straight to the high-potential power supply line V _CC, NT _1, the active region A ₂₁ NT ₂ or the like is formed and A ₂₂ It was formed in parallel at a required interval between the a ₁₁ and a _12.

In such a pattern structure, hindering the improvement of the integration degree, the distance d _A between the active region A ₁₁ and A ₁₂ and V _CC line indicated by.

The distance d _A is determined by the lithography when forming the connection pattern Al ₁ and the like because the output sides of the inverters PT ₁ and NT ₁ and the like are connected by the Al pattern Al _{1 and the} like in the same layer as the _VCC wiring. positioning dimensional margin of accuracy necessary for the active region a ₁₁ or the like and the contact window H _5, etc., contact windows
Size dimensions H _5, etc., contact window H _5, etc. and Al pattern Al ₁
Allowance for positioning with Al, etc., and Al pattern Al ₁ etc. and V _CC
Only the dimension obtained by adding the minimum necessary distance between the wirings is required.

Therefore, in the conventional pattern structure, for example, there is no lithographic restriction shown in FIG.
₁ of the source region S _p1 is disposed V _CC potential is formed in the same size and pitch d _B also the d _A and immediately the applied portion of the active region A ₁₁ and V _CC line.

Here, the distance between the active regions A ₁₁ and A _{12 and the} like, that is, the n-channel region, and the active regions A ₂₁ and A _{22 and the} like, that is, the p-channel region are extremely important in latch-up.

FIG. 5 is a schematic plan view showing only the active region pattern of the conventional SRAM cell in order to easily understand the location where the latch-up occurs.

Portion in FIG hits the output side of the CMOS inverter, the drain region D _n1 of the drain region D _p1 and NT _1, for example PT ₁ is formed in the active region A ₁₁ and A ₂₁ are connected to the same potential latch There is no relation to the up (see FIG. 4).

Between the above-mentioned D _p1 and the n-type drain region D _n2 of the adjacent inverter (see FIG. 4), as shown in the equivalent circuit diagram of the latch-up state shown in FIG. 6, the parasitic pnp-Tr
And enters the load and the p-channel transistor PT ₁ and n-channel transistor NT ₂ is a positive feedback circuit constituted by a parasitic npn-Tr, the parasitic bipolar transistor (pn
In order to prevent a potential difference between the base and the emitter of p-Tr and npn-Tr), latch-up resistance is relatively high with the same parasitic resistance.

Portion indicated by for these are close distance between the source region S _n1 is the source region S _p1 and n-channel region is a p-channel region is compared with the part, and in each region
Since the V _CC potential and the V _SS potential are immediately applied (see FIG. 4), the MOS transistor is not inserted as a load into the positive feedback circuit as shown in FIG. This is a part where the up is likely to occur.

Therefore, in the conventional SRAM cell is extending linearly formed in parallel active regions to V _CC line as shown in FIG. 4, the required distance from the V _CC wiring constraints on lithography aforementioned d _A drain regions of the output side or the like p-channel transistor PT ₁ of the CMOS inverter formed apart and D _p1
Distance and the p-channel transistor PT ₁ such as the source region S _p1 or the like which are equal and V _CC potential is immediately applied is similar to the above d _A
Since the d _B are formed at the V _CC line, when aimed at reduced increased density pitch between V _CC line, the latch-up occurs the fifth view of the distance in close proximity It will be easier.

[Problems to be solved by the invention]

Or more in the conventional SRAM cell which has been extended linearly formed in parallel active regions to V _CC wiring as, when aimed at reduced increased density pitch between V _CC line, high voltage The distance between the source region of the p-channel transistor to which the voltage is applied and the source region of the n-channel transistor to which the setting potential is applied is also reduced at the same pitch, so that the latch-up phenomenon easily occurs and the reliability of the memory cell is reduced. However, there was a problem that was reduced.

Therefore, an object of the present invention is to provide a pattern arrangement structure in which a latch-up phenomenon is suppressed and reliability and integration can be improved.

[Means for solving the problem]

The above object is achieved by forming a pair of complementary memory cells on a semiconductor substrate.
The distance between the source region of the p-channel transistor fixed to the power supply potential of the inverter and the source region of the n-channel transistor fixed to the ground potential is an output part of the inverter. The problem is solved by a semiconductor memory device formed to be larger than the distance between the drain region of the p-channel transistor and the drain region of the n-channel transistor.

(Operation)

That is, the present invention is in the CMCS inverter disposed in the SRAM, the source region side of the active region of the p-channel transistors connected to V _CC wire is connected to other areas by the conductor layer of the V _CC line in the same layer Note that there is no lithographic restriction between the position of the V _CC wiring and the active region forming the p-channel transistor, and thus the source of the p-channel transistor is bent. The position of the region is selectively shifted to the lower region side of the V _CC wiring, and the source region of the p-channel transistor to which the V _CC potential is directly applied and the source region of the n-channel transistor to which the V _SS potential is immediately applied To suppress the occurrence of the latch-up phenomenon.

As a result, the reliability of the SRAM is improved and the SR is improved.
AM can be further integrated.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to an embodiment shown in FIG.

FIG. 1 is a schematic plan view showing an embodiment of a pattern arrangement of an SRAM cell according to the present invention. In the drawing, INV ₁ and INV ₂ are first and second inverters, and A ₁₁₁ and A ₁₁₂ are n-type. Active regions on the wells, A ₂₁ and A ₂₂ are active regions on the p-type semiconductor substrate, FOX is a field oxide film that selectively covers the substrate and the wells to define and separate the active regions, and PT ₁₁ and PT ₁₂ are p Channel transistors, NT ₁ and NT ₂ are n-channel transistors, TT ₁
And TT ₂ are transfer transistors, V _CC is a high-potential power supply wiring made of Al or the like, V _SS is a ground power supply wiring made of Al or the like, W
L is the gate electrode G ₃ in TT ₁ and TT ₂ made of poly-Si or the like, a word line also serving as a G ₄ and the like, S _{pi 1,} S _p12 and D _{pi 1,} D _p12 is a source region having a ⁺ -type PT ₁₁ and PT ₁₂ And drain region, S
_n1, S _n2 and D _n1, D _n2 is the source and drain regions having n ⁺ -type NT ₁ and NT _2, G ₁ and PT ₁₁ made of poly-Si or the like
Common gate electrode to NT _1, G ₂ consists of poly-Si or the like PT ₁₂ and N
Common gate electrode to T _2, H ₁ ~H ₈ the contact windows, Al ₁ is P
The first Al pattern that connects D _p11 and D _n1 , which are the output sides of T ₁₁ and NT ₁ , in common, Al ₂ is D _p12 which is the output side of PT ₁₂ and NT ₂
7 shows a second Al pattern commonly connecting D _n2 .

As shown in the figure, in the SRAM cell according to the present invention,
For example, the ends of the active regions A ₁₁₁ and A ₁₁₂ on the n-type well on which the P ⁺ -type drain regions D _p11 and D _p12 are formed and the n ⁺ -type drains of the active regions A ₂₁ and A ₂₂ on the p-type substrate Distance to areas D _n1 and D _n2
With d _C fixed at the conventional dimensions,
A ₁₁₁ and A ₁₁₂ are bent at required dimensions in the drain portions D _p11 and D _p12 in a direction approaching the _VCC wiring. At this time, the lower regions of the gate electrodes G ₁ and G ₂ of the active regions A ₁₁₁ and A ₁₁₂ and the source regions _{Sp 11} and _{Sp 12} move in parallel in a direction approaching the _VCC line by the required size. At this time, the gate electrodes G ₁ and G ₂
It is extended to the V _CC wiring side. In addition, it is preferable that the parallel movement is such that the lower regions of the gate electrodes G ₁ and G ₂ and the source regions S _p11 and S _p12 are as close as possible to the position immediately below the _Vcc wiring.

Thereby, p constituting inverters INV ₁ and INV ₂
The p ⁺ -type source regions S _p11 and S _{p12 to} which the V _CC potential of the channel transistors PT ₁₁ and PT ₁₂ are applied, and the n ⁺ -type source region S to which the V _SS potential of the n-channel transistors NT ₁ and NT ₂ are applied
Since the distance d _D between _n1 and S _n2 is away than the distance d _C in the conventional structure, the latch-up phenomenon occurring between the p-channel region and an n-channel region is suppressed.

According to the present invention, if the latch-up resistance is maintained as it is, the arrangement pitch of the _VCC wiring can be further reduced, so that higher integration can be achieved.

〔The invention's effect〕

According to the present invention as described above, the latch-up phenomenon of the SRAM cell using the CMCS inverter is suppressed,
High reliability and high integration of the SRFM cell can be achieved.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of one embodiment of the present invention, FIG. 2 is a side sectional view (a) and an equivalent circuit diagram (b) for explaining a latch-up phenomenon, FIG. 3 is an equivalent circuit diagram of an SRAM cell, FIG. 4 is a schematic view of a conventional pattern arrangement of SRAM cells, FIG. 5 is a conventional active area pattern arrangement view, and FIG. 6 is an equivalent circuit diagram of a latch-up phenomenon between adjacent cells. In the figure, INV ₁ and INV ₂ are inverters, A ₁₁₁ and A ₁₁₂ are active regions on an n-type well, A ₂₁ and A ₂₂ are active regions on a p-type semiconductor substrate, FOX is a field oxide film, PT ₁₁ , PT ₁₂ is a p-channel transistor, NT ₁ and NT ₂ are n-channel transistors, TT ₁ and TT ₂ are transfer transistors, V _CC is a high-potential power supply line, V _SS is a ground power supply line, WL is a word line, S _p11 , S _p12 is a P ⁺ type source region, D _p11 and D _p12 are P ⁺ type drain regions, S _n1 and _Sn2 are n ⁺ type source regions, D _n1 and D _n2 are n ⁺ type drain regions, G ₁ and G ₂ , G ₃ and G ₄ indicate gate electrodes, H _{1 to} H ₈ indicate contact windows, and Al ₁ and Al ₂ indicate Al patterns.

Claims (1)

(57) [Claims] 1. A memory cell comprising a pair of complementary MOs on a semiconductor substrate.
The distance between the source region of the p-channel transistor fixed to the power supply potential of the inverter and the source region of the n-channel transistor fixed to the ground potential is an output part of the inverter. A semiconductor memory device formed to be larger than a distance between a drain region of the p-channel transistor and a drain region of the n-channel transistor.