JPH0582763A - Integrated circuit and its manufacture - Google Patents

Abstract

PURPOSE:To increase the number of function circuits mountable on one semiconductor substrate without losing the advantages of master slice method by changing the diffusion resistance value in the diffusion region of a transistor selected out of a plurality of transistors during the production of slice process. CONSTITUTION:N-type impurities are ion impregnated in such a manner that the diffusion resistance value of P-type diffusion region 5g changes from conventional diffusion resistance RPD to 4RPD+ (3/2) RPT for P-Type diffusion region 5h forming the source of P channel transistor 1d and P-type diffusion region 5g forming drain. Also in the P-type diffusion region 5h, N-type impurities are ion impregnated in such a manner that the diffusion resistance value changes from the conventional diffusion resistance RPS to 4RPS f (3/2) RPT. Then, P-type impurities are impregnated for N-type diffusion region forming the source and drain of N channel transistor in such a manner that the diffusion resistance value changes from the conventional diffusion resistance RND to 4 RND+ (3/2) RNT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device and a method of manufacturing the same, and more particularly to a structure of a gate array integrated circuit device by a master slice method and an improvement of the method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the shortening of the development cycle of electrical products and the differentiation from other companies' products,
There are increasing demands for semiconductor integrated circuit devices, such as shortening the development period, lowering the development cost, and realizing user-specific functions. To meet these demands,
There is a master slice type integrated circuit device in which each process up to the formation of a diffusion region is made common to all semiconductor integrated circuit devices, and customization is realized by subsequent wiring connection.

A manufacturing flow, a schematic configuration, a logic circuit and the like in such a conventional integrated circuit device are shown in FIGS.
Shown in. Here, FIG. 7 is an explanatory diagram showing a manufacturing flow of a master process in an integrated circuit device by a conventional master slice method, and FIG. 8 is an explanatory diagram showing a manufacturing flow of a slicing process in the same integrated circuit device. 9 is a plan view schematically showing a schematic configuration of an integrated circuit device according to a conventional master slice system, FIG. 10 is a plan pattern diagram schematically showing an outline of a basic cell in the same integrated circuit device, and FIG. 11 is the same integrated circuit device. FIG. 3 is a plan pattern view schematically showing a part of a basic cell row region for realizing an internal circuit in the device.

FIG. 12 is a logic circuit diagram of a latch circuit which holds an input signal and outputs an inverted signal. FIG. 13 is a transistor circuit diagram which constitutes the same latch circuit.
FIG. 16 is a layout pattern diagram schematically showing the outline of a latch circuit formed by the same transistor circuit. FIG. 15 is an explanatory diagram showing the resistance of the transistor portion when one P-channel transistor is turned on, and FIG. FIG. 17 is an explanatory diagram showing the resistance of the transistor part when the channel transistor is turned on. FIG. 17 is an explanatory diagram showing the resistance of the transistor part when the four P-channel transistors connected in series are turned on. It is explanatory drawing which shows the resistance of a transistor part when the N channel transistor connected in series turns on.

In the configuration shown in each of these conventional examples,
Reference numerals 1a to 1g and 2a to 2g are P-channel and N-channel transistors forming a transistor circuit, and 3,3a to 3h and 4,4a to 4h are P-channel and N-channel transistors. Forming the respective gate electrodes of polysilicon, 5, 5
a to 5i are P-type diffusion regions forming the source electrode or drain electrode of the P-channel transistor, 6, 6a to 6a
i is an N-type diffusion region forming a source electrode or a drain electrode of the N-channel transistor.

Further, 7a is VDD which is made of the first layer aluminum.
Wiring, 7b is a GND wiring made of the first layer aluminum, 7c to
Reference numeral 7j is each signal wiring made of the first layer aluminum, 8a to 8e are each signal wiring made of the second layer aluminum, and 9 is each polysilicon and the first layer aluminum, or each diffusion region and the first layer aluminum. Contact holes for electrically connecting the first layer aluminum and the second layer aluminum to each other, and 11 and 11a.
~ 11h is the source electrode resistance of each transistor, 1
2, 12a to 12h are ON resistances of the respective transistors,
Reference numerals 13, 13a to 13h denote drain electrode resistances of the respective transistors.

Further, 14 is an integrated circuit device, 15 is an input / output buffer circuit area forming a circuit for interfacing signals between the internal circuit of the integrated circuit device 14 and the outside, and 16 is the integrated circuit device 14. An internal circuit area in which various gates, flip-flops, and the like for realizing required logical functions are formed.
And 17c are inverter circuits, and 18 is a transmission gate.

Next, a conventional master slice type integrated circuit device having the above structure will be described. In this type of master slice type integrated circuit device, the layout pattern up to the diffusion region formation is made common to all integrated circuit devices, and it is possible to manufacture the diffusion region formation process in advance. Therefore, an integrated circuit device that has completed the diffusion region forming step is called a master (hereinafter, referred to as a "same").

First, the master process in the integrated circuit device of the master slice system will be described with reference to the manufacturing flow of FIG. In this master process, first,
A well is formed on a semiconductor substrate (step, S7-
01), an active area for forming each element such as a transistor is formed in the well (step, S7-02), and then the gate electrode of each MOS transistor and other signal wiring are formed. Polysilicon is formed on each (step, S7-03).

Subsequently, P-type impurity ions are implanted to form P-type diffusion regions serving as the source / drain of the P-channel transistor (step, S7-04), and this time, N-type impurity ions are added. Implantation is performed to form N-type diffusion regions forming the source / drain of the N-channel transistor (step, S7-05), and the intended master is thus obtained.

After that, with respect to the master having the above-mentioned configuration, it is a slice (hereinafter, referred to as this) that the integrated circuit device is customized by selecting connections between respective elements or the like by desired wiring. ,
A description will be given with reference to the manufacturing flow of FIG.

In this slicing process, first, the first
After forming a contact hole at a position where the layer aluminum wiring should be connected (step, S8-01), the first layer aluminum wiring is formed (step, S8-02), and then the first layer aluminum wiring and the first layer aluminum wiring are connected. After forming a through hole at the position where the two-layer aluminum wiring should be connected (step, S8-03), the second-layer aluminum wiring is formed (step, S8-04), and the integrated circuit device is externally connected. A passivation film is formed to protect it from damage (step, S8-05). Here, the passivation film is
Similar to the master, it is common to all integrated circuit devices, and the wafer manufacturing is completed as described above.

Next, a layout pattern of the conventional master slice type integrated circuit device having the above structure will be described. As shown in the main outline of FIG. 9, in the peripheral portion of the integrated circuit device 14, input / output buffer circuits 15 for interfacing signals between the internal circuit and the outside are arranged. Inside each area surrounded by the buffer circuit 15, each internal gate region 16 that configures various gates, flip-flops, and the like for realizing the logical function required by the device 14 is provided.

Further, as in the layout pattern whose main outline is shown in FIG. 10, the basic cell, which is a basic unit for realizing the internal gate region 16, has a P-type diffusion region 5 and an N-type diffusion region 6. Two gate polysilicons 3 and 4 are arranged on each of the regions 5 and 6 while facing each other. Then, as described above, due to the connection after the wiring process, one set of two P-channel transistors using each gate polysilicon 3 as a gate electrode and each P-type diffusion region 5 as a source / drain are formed. Configurable, and each gate polysilicon 4 is a gate electrode,
A set of two N-channel transistors can be configured using each N-type diffusion region 6 as a source / drain.

Further, the internal gate region 16 shown in FIG.
11 has a configuration in which a plurality of the basic cells shown in FIG. 10 are arranged adjacent to each other as in the layout pattern shown in FIG. 11 as a main outline. 9 to FIG.
Each configuration of the integrated circuit device 14 and the basic cell shown in FIG. 11 is determined in advance.

On the other hand, in the gate array type integrated circuit device, various usable gates, flip-flops and the like are prepared in advance as library cells in order to realize a desired logic function. An example of this library cell will be described for the latch circuit shown in the logic circuit diagram of FIG.

The latch circuit of FIG. 12 is an inverter circuit 1
7a, 17b, 17c and transmission gate 1
8 and. That is, the input end of the inverter circuit 17a is connected to the signal input terminal A of the latch circuit, and the output end of the inverter circuit 17a is connected to the internal terminal B for signal input of the transmission gate 18.
Connected to. Also, the transmission gate 1
The control input terminals T1 and T2 of the latch circuit are respectively connected to the two control input terminals 8 and the signal output internal terminal C of the transmission gate 18 is connected to the input terminal of the inverter circuit 17b. It is connected to the output terminal of the inverter circuit 17c.

Further, the output end of the inverter circuit 17b and the input end of the inverter circuit 17c are connected to the signal output terminal Y of this latch circuit. Therefore, in the latch circuit configured as described above, the control input terminals T1 and T2 are
The control of the data holding state and the data through state is performed by inputting each control signal to the.

Next, the operation of the latch circuit in the above configuration in the data through state will be described. First, when the signal a is input to the signal input terminal A of this latch circuit, the signal a here is inverted by the inverter circuit 17a, and the inverted signal of the signal a is input to the internal terminal B of the transmission gate 18. The output signal and the inverted signal of the signal a are output to the internal terminal C via the transmission gate 18.

Further, this inverted signal is supplied to the inverter circuit 1
7b, the signal a is output from the signal output terminal Y of the present latch circuit, and the inverter circuit 17
An inverted signal of the signal a is output from c to the internal terminal C.

Next, the signal input terminal A of this latch circuit
When the signal input to is changed from the signal a to the inverted signal of the signal a, the inverted signal of the signal a here is inverted by the inverter circuit 17a and the signal a is output to the internal terminal B of the transmission gate 18. And this signal a
Is output to the internal terminal C via the transmission gate 18.

Therefore, at this time, the internal terminal C is
From the inverter circuit 17a to the transmission gate 1
The signal a that has passed through 8 is output, and at the same time, the inverted signal of the signal a from the inverter circuit 17c is output. In this case, the signal at the internal terminal C corresponds to the drive capability of the inverter circuit 17a. Inverter circuit 17c
Since the inverter circuit 17c mainly plays a role of holding data, it is desirable that the driving capability of the inverter circuit 17c is small because it is determined by the magnitude relationship with the driving capability of the.

Now, the configuration of the latch circuit realized in consideration of the above points, that is, the configuration of the latch circuit whose logic circuit diagram is shown in FIG. 12 will be described with reference to the transistor circuit shown in FIG.

In the circuit configuration of FIG. 13, the P-channel transistor 1 is connected to the signal input terminal A of this latch circuit.
a and the gate terminal of the N-channel transistor 2a are connected, the source terminal of the P-channel transistor 1a is connected to VDD, the drain terminal is connected to the internal terminal B, and the source terminal of the N-channel transistor 2a is connected to GND. Further, the drain terminals are respectively connected to the internal terminals B, and the P-channel transistor 1a and the N-channel transistor 2a form an inverter circuit 17a.

The gate terminal of the P-channel transistor 1b is connected to the control signal input terminal T2 of the latch circuit, and the source terminal of the P-channel transistor 1b is the internal terminal B and the drain terminal is the internal terminal C. Further, the gate terminal of the N-channel transistor 2b is connected to the control signal input terminal T1 of the latch circuit, the source terminal of the N-channel transistor 2b is connected to the internal terminal B, and the drain terminal is connected to the inside. These P-channel transistor 1b and N-channel transistor 2 are connected to the terminal C respectively.
The transmission gate 18 is formed by b.

The internal terminal C has a P-channel transistor 1c and an N-channel transistor 2c.
, The source terminal of the P-channel transistor 1c is connected to VDD, the drain terminal is connected to the signal output terminal Y of the latch circuit, and the source terminal of the N-channel transistor 2c is GND.
Similarly, the drain terminal is also the signal output terminal Y of the latch circuit.
And the P-channel transistor 1c and the N-channel transistor 2c are connected to each other to form an inverter circuit 17b.

Further, the source terminal of the P-channel transistor 1d is connected to VDD, the drain terminal is connected to the source terminal of the P-channel transistor 1e in the next stage, and the drain terminal of the P-channel transistor 1e is connected to the P-channel transistor 1f in the next stage. The P-channel transistor 1f is connected to the source terminal, and the drain terminal of the P-channel transistor 1f is connected to the source terminal of the P-channel transistor 1g in the next stage.
The drain terminal of the channel transistor 1g is connected to the internal terminal C, and the gate terminals of these P channel transistors 1d to 1g are all connected to the signal output terminal Y of the latch circuit.

Also, the source terminal of the N-channel transistor 2g is connected to GND, the drain terminal is connected to the source terminal of the N-channel transistor 2f in the preceding stage, and the drain terminal of the N-channel transistor 2f is the source of the N-channel transistor 2e in the preceding stage. Connected to the terminal,
The drain terminal of the channel transistor 2e is connected to the source terminal of the preceding N-channel transistor 2d, the drain terminal of the N-channel transistor 2d is connected to the internal terminal C, and the gates of the N-channel transistors 2g to 2d are connected. The terminals are all connected to the signal output terminal Y of the latch circuit, respectively, and the P-channel transistors 1d to 1g and the N-channel transistors 2d to 2g connect the inverter circuit 17 to each other.
It constitutes c.

As described above, in the integrated circuit device 14 of the master slice system, in order to make the master common, the transistors used are fixed to one type shown in FIG. 10, and four such transistors are connected in series. By configuring, the required driving ability is obtained.

Next, a layout pattern for realizing the latch circuit shown in the transistor circuit of FIG. 13 is shown in FIG.
, And the details will be described. In the configuration of FIG. 14, polysilicon gates 3a, 3b, 3c, 3d, 3
e, 3f, 3g and 3h are P-channel transistors 1
a, 1b, 1c, 1d, 1e, 1f, 1g gate electrodes are respectively formed, and polysilicon gates 4a, 4b,
4c, 4d, 4e, 4f, 4g and 4h are P-channel transistors 2a, 2b, 2c, 2d, 2e, 2f and 2g.
The respective gate electrodes are formed.

The P-type diffusion region 5a serves as the source electrode of the P-channel transistor 1a, and the P-type diffusion region 5b serves as the P-type diffusion region 5b.
The drain electrode of the P-channel transistor 1a and the source electrode of the P-channel transistor 1b are connected to the P-type diffusion region 5
c is the drain electrode of the P-channel transistor 1b,
The P-type diffusion region 5d constitutes the source electrode of the P-channel transistor 1c, and the P-type diffusion region 5e constitutes the drain electrode of the P-channel transistor 1c.

The P-type diffusion region 5l is the source electrode of the P-channel transistor 1d, the P-type diffusion region 5k is the drain electrode of the P-channel transistor 1d and the source electrode of the P-channel transistor 1e, and the P-type diffusion region 5j is the same. ,
The drain electrode of the P-channel transistor 1e, the P-type diffusion region 5i is the source electrode of the P-channel transistor 1f, and the P-type diffusion region 5h is the P-channel transistor 1e.
The drain electrode of f and the source electrode of the P-channel transistor 1g, and the P-type diffusion region 5g respectively configure the drain electrode of the P-channel transistor 1g.

The N-type diffusion region 6a is formed by connecting the source electrode of the N-channel transistor 2a to the N-type diffusion region 6b.
Is the drain electrode of the N-channel transistor 2a and the source electrode of the N-channel transistor 2b, the N-type diffusion region 6c is the drain electrode of the N-channel transistor 2b, and the N-type diffusion region 6d is the N-channel transistor 2c.
And the N-type diffusion region 6e constitutes the drain electrode of the N-channel transistor 2c.

The N-type diffusion region 6l serves as the source electrode of the N-channel transistor 2g, the N-type diffusion region 6k serves as the drain electrode of the N-channel transistor 2g and the source electrode of the N-channel transistor 2f, and the N-type diffusion region 6j serves as the N-type diffusion region 6j. ,
The drain electrode of the N-channel transistor 2f, the N-type diffusion region 6i is the source electrode of the N-channel transistor 2e, and the N-type diffusion region 6h is the N-channel transistor 2f.
The drain electrode of e and the source electrode of the N-channel transistor 2d, and the N-type diffusion region 6g respectively configure the drain electrode of the N-channel transistor 2d.

As the signal input terminal A, the second layer aluminum signal wiring 8a is formed, and the second layer aluminum signal wiring 8a is formed.
Is the first layer aluminum signal wiring 7 through the through hole 10.
The first-layer aluminum signal wiring 7c is connected to the polysilicon gates 3a and 4a through the contact hole 9.
Connected to. The P-type diffusion region 5a is connected to the first-layer aluminum VDD wiring 7a through a contact hole 9, and N
The type diffusion region 6a is connected to the first layer aluminum GND wiring 7b through the contact hole 9.

The P-type diffusion region 5b is connected to the second-layer aluminum signal wiring 8b through the contact hole 9, the first-layer aluminum signal wiring 7d, and the through hole 10, and the N-type diffusion region 6b is connected to the contact hole 9 ,. It is connected to the second-layer aluminum signal wiring 8b through the first-layer aluminum signal wiring 7e.

A second layer aluminum signal wiring 8d is formed as the control signal input terminal T2, and the second layer aluminum signal wiring 8d is formed through the through hole 10 and the first layer aluminum signal wiring 7.
g, polysilicon gate 3 through contact hole 9
a second control signal input terminal T1
A layer aluminum signal wiring 8c is formed, and the second layer aluminum signal wiring 8c is connected to the polysilicon gate 4b through the through hole 10, the first layer aluminum signal wiring 7h, and the contact hole 9.

The P-type diffusion region 5c and the N-type diffusion region 6c are
First layer aluminum signal wiring 7f through contact hole 9
The first-layer aluminum signal wiring 7f is connected to the polysilicon gates 3c, 4c,
And a P-type diffusion region 5g and an N-type diffusion region 6g. The P type diffusion region 5d is connected to the first layer aluminum VDD wiring 7a through the contact hole 9, and the N type diffusion region 6d is connected through the contact hole 9 to the first layer aluminum GN.
It is connected to the D wiring 7b.

The P type diffusion region 5e and the N type diffusion region 6e are
First layer aluminum signal wiring 7i through contact hole 9
The first-layer aluminum signal wiring 7i is connected to the polysilicon gates 3e, 3f,
3g, 3h and 4e, 4f, 4g, 4h, and are also connected to the second-layer aluminum signal wiring 8e via the through hole 10 and the second-layer aluminum signal wiring 8e.
Constitute the signal output terminal Y.

P-type diffusion region 5i and P-type diffusion region 5j are connected to each other through contact hole 9 and first layer aluminum signal wiring 7j, and N-type diffusion region 6i and N-type diffusion region 6j are The contact hole 9 and the first layer aluminum signal wiring 7h are connected to each other. P-type diffusion region 5l
Is connected to the first-layer aluminum VDD wiring 7a through the contact hole 9, and the N-type diffusion region 6l is connected to the first-layer aluminum GND wiring 7b through the contact hole 9.

As described above, the latch circuits shown in FIGS. 12 and 13 are realized by using four basic cells and 14 transistors. Next, in FIG.
The drive capability of each circuit in the latch circuit shown in FIG.

The driving capability of the transistor in the basic cell is considered as the reciprocal of the resistance value when the transistor is turned on, and in FIG. 15, the transistor portion in the transistor portion when this one P-channel transistor is turned on is considered. A resistance configuration is shown, and the resistance of the P-channel transistor portion is such that the diffusion resistance R _PS of the source region 11, the ON resistance R _PT of the transistor portion 12, and the diffusion resistance R _PD of the drain region 13 are connected in series. The resistance value R _P in this case can be expressed as R _P = R _PS + R _PT + R _PD (1).

Similarly, FIG. 16 shows a resistance configuration in the transistor portion when the one N-channel transistor is turned on, and the resistance of the N-channel transistor portion is the diffusion of the source region 11. Resistance R _NS
When the ON resistance R _NT of the transistor 12, believed to have the diffusion resistance R _ND of the drain region 13 are connected in series, the resistance R _N in this _{case, R N = R NS + R} NT + R ND It can be expressed as (2).

Further, the driving ability of the inverter circuits 17a and 17b composed of four transistors is considered as the reciprocal of each resistance value shown in the equations (1) and (2).
FIG. 7 shows a resistance configuration in the transistor portion when the four P-channel transistors are turned on.

The resistance of the P-channel transistor section is
Diffusion resistance R _PS of the source region 11a, ON resistance R _PT of the transistor portion 12a, diffusion resistance R _PD of the drain region 13a, diffusion resistance R _PS of the source region 11b, ON resistance R _PT of the transistor portion 12b, drain region Diffusion resistance R _{PD of} 13b, diffusion resistance R _PS of the source region 11c, ON resistance R _PT of the transistor portion 12c, diffusion resistance R _PD of the drain region 13c, diffusion resistance R _PS of the source region 11d, and the transistor portion 12d. It is considered that the ON resistance R _PT and the diffusion resistance R _PD of the drain region 13d are connected in series.

In this case, the resistance value R is R = {4R _PS + (3/2) R _PT } + R _PT + {4R _PD + (3/2) R _PT } = 4R _PS + 4R _PT + 4R _PD = 4 ( R _PS + R _PT + R _PD ) ... It can be expressed as (3).

Similarly, FIG. 18 shows a resistance configuration in the transistor portion when the four N-channel transistors are turned on. The resistance of the N-channel transistor portion is the diffusion of the drain region 13e. Resistance R _ND , ON resistance R _NT of the transistor portion 12e, diffusion resistance R _NS of the source region 11e, diffusion resistance R _ND of the drain region 13f, ON resistance R of the transistor portion 12f.
_NT , diffusion resistance R _NS of the source region 11f, diffusion resistance R _ND of the drain region 13g, O of the transistor portion 12g.
N resistance R _NT , diffusion resistance R _NS of the source region 11 g, diffusion resistance R _ND of the drain region 13 h, the transistor section 1
2h ON resistance R _NT , source region 11h diffusion resistance R _NS
It is considered that and are connected in series.

In this case, the resistance value R is R = {4R _NS + (3/2) R _NT } + R _NT + {4R _ND + (3/2) R _NT } = 4R _NS + 4R _NT + 4R _ND = 4 ( R _NS + R _NT + R _ND ) ... (4) can be represented.

The driving ability of the inverter circuit 17c composed of four transistors is expressed by the above equation (9),
It can be considered as the reciprocal of each resistance value shown in and (10).

[0050]

The conventional master slice type integrated circuit device is manufactured by the means as described above, and the circuit configuration is realized by combining the basic transistors having the same driving capability. In order to realize a transistor with a desired driving ability, it is necessary to use a large number of transistors that are not necessary for logical operation, and the number of logic circuits mounted on the integrated circuit device is reduced. There was a problem that became.

The present invention has been made to solve the above-mentioned conventional problems, and its purpose is to prevent the advantages of the integrated circuit device of the master slice system from being deteriorated. By providing an integrated circuit device of this type and a method for manufacturing the same, which is capable of increasing the number of logic circuits that can be mounted on the integrated circuit device, a master slice type integrated circuit device and a method for manufacturing the integrated circuit device are provided. is there.

[0052]

In order to achieve the above object, an integrated circuit device according to the present invention and a method for manufacturing the same are provided with a diffusion resistance value of a diffusion region in a selected transistor among a plurality of transistors. It was made to change.

That is, the present invention has a plurality of transistors each having a diffusion region serving as a source / drain which is set to a predetermined reference diffusion resistance value, and has a manufacturing process up to the diffusion region formation of each transistor. In advance, as a master process, the manufacturing process such as wiring connection of each transistor after that is customized as a slicing process to realize a desired functional circuit by the master slicing method of the integrated circuit device configuration. The integrated circuit device is characterized in that a diffusion resistance value of a diffusion region in a selected transistor among a plurality of transistors is set to be different from the reference diffusion resistance value.

Further, the present invention has a plurality of transistors each having a diffusion region serving as a source / drain which is set to a predetermined reference diffusion resistance value and is formed, and a manufacturing process until the diffusion region of each transistor is formed. In the manufacturing method of the integrated circuit device by the master slice method, which is manufactured in advance as a master process, and the manufacturing process such as wiring connection in each transistor after that is customized as a slice process to realize a required functional circuit. ,
In the slicing step after the master step is finished, the method includes a manufacturing step of changing a diffusion resistance value of a diffusion region in a selected transistor among the plurality of transistors with respect to the reference diffusion resistance value. And a method for manufacturing an integrated circuit device.

[0055]

Therefore, in the integrated circuit device according to the present invention,
Since the diffusion resistance value of the diffusion region of the selected transistor among the plurality of transistors is changed, the driving ability of the transistor in the finally obtained functional circuit can be arbitrarily set as desired. ..

[0056]

Embodiments of an integrated circuit device and a method of manufacturing the same according to the present invention will be described below in detail with reference to FIGS.

[First Embodiment] FIG. 1 is an explanatory view showing a manufacturing flow of a slicing process in an integrated circuit device by a master slice system to which the first embodiment of the present invention is applied, and FIG. 2 is the same as the above. 12 is a transistor circuit diagram showing a configuration when the latch circuit in the logic circuit diagram of FIG. 12 is realized, and FIG. 3 is a layout pattern diagram schematically showing an outline of a latch circuit by the same transistor circuit as above.

FIG. 4 is a circuit diagram of 1 in the transistor circuit of FIG.
5 is an explanatory diagram showing the resistance of the transistor portion when the P-channel transistors are turned on, and FIG. 5 is an explanatory diagram showing the resistance of the transistor portion when one N-channel transistor in the transistor circuit of FIG. 2 is turned on. Here, in the drawings showing the first embodiment, the same reference numerals as those in the drawings showing the conventional example represent the same or corresponding portions.

FIG. 1 shows the manufacturing flow of the slicing process of the integrated circuit device by the master slice method in the first embodiment.
Will be described. First, the driving capability of the integrated circuit device which has completed the diffusion region forming step described as the conventional example, that is, the P-channel and N-channel transistors forming each transistor circuit on the master, is changed from the standard. The resistance value of the diffusion region in each transistor is changed by performing the following operation for each desired transistor.

That is, first, with respect to the P-type diffusion region which constitutes the source and drain of an arbitrary P-channel transistor whose drive capability is to be changed from the standard, impurities of the opposite conductivity type are applied so that the P-type diffusion region has a desired diffusion resistance value. That is, the N-type impurity is ion-implanted, and then the desired diffusion resistance value is set to the N-type diffusion region forming the source and drain of any N-channel transistor whose drive capability is to be changed from the standard. Similarly, ion implantation of P-type impurities is performed, and the resistance value of the diffusion region in each transistor is changed by partially ion-implanting reverse-type impurities (step S1-01). ..

Subsequently, as in the conventional case, the first
After forming a contact hole at a position where the layer aluminum wiring should be connected (step, S1-02), the first layer aluminum wiring is formed (step, S1-03), and further, the first layer aluminum wiring and the first layer aluminum wiring are connected. After forming a through hole at a position where the two-layer aluminum wiring should be connected (step, S1-04), the second-layer aluminum wiring is formed (step, S1-05), and finally, the integrated circuit device is formed. Wafer fabrication is completed by forming a passivation film that protects from the outside (step, S1-06).

Next, the structure of the latch circuit shown in the logic circuit diagram of FIG. 12 in the integrated circuit device of the master slice system of the first embodiment having the above structure will be described with reference to the transistor circuit shown in FIG.

In the circuit configuration of FIG. 2, the signal input terminal A of the present latch circuit is connected to the gate terminals of the P-channel transistor 1a and the N-channel transistor 2a, and the source terminal of the P-channel transistor 1a is VDD. , The drain terminal is connected to the internal terminal B, the source terminal of the N-channel transistor 2a is connected to GND, and the drain terminal is connected to the internal terminal B.
The inverter circuit 17a is composed of a and the N-channel transistor 2a.

Further, the control signal input terminal T of this latch circuit
2, the gate terminal of the P-channel transistor 1b is connected, the source terminal of the P-channel transistor 1b is connected to the internal terminal B, and the drain terminal is connected to the internal terminal C. The gate terminal of the N-channel transistor 2b is connected to the terminal T1, the source terminal of the N-channel transistor 2b is connected to the internal terminal B, and the drain terminal is connected to the internal terminal C. The transmission gate 18 is composed of 1b and the N-channel transistor 2b.

The internal terminal C has a P-channel transistor 1c and an N-channel transistor 2c.
Is connected to the source terminal of the P-channel transistor 1c is connected to VDD, the drain terminal is connected to the signal output terminal Y of the latch circuit, and the source terminal of the N-channel transistor 2c is connected to GND.
Similarly, the drain terminal is similarly connected to the signal output terminal Y of the present latch circuit, and the P-channel transistor 1c and the N-channel transistor 2c constitute the inverter circuit 17b.

Further, the source terminal of the P-channel transistor 1d is connected to VDD, the drain terminal is connected to the internal terminal C, the source terminal of the N-channel transistor 2d is connected to GND, and the drain terminal is connected to the internal terminal C, and The gate terminals of the P-channel transistor 1d and the N-channel transistor 2d are connected to the signal output terminal Y of the present latch circuit, respectively, and the inverter circuit 17c is connected by the P-channel transistor 1d and the N-channel transistor 2d. I am configuring.

Subsequently, a layout pattern for realizing the latch circuit shown in the transistor circuit of FIG. 2 is shown in FIG. 3 and its details will be described. In the structure of FIG. 3, the polysilicon gates 3a, 3b, 3c and 3e form the gate electrodes of the P-channel transistors 1a, 1b, 1c and 1d, respectively, and the polysilicon gates 4a, 4b and 4e.
c and 4e are P-channel transistors 2a, 2b and 2
The gate electrodes of c and 2d are respectively configured.

The P-type diffusion region 5a serves as the source electrode of the P-channel transistor 1a, and the P-type diffusion region 5b serves as the P-type diffusion region 5b.
The drain electrode of the P-channel transistor 1a and the source electrode of the P-channel transistor 1b are connected to the P-type diffusion region 5
c is the drain electrode of the P-channel transistor 1b,
The P-type diffusion region 5d is the source electrode of the P-channel transistor 1c, the P-type diffusion region 5e is the drain electrode of the P-channel transistor 1c, and the P-type diffusion region 5h is the source electrode of the P-channel transistor 1d. The diffusion region 5g constitutes the drain electrode of the P-channel transistor 1d, respectively.

The N-type diffusion region 6a is formed by connecting the source electrode of the N-channel transistor 2a to the N-type diffusion region 6b.
Is the drain electrode of the N-channel transistor 2a and the source electrode of the N-channel transistor 2b, the N-type diffusion region 6c is the drain electrode of the N-channel transistor 2b, and the N-type diffusion region 6d is the N-channel transistor 2c.
, The N-type diffusion region 6e is the drain electrode of the N-channel transistor 2c, and the N-type diffusion region 6h is
The source electrode of the N-channel transistor 2d constitutes the drain electrode of the N-channel transistor 2d, and the N-type diffusion region 6g constitutes the drain electrode of the N-channel transistor 2d.

As the signal input terminal A, the second layer aluminum signal wiring 8a is formed, and the second layer aluminum signal wiring 8a is formed.
Is the first layer aluminum signal wiring 7 through the through hole 10.
The first-layer aluminum signal wiring 7c is connected to the polysilicon gates 3a and 4a through the contact hole 9.
Connected to. Further, the P type diffusion region 5a is connected to the first layer aluminum VDD wiring 7a via the contact hole 9, and the N type diffusion region 6a is connected to the first layer aluminum GND wiring 7b via the contact hole 9. ..

The P type diffusion region 5b is connected to the second layer aluminum signal wiring 8b via the contact hole 9, the first layer aluminum signal wiring 7d and the through hole 10, and the N type diffusion region 6b is connected to the contact hole 9, It is connected to the second-layer aluminum signal wiring 8b through the first-layer aluminum signal wiring 7e.

A second layer aluminum signal wiring 8d is formed as a control signal input terminal T2, and the second layer aluminum signal wiring 8d is formed through the through hole 10 and the first layer aluminum signal wiring 7.
g, polysilicon gate 3 through contact hole 9
a second control signal input terminal T1
A layer aluminum signal wiring 8c is formed, and the second layer aluminum signal wiring 8c is connected to the polysilicon gate 4b through the through hole 10, the first layer aluminum signal wiring 7h, and the contact hole 9.

The P-type diffusion region 5c and the N-type diffusion region 6c are
First layer aluminum signal wiring 7f through contact hole 9
The first-layer aluminum signal wiring 7f is connected to the polysilicon gates 3c, 4c,
And a P-type diffusion region 5g and an N-type diffusion region 6g. The P type diffusion region 5d is connected to the first layer aluminum VDD wiring 7a through the contact hole 9, and the N type diffusion region 6d is connected through the contact hole 9 to the first layer aluminum GN.
It is connected to the D wiring 7b.

The P-type diffusion region 5e and the N-type diffusion region 6e are
First layer aluminum signal wiring 7i through contact hole 9
The first-layer aluminum signal wiring 7i is connected to the polysilicon gates 3e and 4e through the contact hole 9.
And the second layer aluminum signal wiring 8 through the through hole 10.
The second-layer aluminum signal wiring 8e constitutes the signal output terminal Y while being connected to each of the above-mentioned second layer aluminum signal wirings 8e.

The P-type diffusion region 5h is provided with the contact hole 9
The N-type diffusion region 6h is connected to the first-layer aluminum VDD wiring 7a via the contact hole 9 and the first-type aluminum VDD wiring 7a via the contact hole 9.
It is connected to the layer aluminum GND wiring 7b. as mentioned above,
The latch circuits shown in FIGS. 12 and 2 are realized by using three basic cells and eight transistors. Next, the drive capability of each circuit when the latch circuit shown in FIG. 12 is realized by the configuration of the first embodiment shown in FIG. 2 will be described.

The driving capability of the standard transistor in the basic cell is exactly the same as that of the conventional configuration described above, and the P-channel transistors 1a, 1b and 1c and the N-channel transistors 2a, 2b and 2c are used. The resistance values when and are ON are exactly the same as in the case of the conventional configuration, and the drive capability of the inverter circuits 17a and 17b is the same as the resistance values shown in the equations (7) and (8). Think of it as the reciprocal of. Here, P according to the first embodiment described above is used.
The channel transistor 1d and the N-channel transistor 2d will be described.

First, with respect to the P-type diffusion region 5h forming the source and the P-type diffusion region 5g forming the drain of the P-channel transistor 1d according to the first embodiment, the diffusion resistance of the P-type diffusion region 5g is reduced. The value is the conventional diffusion resistance R
From _PD 4R _PD + (3/2) so that the R _PT ‥‥ (5), the N-type impurity is ion-implanted.

In the P-type diffusion region 5h, an N-type impurity is ionized so that the diffusion resistance value becomes 4R _PS + (3/2) R _PT (6) from the conventional diffusion resistance R _PS. inject.

Then, an N-type diffusion region 6h constituting the source of the N-channel transistor 2d according to the first embodiment,
In contrast to the N-type diffusion region 6g forming the drain, the diffusion resistance value of the N-type diffusion region 6g is changed from the conventional diffusion resistance R _ND to 4R _ND + (3/2) R _NT (7). So that P-type impurities are ion-implanted.

[0080] Further, the N-type diffusion region 6h, its diffusion resistance, so that the 4R _NS + conventional diffusion resistance _{R NS (3/2) R NT ‥‥} (8), P -type impurities, respectively Is ion-implanted.

Here, FIG. 4 shows a resistance configuration in the transistor portion when the P-channel transistor 1d in FIG. 2 is turned on. The resistance of the P-channel transistor part is the source region 11 shown in the equation (6).
a diffusion resistance 4R _PS + (3/2) R _PT , the ON resistance R _PT of the transistor portion 12a, and the diffusion resistance 4R _PD + (3/2) R _{PT of} the drain region 13a shown in the equation (5). It is considered that and are connected in series.

In this case, the resistance value R is R = ( _RPS + _RPT + _RPD ) + ( _RPS + _RPT + _RPD ) + ( _RPS + _RPT + _RPD ) + ( _RPS + _RPT + _RPD ) = 4 (R _PS + R _PT + R _PD ) + (R _PS + R _PT + R _PD ) ... (9)

Similarly, FIG. 5 shows a resistance configuration in the transistor portion when the N-channel transistor 2d in FIG. 2 is turned on. Resistance of the N-channel transistor portion, the diffusion resistance 4R _NS + (3/2) and R _NT source region 11e shown in (8), the ON resistance R _NT of the transistor portion 12e, the (7) It is considered that the diffusion resistance 4R _ND + (3/2) R _{NT of the} illustrated drain region 13e is connected in series.

In this case, the resistance R is R = (R _NS + R _NT + R _ND ) + (R _NS + R _NT + R _ND ) + (R _NS + R _NT + R _ND ) + (R _NS + R _NT + R _ND ) = 4 (R _NS + R _NT + R _ND ) + (R _NS + R _NT + R _ND ) ... (10)

Further, the drive capability of the inverter circuit 17c formed of the transistors in the latch circuit in the first embodiment is considered as the reciprocal of each resistance value shown in the equations (9) and (10), and Eqs. 9) and (3), and (1
Since the equation (0) and the equation (4) both have the same resistance value, as a result, the configuration according to the first embodiment has the same performance as that of the configuration of the conventional example described above. It is possible to easily realize circuits having the same function.

[Second Embodiment] In the first embodiment, as shown in FIG. 1, in a slice manufacturing process, an impurity of opposite conductivity type is ion-implanted in a diffusion region of a predetermined transistor. By injecting, the resistance value of the diffusion region in the corresponding predetermined transistor is reduced,
A transistor with a desired drive capacity is realized, but the second
As is clear from the manufacturing flow of the slicing process in the integrated circuit device by the master slicing method shown in FIG. 6 as an example, with respect to the diffusion region of each predetermined transistor,
Further, it is possible to increase the resistance value of the diffusion region of the corresponding partially predetermined transistor by ion-implanting the impurities of the same conductivity type to realize a transistor having a desired driving capability.

That is, in the manufacturing flow of FIG.
First, for a P-type diffusion region that constitutes the source and drain of an arbitrary P-channel transistor whose drive capability is to be changed from the standard, the same conductivity type, P ( Re-implantation of P ⁻ ) -type impurities is performed (step, S6-01), and this is desired for the N-type diffusion region that constitutes the source and drain of any N-channel transistor whose drive capability is to be changed from the standard. In the same manner, re-ion implantation of N (N ⁻ ) P-type impurities is performed so that the diffusion resistance value of each of these transistors is partially diffused by ion implantation of impurities of the same conductivity type. Change the resistance value of the area (step, S6-02).

Subsequently, as in the case of the first embodiment, contact holes are formed at the positions where the first-layer aluminum wirings should be connected (step S6-03), and then the first-layer aluminum wirings are formed. Is formed (step, S6-04), a through hole is formed at a position where the first layer aluminum wiring and the second layer aluminum wiring should be connected (step, S6-05), and then the second layer is formed. Form aluminum wiring (step, S6-06), and finally,
A passivation film that protects the integrated circuit device from the outside is formed (step, S6-07), and the wafer manufacturing is completed.

[Third Embodiment] Further, in the first embodiment, as shown in FIG. 1, in the slice manufacturing process, the impurity of the opposite conductivity type is applied to the diffusion region of each predetermined transistor. By implanting ions, the resistance value of the diffusion region of the corresponding predetermined transistor is reduced to realize a transistor having a desired driving capability. In addition, as a third embodiment, The present invention can be applied to achieve a desired theoretical threshold value instead of changing the driving ability, and the same action and effect can be obtained.

[Fourth Embodiment] Further, in the first embodiment, as shown in FIG. 1, in the slice manufacturing process, the impurity of the opposite conductivity type is applied to the diffusion region of each predetermined transistor. By ion-implanting, the resistance value of the diffusion region of the corresponding part of the predetermined transistor is reduced to realize a transistor having a desired driving capability.
Separately, in the fourth embodiment, instead of controlling the diffusion resistance value as described above, the effective gate length of the transistor may be controlled to realize a transistor having a desired driving capability. The effect is obtained.

[0091]

As described above in detail with reference to the embodiments, according to the present invention, a plurality of transistors each having a diffusion region serving as a source / drain set to a predetermined reference diffusion resistance value are formed. Having the manufacturing process up to the diffusion region formation of each transistor as a master process in advance, the manufacturing process such as wiring connection of each transistor after that is customized as a slicing process to manufacture the required functional circuit. In an integrated circuit device by the master slice method to be realized, the same master obtained in the master process is used, and the diffusion resistance value of the diffusion region of the transistor selected from among the plurality of transistors at the time of manufacturing the slice process. , The driving capability of the transistor in the functional circuit to be configured is changed as expected. It can be set arbitrarily and can realize a circuit configuration with the same performance and function as the conventional one with a smaller number of transistors. As a result, the advantages of the master slice method are not impaired at all, and it is possible to realize it on one semiconductor substrate. It has an excellent feature that the number of functional circuits that can be installed can be increased.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a manufacturing flow of a slicing process of an integrated circuit device by a master slice system to which a first embodiment of the present invention is applied.

FIG. 2 is a transistor circuit diagram showing a configuration of a latch circuit in manufacturing the integrated circuit device of FIG.

FIG. 3 is a layout pattern diagram schematically showing an outline of a latch circuit including the transistor circuit of FIG.

FIG. 4 is an explanatory diagram showing resistance of a transistor portion when one P-channel transistor in the transistor circuit of FIG. 2 is turned on.

5 is an explanatory diagram showing resistance of a transistor portion when one N-channel transistor in the transistor circuit of FIG. 2 is turned on.

FIG. 6 is an explanatory view showing a manufacturing flow of a slicing process of an integrated circuit device by a master slice system to which the second embodiment of the invention is applied.

FIG. 7 is an explanatory diagram showing a manufacturing flow of a master process of an integrated circuit device by a conventional master slice method.

FIG. 8 is an explanatory diagram showing a manufacturing flow of a slice process of a conventional integrated circuit device.

9 is a plan view schematically showing a schematic configuration of the integrated circuit device of FIG.

10 is a plan pattern view schematically showing an outline of a basic cell in the integrated circuit device of FIG.

11 is a plan pattern view schematically showing a part of a basic cell row region for realizing an internal circuit in the integrated circuit device of FIG.

12 is a logic circuit diagram showing a latch circuit for holding an input signal and outputting an inverted signal in the integrated circuit device of FIG.

13 is a transistor circuit diagram showing a configuration of a latch circuit in the integrated circuit device of FIG.

FIG. 14 is a layout pattern diagram schematically showing an outline of a latch circuit including the transistor circuit of FIG.

FIG. 15 shows one P in the transistor circuit of FIG.
It is explanatory drawing which shows the resistance of a transistor part when a channel transistor turns on.

16 is a diagram illustrating one N in the transistor circuit of FIG.
It is explanatory drawing which shows the resistance of a transistor part when a channel transistor turns on.

FIG. 17 is an explanatory diagram showing the resistance of the transistor portion when four P-channel transistors connected in series in the transistor circuit of FIG. 13 are turned on.

FIG. 18 is an explanatory diagram showing the resistance of the transistor unit when four N-channel transistors connected in series in the transistor circuit of FIG. 13 are turned on.

[Explanation of symbols]

1a to 1g P-channel transistor 2a to 2g N-channel transistor 3,3a to 3h Polysilicon serving as a gate electrode of a P-channel transistor 4,4a-4h Polysilicon serving as a gate electrode of an N-channel transistor 5,5a to 5i P P-type diffusion regions 6, 6a to 6i serving as source / drain of channel transistor N-type diffusion region serving as source / drain of N-channel transistor 7a VDD wiring made of first layer aluminum 7b GND wiring made of first layer aluminum 7c 7j Signal wiring made of first layer aluminum 8a to 8e Signal wiring made of second layer aluminum 9 Contact hole for connecting polysilicon, diffusion region and first layer aluminum 10 Connecting first layer aluminum and second layer aluminum Through hole 11, 11a to 11h Transistor source voltage Pole resistance 12, 12a to 12h Transistor on-resistance 13, 13a to 13h Transistor drain electrode resistance 14 Integrated circuit device 15 Input / output buffer circuit region between internal circuit of the integrated circuit device and outside 16 Internal circuit region of integrated circuit device 17a, 17b, 17c Inverter circuit 18 Transmission gate

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 11, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

[0025] The control signal input terminal T 1 of the latch circuit, is connected to the gate terminal of the P-channel transistor 1b, and the P source terminal inside the terminal B of the channel transistor 1b, the drain terminal is inside the terminal C are respectively connected to a further, to the control signal input terminal T 2 of the latch circuit, the gate terminal of the N-channel transistor 2b is connected and to the N-channel transistor 2b source terminal inside the terminal B of the drain terminal Are respectively connected to the internal terminal C, and these P-channel transistor 1b and N-channel transistor 2 are connected.
The transmission gate 18 is formed by b.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

Next, a layout pattern for realizing the latch circuit shown in the transistor circuit of FIG. 13 is shown in FIG.
, And the details will be described. In the configuration of FIG. 14, polysilicon gates 3a, 3b, 3c, 3h , 3
g , 3f, 3e are P-channel transistors 1a, 1
b, 1c, 1d, 1e, 1f, 1g gate electrodes are respectively configured, and polysilicon gates 4a, 4b, 4c,
4d, 4e, 4f, 4g and 4h form the gate electrodes of the P-channel transistors 2a, 2b, 2c, 2d, 2e, 2f and 2g, respectively.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

[0037] As the control signal input terminal T 1, the second layer aluminum signal line 8d is formed, the second layer aluminum signal lines 8d, the through-hole 10, the first layer aluminum signal lines 7
g, polysilicon gate 3 through contact hole 9
b and connected as a control signal input terminal T 2 with a second
A layer aluminum signal wiring 8c is formed, and the second layer aluminum signal wiring 8c is connected to the polysilicon gate 4b through the through hole 10, the first layer aluminum signal wiring 7h, and the contact hole 9.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

The driving capability of the transistor in the basic cell is considered as the reciprocal of the resistance value when the transistor is turned on, and in FIG. 15, the transistor portion in the transistor portion when this one P-channel transistor is turned on is considered. is shown a resistor configuration, the resistance of the P-channel transistor portion includes a diffusion resistance R _PS 11 of the source area, the ON resistance R _PT 12 of the transistor portion, and the diffusion resistance R _PD 13 of the drain area series It is considered that they are connected, and the resistance value R _P in this case can be expressed as R _P = R _PS + R _PT + R _PD (1).

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

[0043] Similarly, in FIG. 16 is shown a resistance configuration in the transistor unit in the case where the one N-channel transistor is turned ON, the resistance of the N-channel transistor portion, the diffusion of the source area Resistance R _NS 11
When, the ON resistance R _NT 12 of the transistor unit, and the diffusion resistance R _ND 13 of the drain area is considered to have been connected in series, the resistance R _N in this _{case, R N = R NS + R} NT + R _ND It can be expressed as (2).

[Procedure Amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction content]

Then, the P-channel transistor and the N-channel
The driving capability of the inverter circuits 17a and 17b each including one channel transistor is as shown in the equation (1) and
(2) it is thought as the reciprocal of the resistance value shown in the expression. Also ,
FIG. 17 shows the resistance structure in the transistor unit in a case where four P-channel transistors turns ON.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0045

[Correction method] Change

[Correction content]

The resistance of the P-channel transistor section is
Diffusion resistance R _PS 11a of the source area, the transistor unit
ON resistance R _PT 12a, the diffusion resistance of the drain area R _PD 1 of
3a and the diffusion resistance R _PS 11b of the source area, ON resistance R _PT 12b of the transistor unit, and the diffusion resistance R _PD 13b of the drain area, the source area diffusion resistance R _PS 11c, ON resistance of the transistor unit R _PT 12c, drain area
The diffusion resistance R _PD 13c of the diffusion resistance of the source area R _PS 1
1d, ON resistance R _PT 12d of the transistor portion, and the diffusion resistance R _PD 13d of the drain area is considered to have been connected in series.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction content]

The resistance value R in this _{case, R = (R P S +} R P T + R P D) + (R P S + R P T + R P D) + (R P S + R P T + R P D) + ( R _{P S} + R _{P T} + R _{P D} ) = 4 (R _PS + R _PT + R _PD ) ... (3)

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction content]

[0047] Similarly, in FIG. 18, is shown a resistance configuration in the transistor unit in the case where the four N-channel transistor is turned ON, the resistance of the N-channel transistor portion, the diffusion of the drain area Resistance R _ND 1
3e, ON resistance of the transistor unit R _NT 12e, the diffusion resistance R _NS 11e source area, the diffusion resistance R _ND 13f of the drain area, ON resistance R _NT 12 of the transistor unit
f, and the diffusion resistance R _NS 11f of the source area, a drain area
Diffusion resistance R _ND 13 g of, ON resistance R _NT 12 g of the transistor unit, and the diffusion resistance R _NS 11g of the source area, the diffusion resistance R _ND 13h of the drain area, ON resistance R _NT 12h of the transistor part, the source territory Area diffusion resistance R _NS 11h
It is considered that and are connected in series.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0048

[Correction method] Change

[Correction content]

In this case, the resistance value R is R = (R _{N S} + R _{N T} + R _{N D} ) + (R _{N S} + R _{N T} + R _{N D} ) + (R _{N S} + R _{N T} + R _{N D} ) + ( R _{N S} + R _{N T} + R _{N D} ) = 4 (R _NS + R _NT + R _ND ) ... (4)

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0064

[Correction method] Change

[Correction content]

Further, the control signal input terminal T of this latch circuit
1 , the gate terminal of the P-channel transistor 1b is connected, the source terminal of the P-channel transistor 1b is connected to the internal terminal B, and the drain terminal of the P-channel transistor 1b is connected to the internal terminal C. the terminal T 2, the gate terminal of the N-channel transistor 2b is connected and to the N-channel transistor 2b source terminal inside the terminal B of, the drain terminal is connected to the internal terminal C, these P-channel The transmission gate 18 is configured by the transistor 1b and the N-channel transistor 2b.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Name of item to be corrected] 0072

[Correction method] Change

[Correction content]

The second layer aluminum signal wiring 8d is formed as the control signal input terminal T 1 , and the second layer aluminum signal wiring 8d is formed through the through hole 10 and the first layer aluminum signal wiring 7.
g, polysilicon gate 3 through contact hole 9
b and connected as a control signal input terminal T 2 with a second
A layer aluminum signal wiring 8c is formed, and the second layer aluminum signal wiring 8c is connected to the polysilicon gate 4b through the through hole 10, the first layer aluminum signal wiring 7f and the contact hole 9.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0073

[Correction method] Change

[Correction content]

The P-type diffusion region 5c and the N-type diffusion region 6c are
First layer aluminum signal wiring 7 h through the contact hole 9
The first-layer aluminum signal wiring 7h is connected to the polysilicon gates 3c, 4c,
And a P-type diffusion region 5g and an N-type diffusion region 6g. The P type diffusion region 5d is connected to the first layer aluminum VDD wiring 7a through the contact hole 9, and the N type diffusion region 6d is connected through the contact hole 9 to the first layer aluminum GN.
It is connected to the D wiring 7b.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0076

[Correction method] Change

[Correction content]

The driving capability of the standard transistor in the basic cell is exactly the same as that of the conventional configuration described above, and the P-channel transistors 1a, 1b and 1c and the N-channel transistors 2a, 2b and 2c are used. The resistance values when and are ON are exactly the same as in the case of the conventional configuration, and the drive capacity of the inverter circuits 17a and 17b is the same as the resistance values shown in the equations ( 1 ) and ( 2 ). Think of it as the reciprocal of. Here, P according to the first embodiment described above is used.
The channel transistor 1d and the N-channel transistor 2d will be described.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0082

[Correction method] Change

[Correction content]

[0082] the resistance value R in this _{case, R = {4R P S +} (3/2) R P T} + R P T + {4R P D + (3/2) R P T} = 4 (R PS + R _PT + R _{P D} ) ... It can be expressed as (9).

[Procedure 16]

[Document name to be amended] Statement

[Correction target item name] 0084

[Correction method] Change

[Correction content]

In this case, the resistance value R is R = {4R _{N S} + (3/2) R _{N T} } + R _{N T} + {4R _{N D} + (3/2) R _{N T} } = 4 (R _NS + R _NT + R _{N D} ) ... It can be expressed as (10).

[Procedure Amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0087

[Correction method] Change

[Correction content]

That is, in the manufacturing flow of FIG.
First, for a P-type diffusion region that constitutes the source and drain of an arbitrary P-channel transistor whose drive capability is to be changed from the standard, the same conductivity type, P ( Re-ion implantation of P ⁺ ) -type impurities is performed (step, S6-01), and then this is desired for the N-type diffusion region that constitutes the source and drain of any N-channel transistor whose drive capability is to be changed from the standard. In the same manner, re-ion implantation of N (N ⁺ ) P-type impurities is performed so that the diffusion resistance value of each of these transistors is partially diffused by ion implantation of impurities of the same conductivity type. Change the resistance value of the area (step, S6-02).

[Procedure 18]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure Amendment 19]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure amendment 20]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

[Procedure correction 21]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 13

[Correction method] Change

[Correction content]

[Fig. 13]

[Procedure correction 22]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 14

[Correction method] Change

[Correction content]

FIG. 14

[Procedure amendment 23]

[Document name to be corrected] Drawing

[Correction target item name] Fig. 16

[Correction method] Change

[Correction content]

FIG. 16

Claims (2)

[Claims] 1. A master process comprising a plurality of transistors each having a diffused region serving as a source / drain set to a predetermined reference diffused resistance value and forming a diffused region of each transistor as a master process. In a configuration of an integrated circuit device by a master slice method, which is manufactured in advance, and a manufacturing process such as wiring connection of each transistor thereafter is customized as a slicing process to realize a required functional circuit, In the integrated circuit device, the diffusion resistance value of the diffusion region of the selected transistor is set to be different from the reference diffusion resistance value. 2. A plurality of transistors each having a diffused region serving as a source / drain set to a predetermined reference diffused resistance value, each of which has a plurality of transistors, and a manufacturing process up to the formation of a diffused region of each transistor is used as a master process. In a method of manufacturing an integrated circuit device by a master slice method, which is manufactured in advance, and a manufacturing process such as wiring connection in each transistor after that is customized as a slice process to realize a required functional circuit, the master process A slicing step after completion, including a manufacturing step of changing a diffusion resistance value of a diffusion region in a selected transistor among the plurality of transistors with respect to the reference diffusion resistance value. Method of manufacturing circuit device.