JPH04372168A - Forming method for layout pattern data - Google Patents

Abstract

PURPOSE:To provide a gate separation type gate array having high integration. CONSTITUTION:When basic cells of the same potential cells types are disposed adjacently in a boundary of two cells so disposed adjacently by a first disposition, the cells are so redisposed that the basic cells are superposed by a second disposition. Cell layout pattern data of an unnecessary part of the superposed basic cells is removed by preprocessing. Accordingly, the number of gates to be placed can be increased, a layout efficiency is improved, and an integrated circuit having high integration is obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the layout of integrated circuit devices, and more particularly to the layout of integrated circuit devices that perform gate isolation.

0002

[Prior art] In recent years, the cycles of electrical products have become shorter,
In line with differentiation from other companies' products, there are increasing demands for integrated circuit devices to shorten development periods, lower development costs, and realize unique functions for users. In order to meet these demands, there is a gate array integrated circuit device in which the steps up to the step of forming a diffusion region are common to all integrated circuits and are manufactured in advance, and customization is achieved by connecting wiring.

FIG. 5 is a main schematic diagram showing the configuration of a gate array integrated circuit device 1 of the gate separation type. An internal gate region 3 in which circuits, flip-flops, etc. are formed is arranged in the center, and an input/output buffer circuit region 2 in which a circuit for interfacing the region 3 with the outside is formed is arranged in the periphery. There is.

FIG. 6 is a main schematic diagram showing a basic cell, which is a basic unit for realizing the internal gate region 3. As shown in FIG. As shown in the figure, a P-type diffusion region 6 and an N-type diffusion region 7 are arranged facing each other, and a gate polysilicon 4 and a gate polysilicon 5 are arranged on each diffusion region. . After the wiring process, the gate polysilicon 4 is used as a gate electrode, and P
By using the type diffusion region 6 as a source region and a drain region, one P channel transistor 8 can be constructed, and by using the gate polysilicon 5 as a gate electrode, an N
By using the type diffusion region 7 as a source region and a drain region, one N-channel transistor 9 can be constructed. As shown in FIG. 7, the internal gate region 3 in FIG. 5 is constructed by arranging a plurality of basic cells shown in FIG. 6 adjacent to each other.

The configuration of such an integrated circuit device 1 is determined in advance, and the integrated circuit device 1 is manufactured in advance up to the step of forming the diffusion region according to this configuration. By appropriately wiring the basic cells, a desired logic function can be realized.

Various gates, flip-flops, etc. that can be used to realize desired logic functions are prepared in advance as library cells. As an example of a library cell, FIG. 9 shows an inverter represented by the symbol shown in FIG. 8, and a transistor circuit having twice the normal load driving capacity.

Two P-channel transistors 8a and 8b are connected in parallel, and two N-channel transistors 9a and 9b are also connected in parallel. P channel transistor 8
The source electrodes of a and 8b are commonly connected to the power supply VDD, the gate electrodes are commonly connected to the input terminal A, and the drain electrodes are commonly connected to the output terminal Y, respectively. The source electrodes of N-channel transistors 9a and 9b are commonly connected to ground GND.
The gate electrodes are commonly connected to the input terminal A, and the drain electrodes are commonly connected to the output terminal Y.

A layout pattern diagram for realizing such a transistor circuit is formed as shown in FIG.

P-channel transistors 8a and 8, respectively.
The P-type diffusion regions 6b and 6d forming the source electrode of
0a, and each N-channel transistor 9a
, 9b forming source electrodes 7b, 7d.
is connected to the first layer aluminum GND wiring 10b via the contact hole 12.

[0010] Also, each P channel transistor 8
polysilicon 4b, 4c, 5b, 5c forming gate electrodes of a, 8b and N channel transistors 9a, 9b
is electrically connected to the first layer aluminum signal wiring 10c via the contact hole 12, and is electrically connected to the first layer aluminum signal wiring 10c.
C is electrically connected to the second layer aluminum signal wiring 11a, which constitutes a connection terminal for the input signal A, via a through hole 13.

The P-type diffusion region 6c forming the drain electrodes of the P-channel transistors 8a and 8b is connected to the first layer forming the output terminal Y via the contact hole 12, the first layer aluminum signal wiring 10d, and the through hole 13. It is electrically connected to the two-layer aluminum signal wiring 11b. The N-type diffusion region 7c forming the drain electrodes of the N-channel transistors 9a and 9b is also electrically connected to the second layer aluminum signal wiring 11b via the contact hole 12, the first layer aluminum signal wiring 10e, and the through hole 13. It is connected.

As described above, the four basic cells are wired and connected to form the inverter circuit shown in FIG. 9, and further connections are made for electrical isolation between adjacent basic cells. That is, the P type diffusion region 6a is connected to the contact hole 12.
The P-type diffusion region 6e is electrically connected to the first layer aluminum VDD wiring 10a through a contact hole 12. The N-type diffusion region 7a connects to the first layer aluminum GND wiring 1 through the contact hole 12.
0b and is separated by a polysilicon gate 5a electrically connected to the contact hole 1.
They are separated by a polysilicon gate 5d which is electrically connected to the first layer aluminum GND wiring 10b via a polysilicon gate 5d. In this way, the area occupied by the set of basic cells necessary to configure one inverter circuit shown in FIG. 9 can be represented as a cell frame 14.

When a large number of inverter circuits shown in FIG. 9 are formed in the integrated circuit device 1, their arrangement is in the cell frame 14.
This is done as follows using .

FIG. 11 is a schematic diagram of a mask data creation flow for a conventional gate array integrated circuit device.

First, the user designs a logic using symbols as shown in FIG. 8 to realize a desired function. Based on the logical connection information that is the logical design result, placement and wiring data is placed on the integrated circuit device 1 shown in FIG. This placement and wiring data is stored in cell frame 1 as shown in FIG.
4, terminal position information 15 indicating the position of the input terminal A, and terminal position information 16 indicating the position of the output terminal Y.

The cell frames 14 are arranged adjacent to each other or close to each other with an interval that is an integral multiple of the basic cell. For example, FIG. 13 shows a case where the cell frames 14 shown in FIG. 12 are arranged adjacently. Next, wiring between the cells arranged in this manner is performed. Furthermore, each cell frame 14 is defined by cell layout pattern data stored in the cell library (for example, FIG.
0 (wiring and connection data inside the cell frame 14). For example, two cell frames 1 shown in FIG.
4 are given the cell layout pattern data shown in FIG. 10, respectively, and the layout pattern data shown in FIG. 13 is replaced with the layout pattern data shown in FIG. Then, mask pattern data for a customized manufacturing process is created for this layout pattern data. In this manner, the conventional gate array integrated circuit device using the gate isolation method uses seven basic cells to realize two inverter circuits with twice the standard load driving capacity.

[0017]

[Problems to be Solved by the Invention] However, in the conventional gate array integrated circuit device using the gate isolation method, gate isolation is always performed at the boundary of the cell frame 14, which poses the problem of increasing the area required for layout. there were. For example, in the layout pattern shown in FIG. 14, gate polysilicon 4d electrically isolates two P-type diffusion regions 6d and 6e in left cell frame 14. However, the P-type diffusion region 6e belonging to the left cell frame 14 also serves as a part of the P-type diffusion region 6b belonging to the right cell frame 14, and has the same potential as this. Moreover, cell frame 1 on the right
The P type diffusion region 6b belonging to No. 4 is connected to the first layer aluminum VDD wiring 10a and has the same potential as the left P type diffusion region 6d. Therefore, originally P type diffusion regions 6d, 6e
need not be electrically isolated from each other. Further, there is no need to provide the P-type diffusion region 6e. Even if there are diffusion regions with the same potential on both sides of the cell isolation gate, a layout area is required for each diffusion region, so it is necessary to occupy a large layout area to achieve the same function. However, there is a problem in that the number of multifunctional cells, that is, the number of circuits mounted on an integrated circuit device is reduced.

The present invention has been made in order to solve the above-mentioned problems, and its purpose is to increase the number of circuits that can be mounted, that is, to obtain a gate array integrated circuit device of a gate separation type with a high degree of integration. shall be.

[0019]

[Means for Solving the Problems] A method for creating layout pattern data of the present invention provides (a) a unit of logical function constituted by a plurality of basic cells, and a unit for electrically separating the unit; Using placement and wiring data having a cell frame indicating the area occupied by other basic cells provided in the vicinity of the unit, and information regarding the positions of input terminals, output terminals, power supply wiring, and basic cells inside the cell frame. , arranging the cell frames in close proximity; (b) the step (a);
(c) determining whether the condition that similar potentials are applied to the other neighboring basic cells belonging to mutually different cell frames of the neighboring cell frames is satisfied, and (c) the step ( If the condition in b) is satisfied, the other adjacent basic cells are overlapped,
Rearranging the adjacent cell frames, (d) the step (c)
Unit layout pattern data having information regarding the positions of wiring and connections inside the cell frame is provided to each of the cell frames arranged in the steps up to, to obtain layout pattern data, and (e) the step (c) ) on the layout pattern data, the wiring and connections of the other basic cells overlapped by the above are removed.

[0020]

[Operation] In the present invention, when the same potential is applied to the basic cells for electrically isolating one unit of logic function that are adjacent to each other near the boundaries of adjacent cell frames, It is not necessary to electrically separate the cell frames that are connected to each other. Therefore, basic cells for electrical isolation are removed from the layout pattern data, and the cell frames are rearranged so that they overlap.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic diagram of a mask data creation flow for a gate isolation type gate array integrated circuit device according to an embodiment of the present invention. The user designs logic using symbols such as those shown in FIG. 8 to realize a desired function. Based on the logical connection information that is the logical design result, placement and wiring data as shown in FIG. 12 is placed on the integrated circuit device 1 shown in FIG. This arrangement of cells is performed twice: a first arrangement and a second arrangement.

First, in the first arrangement, similar to the conventional arrangement of cells, the cell frames 14 are arranged adjacent to each other or close to each other at intervals of an integral multiple of the basic cells. Since this first arrangement is similar to the conventional cell arrangement, the arrangement result is also the same. Therefore, the execution result of the first arrangement is the same as the arrangement execution result in the conventional case shown in FIG.

Next, in the second arrangement, as a result of the first arrangement, the cells are arranged adjacent to each other on the left and right, and the diffusion region on the left side of the cell isolation gate on the right side of the cell arranged on the left side and the diffusion region on the right side If both the cell isolation gate on the left side of the placed cell and the diffusion region on the right side are electrically connected to a power source of the same potential, rearrange them by overlapping one basic cell as shown in Figure 2. . The placement and wiring data also includes the power supply wiring pattern as information, and since the basic cells have the same shape within any cell frame, such rearrangement is possible. Region C indicates an overlapping portion.

For example, when cells having cell layout pattern data as shown in FIG. 10 are arranged adjacent to each other, the P-type diffusion regions 6d, 6a and the gate polysilicon 4d in the cell on the left in FIG. Since the P-type diffusion regions 6e and 6b in the cell on the right side are all at the same potential, even if one basic cell constituted by the gate polysilicon 4d in the cell on the left side is placed one above the other, it will not affect the overall operation. will not be given.

After that, automatic wiring between cells is performed based on this placement result. The placement and wiring data in this automatic wiring result is replaced with cell layout pattern data in the cell library in the same way as in the conventional case.

Next, the set of cell layout pattern data in which the cells have been rearranged as described above is subjected to preprocessing, and the cell layout pattern data in the overlapping portion is removed. For example, as a result of the second arrangement shown in FIG. 2, when replacing the cell placed on the left with the cell layout pattern shown in FIG. 10, the P-type diffusion region 6e in FIG. contact holes 12 for electrically connecting the region 7e, the cell isolation gates 4d and 5d, and the isolation gates 4d and 5d to the first layer aluminum VDD wiring 10a and the first layer aluminum GND wiring 10b, respectively;
1st layer aluminum VDD wiring 10a and 1st layer aluminum GND
This is a portion where the wiring 10b is extended to connect with the isolation gates 4d and 5d, respectively. Furthermore, when replacing the cell placed on the right side with the cell layout pattern shown in FIG. 10, the P-type diffusion region 6a in FIG.
, the N-type diffusion region 7a, the cell isolation gates 4a and 5a, and the isolation gates 4a and 5a are connected to the first layer aluminum VDD wiring 10a.
and a contact hole 12 for electrically connecting to the first layer aluminum GND wiring 10b and the first layer aluminum VD.
This is a portion where the D wiring 10a and the first layer aluminum GND wiring 10b are extended to connect with the isolation gates 4a and 5a, respectively.

FIG. 3 shows a layout pattern diagram obtained after completing these pre-processes. As can be seen from this figure, according to this embodiment, by using six basic cells in a gate array integrated circuit device using a gate separation method, an inverter circuit with two load driving capabilities twice that of the standard one can be realized. be able to.

Returning to FIG. 1, mask pattern data is then created for the layout pattern of the customized manufacturing process.

In the above embodiment, the case where the second arrangement is executed when the result of the first arrangement is that two cells are adjacent to each other as shown in FIG. 13 has been described. , as shown in FIG. 4, the second arrangement may be performed in the case where the cells are arranged close to each other with an interval that is an integral multiple of the basic cells, and the same effect as in the above embodiment can be obtained.

[0030]Although in the above embodiment, the cells arranged adjacent to each other are the same cell, even in the case of different cells, the basic cells for electrical isolation may have the same potential. As long as it is given, the same effect as the above embodiment can be achieved.

[0031]

[Effects of the Invention] As described above, in the layout data creation method of the present invention, when the same potential is applied to adjacent isolation basic cells in cell arrangement, the basic cells are rearranged so that they overlap. , the number of mountable gates can be increased, layout efficiency can be improved, and an integrated circuit device with a high degree of integration can be obtained.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a mask data creation flow for a gate isolation type gate array semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the cell placement results of FIG. 11 according to an embodiment of the present invention.

FIG. 3 is a diagram showing a layout pattern resulting from placement according to an embodiment of the present invention.

FIG. 4 is a main schematic diagram showing the configuration of a gate array integrated circuit device of a gate separation type.

FIG. 5 is a main schematic diagram showing the configuration of a gate isolation type gate array integrated circuit device.

FIG. 6 is a main schematic diagram showing a basic cell.

FIG. 7 is a main schematic diagram showing a part of a basic cell column region for realizing the internal circuit of a gate array integrated circuit device.

FIG. 8 is a symbol diagram of an inverter circuit with twice the load driving capacity.

FIG. 9 is a transistor circuit diagram of an inverter circuit with twice the load driving capacity.

FIG. 10 is a main schematic diagram of a layout pattern of an inverter circuit with twice the load driving capacity.

FIG. 11 is a schematic diagram of a mask data creation flow for a conventional gate array integrated circuit device.

FIG. 12 is a diagram showing placement and wiring data for the cell shown in FIG. 10;

FIG. 13 is a diagram showing a conventional placement result of the cells in FIG. 11;

FIG. 14 is a diagram showing a layout pattern of the conventional arrangement result shown in FIG. 13;

[Explanation of symbols]

1 Integrated circuit devices 4a, 4d P-channel transistor gate polysilicon 5a, 5d N-channel transistor gate polysilicon 6e P-type diffusion region 7e N-type diffusion region 10a 1st layer aluminum VDD wiring 10b 1st layer aluminum GND wiring 12 Contact Hall 14 cell frame

Claims (1)

[Claims] Claim 1: (a) A unit of logical function constituted by a plurality of basic cells, and an area occupied by another basic cell provided in the vicinity of the unit to electrically isolate the unit. (b) arranging the cell frames in close proximity using layout and wiring data having a cell frame shown and information regarding the positions of input terminals, output terminals, power supply wiring, and basic cells inside the cell frame; ) Determining whether or not the condition that similar potentials are applied to the other adjacent basic cells belonging to different cell frames in the adjacent cell frames in the step (a) is satisfied. (c) if the conditions in step (b) are satisfied, rearranging the adjacent cell frames so as to overlap the other adjacent basic cells; (d)
a step of obtaining layout pattern data by providing unit layout pattern data having information regarding the positions of wiring and connections inside the cell frame to each of the cell frames arranged in the steps up to step (c);
e) A method for creating layout pattern data, comprising the step of removing, on the layout pattern data, the wiring and connections of the other basic cells overlapped in the step (c).