JP2004140133A - Semiconductor integrated circuit and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To integrate a multitude of circuits in one chip without complicating a manufacturing process, in a semiconductor integrated circuit comprising a plurality of circuit blocks having different manufacturing processes such as an analog circuit, a logic circuit, a memory circuit or the like. <P>SOLUTION: The semiconductor integrated circuit is equipped with a semiconductor substrate 1, a first circuit block 10 comprising an impurities diffusion layer formed on the first surface of the semiconductor substrate employing a first manufacturing process, an insulating film and a conductor film, and a second circuit block 20 comprising another impurities diffusion layer formed on the second surface of the semiconductor substrate employing a second manufacturing process different from the first manufacturing process, another insulating film and another conductive film. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a plurality of circuit blocks having different manufacturing processes, such as an analog circuit, a logic circuit, and a memory circuit. Further, the present invention relates to a method for manufacturing such a semiconductor integrated circuit.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, when a semiconductor integrated circuit including a plurality of circuit blocks having different manufacturing processes is manufactured, the plurality of circuit blocks are separated into separate semiconductor substrates (hereinafter, also referred to as “chips”) in order to simplify each manufacturing process. ) And mounting these chips in one package.
[0003]
In the case of manufacturing a large-scale semiconductor integrated circuit, the size of a chip is restricted due to reasons such as exposure accuracy in the manufacturing process. Therefore, a single chip cannot constitute the entire system. A system has been constructed using these chips, and these chips have been mounted in one package.
[0004]
As described above, in order to manufacture a semiconductor integrated circuit by mounting a plurality of chips in one package, wiring between these chips is performed by wire bonding or through a packaged substrate such as a lead frame. In this case, a method of realizing an apparent one-chip by wiring is used.
[0005]
However, according to such a conventional method, the wiring between chips must be changed depending on the type of the system, so that the manufacturing process becomes complicated. Also, since the number of wires between chips is expected to increase as the scale of the system increases, a large area is required for pads used for wires between chips.
[0006]
Meanwhile, Patent Document 1 below discloses that a CMOS transistor including an N-channel transistor and a P-channel transistor is formed on each of the chips on the front surface and the back surface of the wafer. However, as shown in FIG. 2 of Patent Document 1, the structure of the front surface and the back surface of the wafer is completely the same, and a plurality of circuit blocks having different manufacturing processes such as analog circuits, logic circuits, and memory circuits are used. It cannot be accumulated.
[0007]
[Patent Document 1]
Japanese Utility Model Laid-Open Publication No. 4-88058 (page 1, FIG. 2)
[0008]
[Problems to be solved by the invention]
In view of the above, the present invention provides a semiconductor integrated circuit including a plurality of circuit blocks having different manufacturing processes such as an analog circuit, a logic circuit, and a memory circuit without complicating the manufacturing process. The purpose is to integrate many circuits on a chip.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit according to the present invention includes a semiconductor substrate and an impurity diffusion layer, an insulating film, and a conductive film formed on a first surface of the semiconductor substrate by using a first manufacturing process. And a second circuit including an impurity diffusion layer, an insulating film, and a conductive film formed on a second surface of the semiconductor substrate using a second manufacturing process different from the first manufacturing process. And a block.
[0010]
The semiconductor integrated circuit includes a plurality of input / output pads formed on a surface of the first circuit block and the second circuit block on which the smaller area is formed, through an opening formed in the semiconductor substrate. And a wiring formed for electrically connecting the first circuit block and the second circuit block. The semiconductor integrated circuit may further include a package on which the semiconductor substrate is mounted, and a plurality of pins fixed to the package and electrically connected to the first and second circuit blocks. In the above, the first circuit block is one of an analog circuit, a logic circuit, and a memory circuit, and the second circuit block is another one of an analog circuit, a logic circuit, and a memory circuit. You may do it.
[0011]
In the method for manufacturing a semiconductor integrated circuit according to the present invention, a first circuit block including an impurity diffusion layer, an insulating film, and a conductive film is formed on a first surface of a semiconductor substrate by using a first manufacturing process. (A), a second circuit block including an impurity diffusion layer, an insulating film, and a conductive film is formed on a second surface of a semiconductor substrate by using a second manufacturing process different from the first manufacturing process. Step (b).
[0012]
Step (a) or (b) includes, through an opening formed in the semiconductor substrate, a plurality of input / output terminals on a surface of the first circuit block and the second circuit block on which the smaller area is formed. The method may include a step of forming a pad and a step of forming a wiring for electrically connecting the first circuit block and the second circuit block. The manufacturing method may further include a step of mounting the semiconductor substrate on a package and electrically connecting a plurality of pins fixed to the package to the first and second circuit blocks. In the above, the first circuit block is one of an analog circuit, a logic circuit, and a memory circuit, and the second circuit block is another one of an analog circuit, a logic circuit, and a memory circuit. You may do it.
[0013]
According to the present invention, in a semiconductor integrated circuit including a plurality of circuit blocks having different manufacturing processes such as an analog circuit, a logic circuit, and a memory circuit, different manufacturing processes are used on both surfaces of one semiconductor substrate (chip). Since different circuit blocks are formed, many circuits can be integrated on one chip without complicating the manufacturing process.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the same elements are denoted by the same reference numerals, and description thereof will be omitted.
FIG. 1 is a plan view of a semiconductor substrate used in a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 1A shows a first surface of the semiconductor substrate, and FIG. 1B shows a second surface of the semiconductor substrate.
[0015]
As shown in FIG. 1, a circuit block 10 is formed on a first surface of a semiconductor substrate 1, and a circuit block 20 is formed on a second surface of the semiconductor substrate 1. Here, the circuit block 10 and the circuit block 20 are formed using different manufacturing processes. For example, the circuit block 10 is one of an analog circuit, a logic circuit, and a memory circuit, and the circuit block 20 is another one of an analog circuit, a logic circuit, and a memory circuit. In the following, a description will be given assuming that the circuit block 10 is a large-scale memory circuit (DRAM) and the circuit block 20 is a logic circuit.
[0016]
As shown in FIG. 1, a plurality of openings 2 are formed in the semiconductor substrate 1, and the circuit block 10 and the circuit block 20 are electrically connected through these openings. The area of the circuit block 10 formed on the first surface of the semiconductor substrate 1 is larger than the area of the circuit block 20 formed on the second surface of the semiconductor substrate 1. Therefore, by arranging a plurality of input / output pads 3 which require a large size to connect to the pins of the semiconductor integrated circuit on the second surface of the semiconductor substrate 1, the area of the semiconductor substrate 1 can be reduced as a whole. Can be.
[0017]
FIG. 2 is a partial cross-sectional view of the semiconductor integrated circuit according to the present embodiment. As shown in FIG. 2, a gate electrode 12 made of a conductive film such as polysilicon is formed on a first surface of the semiconductor substrate 1 via a gate insulating film 11 such as a silicon oxide film. In the semiconductor substrate 1 on both sides of the gate insulating film 11 and the gate electrode 12, impurity diffusion layers 13 serving as a source and a drain are formed. The gate insulating film 11, the gate electrode 12, and the impurity diffusion layer 13 constitute a MOS transistor 101 for storing data in a capacitor 102 in a DRAM memory cell.
[0018]
Further, on the first surface of the semiconductor substrate 1, an interlayer insulating film 14 and wiring layers 15 and 16 made of a conductive film such as aluminum are formed. Wiring layer 15 is connected to impurity diffusion layer 13 via a via hole formed in interlayer insulating film 14. In some regions, the wiring layers 15 and 16 are used as a lower electrode 15a and an upper electrode 16a sandwiching a dielectric film 17, which is a thin insulating film. The lower electrode 15a, the dielectric film 17, and the upper electrode 16a constitute a capacitor 102 for storing data in a DRAM memory cell. Further, on the first surface of the semiconductor substrate 1, an interlayer insulating film 18 and a wiring layer 19 made of a conductive film such as aluminum are formed.
[0019]
On the other hand, on the second surface of the semiconductor substrate 1, a gate electrode 22 made of a conductive film such as polysilicon is formed via a gate insulating film 21 such as a silicon oxide film. In the semiconductor substrate 1 on both sides of the gate insulating film 21 and the gate electrode 22, impurity diffusion layers 23 serving as a source and a drain are formed. The gate insulating film 21, the gate electrode 22, and the impurity diffusion layer 23 constitute an output MOS transistor 201 in an input / output cell of a logic circuit.
[0020]
Further, on the second surface of the semiconductor substrate 1, an interlayer insulating film 24 and a wiring layer 25 made of a conductive film such as aluminum are formed. Wiring layer 25 is connected to impurity diffusion layer 23 through a via hole formed in interlayer insulating film 24. Further, an interlayer insulating film 26 and a wiring layer 27 made of a conductive film such as aluminum are formed on the second surface of the semiconductor substrate 1. In some regions, the wiring layer 27 is used as the input / output pad 3. The input / output pad 3 is connected to a pin 5 fixed to a package 4 via a bump (conductive projection medium for electrode connection) 6.
[0021]
The memory circuit formed on the first surface of the semiconductor substrate 1 and the logic circuit formed on the second surface of the semiconductor substrate 1 are formed by wiring filled in openings (through holes) 2 formed in the semiconductor substrate 1. The layers 15 and 25 are connected by a conductive film. In the case where the number of wiring layers is insufficient in each circuit, more wiring layers may be provided.
[0022]
The memory circuit formed on the first surface of the semiconductor substrate 1 includes a large number of DRAM memory cells, and the MOS transistor 101 included in each memory cell is miniaturized. That is, in the MOS transistor 101, the gate insulating film 11 and the gate electrode 12 are formed thin and small, and the source / drain 13 is formed shallow and small. In some regions, the capacitor 102 is formed by providing the dielectric film 17 between the wiring layer 15 and the wiring layer 16. On the other hand, in an input / output cell of a logic circuit formed on the second surface of the semiconductor substrate 1, a high-output MOS transistor 201 is used. That is, in the MOS transistor 201, the gate insulating film 21 and the gate electrode 22 are formed to be thick and large, and the source / drain 13 is formed to be deep and large. Due to such a difference in the structure of the device, the memory circuit formed on the first surface of the semiconductor substrate 1 and the logic circuit formed on the second surface of the semiconductor substrate 1 are formed using different manufacturing processes. Is done.
[0023]
Next, a method for manufacturing a semiconductor integrated circuit according to one embodiment of the present invention will be described with reference to FIGS. 3 and 4 are flowcharts showing a method for manufacturing a semiconductor integrated circuit according to one embodiment of the present invention.
[0024]
As shown in FIG. 3, first, in step S1, an opening (through hole) is formed at a predetermined position in the semiconductor substrate 1. Next, in step S2, an insulating film to be the gate insulating film 11 is formed on the first surface of the semiconductor substrate 1. Further, in step S3, a conductive film such as polysilicon is formed on the insulating film, and the insulating film and the conductive film are etched to form the gate insulating film 11 and the gate electrode 12. In step S4, impurities are implanted while masking the semiconductor substrate 1 while leaving a part of the region, so that the impurity diffusion layers serving as the source and drain are formed in the semiconductor substrate 1 on both sides of the gate insulating film 11 and the gate electrode 12. 13 is formed. The MOS transistor 101 in the memory cell of the DRAM is constituted by the gate insulating film 11, the gate electrode 12, and the impurity diffusion layer 13 thus formed.
[0025]
In step S5, the interlayer insulating film 14 is formed on the first surface of the semiconductor substrate 1, and in step S6, the wiring layer 15 including the lower electrode 15a is pattern-formed on the interlayer insulating film 14. In step S7, the dielectric film 17 is patterned on the lower electrode 15a, and in step S8, the wiring layer 16 including the upper electrode 16a is patterned on the dielectric film 17 or the lower electrode 15a. The lower electrode 15a, the dielectric film 17, and the upper electrode 16a thus formed form a capacitor 102 in a DRAM memory cell. Further, in step S9, an interlayer insulating film 18 is formed on the first surface of the semiconductor substrate 1, and in step S10, a wiring layer 19 is pattern-formed on the interlayer insulating film 18. In the above steps S2 to S10, the first semiconductor manufacturing process is used.
[0026]
On the other hand, as shown in FIG. 4, in step S11, an insulating film to be the gate insulating film 21 is formed on the second surface of the semiconductor substrate 1. Further, in step S12, a conductive film such as polysilicon is formed on the insulating film, and the insulating film and the conductive film are etched to form the gate insulating film 21 and the gate electrode 22. In step S13, impurities are implanted while masking the semiconductor substrate 1 while leaving a part of the region, so that an impurity diffusion layer serving as a source and a drain is formed in the semiconductor substrate 1 on both sides of the gate insulating film 21 and the gate electrode 22. 23 are formed. The MOS transistor 201 in the input / output cell of the logic circuit is constituted by the gate insulating film 21, the gate electrode 22, and the impurity diffusion layer 23 thus formed.
[0027]
In step S14, an interlayer insulating film 24 is formed on the second surface of the semiconductor substrate 1, and in step S15, a wiring layer 25 is patterned on the interlayer insulating film 24. Further, in step S16, an interlayer insulating film 26 is formed on the second surface of the semiconductor substrate 1, and in step S17, the wiring layer 17 including the input / output pads 3 is pattern-formed on the interlayer insulating film 26. In the above steps S11 to S17, the second semiconductor manufacturing process is used. Thereafter, in step S18, the semiconductor substrate 1 is mounted on the package 4, and the input / output pads 3 are connected to the pins 5 fixed to the package 4 using the bumps 6.
[0028]
Thus, by connecting the circuits formed on both surfaces of one semiconductor substrate via through holes, and connecting the input / output pads formed on one surface of the semiconductor substrate and the pins of the semiconductor device using bumps, Wiring by wire bonding or wiring via a packaged substrate such as a lead frame becomes unnecessary.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor substrate used in one embodiment of the present invention.
FIG. 2 is a partial cross-sectional view of a semiconductor integrated circuit according to one embodiment of the present invention.
FIG. 3 is a first half of a flowchart showing a manufacturing method according to an embodiment of the present invention.
FIG. 4 is a second half of a flowchart showing a manufacturing method according to an embodiment of the present invention.
[Explanation of symbols]
Reference Signs List 1 semiconductor substrate, 2 opening, 3 input / output pad, 4 package, 5 pin, 6 bump, 10, 20 circuit block, 11, 21 gate insulating film, 12, 22 gate electrode, 13, 23 impurity diffusion layer, 14, 18 , 24, 26 interlayer insulating film, 15, 16, 19, 25, 27 wiring layer, 17 dielectric film, 101 memory cell MOS transistor, 102 memory cell capacitor, 201 input / output cell MOS transistor

Claims (8)

A semiconductor substrate;
A first circuit block including an impurity diffusion layer, an insulating film, and a conductive film formed on a first surface of the semiconductor substrate using a first manufacturing process;
A second circuit block including an impurity diffusion layer, an insulating film, and a conductive film formed on a second surface of the semiconductor substrate using a second manufacturing process different from the first manufacturing process;
A semiconductor integrated circuit comprising: A plurality of input / output pads formed on a surface on which the smaller area of the first circuit block and the second circuit block is formed;
A wiring formed to electrically connect the first circuit block and the second circuit block through an opening formed in the semiconductor substrate;
The semiconductor integrated circuit according to claim 1, further comprising: A package on which the semiconductor substrate is mounted;
A plurality of pins fixed to the package and electrically connected to the first and second circuit blocks;
3. The semiconductor integrated circuit according to claim 1, further comprising: The first circuit block is one of an analog circuit, a logic circuit, and a memory circuit, and the second circuit block is another one of an analog circuit, a logic circuit, and a memory circuit. The semiconductor integrated circuit according to claim 1. (A) forming a first circuit block including an impurity diffusion layer, an insulating film, and a conductive film on a first surface of a semiconductor substrate by using a first manufacturing process;
Forming a second circuit block including an impurity diffusion layer, an insulating film, and a conductive film on a second surface of the semiconductor substrate by using a second manufacturing process different from the first manufacturing process (b). When,
A method for manufacturing a semiconductor integrated circuit comprising: Step (a) or (b)
Forming a plurality of input / output pads on a surface on which the smaller area of the first circuit block and the second circuit block is formed;
6. A step of forming a wiring for electrically connecting the first circuit block and the second circuit block through an opening formed in the semiconductor substrate. Of manufacturing a semiconductor integrated circuit. 7. The semiconductor integrated circuit according to claim 5, further comprising: mounting the semiconductor substrate on a package; and electrically connecting a plurality of pins fixed to the package to the first and second circuit blocks. Production method. The first circuit block is one of an analog circuit, a logic circuit, and a memory circuit, and the second circuit block is another one of an analog circuit, a logic circuit, and a memory circuit. A method for manufacturing a semiconductor integrated circuit according to claim 5.

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