JPH04107964A - Semiconductor ic device - Google Patents

Abstract

PURPOSE:To perform wiring processing without being influenced by of a diffusion layer so as to shorten a process by preparing the separately manufactured diffusion layer and a wiring layer for electrically connecting these. CONSTITUTION:A chip 1 where only a diffusion layer is formed and a chip 2 where only a wiring layer is formed are individually manufactured. These chips 1, 2 are provided with electrodes 3 for connection respectively. A pad 4 for wire bonding is provided around the chip 2 only provided with the wiring layer. Next, these electrodes 3 for connection are melted and the diffusion layer and the wiring layer are electrically connected. The pad 4 for wire bonding is bonded with a connector wire 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and more specifically, to a semiconductor integrated circuit device in which a diffusion region and a wiring region are separately manufactured and bonded and integrated. The present invention relates to integrated circuit devices.

[Conventional technology]

Conventional semiconductor integrated circuit devices (hereinafter referred to as ICs) are generally manufactured by forming a diffusion region on a substrate by diffusion technology or ion implantation technology, and then forming contact holes through an interlayer insulating film, for example, in order to form a first layer. Then, a wiring region consisting of a second layer of aluminum wiring is formed to form an IC including these diffusion regions and wiring regions.

In addition, examples of documents describing the manufacturing method of the IC include:
Written by Yasuo Tarui, published by Ohmsha Co., Ltd. on March 20, 1981.
Examples include VLSI technology JP 355-415.

[Problem to be solved by the invention]

However, when a wiring region (wiring layer) is formed on a diffusion region (diffusion layer) in this way, various problems arise in the wiring processing due to the influence of the step difference in the diffusion layer. Since the formation of the wiring layer is started after the formation of the wiring layer, there is a drawback that the process takes a long time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technology that eliminates the drawbacks of the prior art, enables wiring processing without being affected by the step difference in the diffusion layer, and shortens the process.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In the present invention, instead of forming a wiring layer on the diffusion layer following the diffusion layer as in the conventional method, the diffusion layer and the wiring layer are made separately, and these are electrically connected. Make it.

[Effect]

In this way, since the diffusion layer and wiring layer are manufactured separately,
The formation of the wiring layer is less affected by the diffusion layer, and when necessary, for example, a chip with a diffusion layer and a chip with a wiring layer can be bonded and electrically connected to form an integrated chip. Because you only have to do it, you can shorten the process.
The period required for manufacturing an IC can be shortened.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

As shown in FIG. 1, a chip 1 having only a diffusion layer formed thereon and a chip 2 having only a wiring layer formed thereon are separately manufactured.

Connecting electrodes 3 are formed on these chips 1 and 2, respectively.

Wire bonding pads 4 are provided around the chip 2 on which only a wiring layer is formed.

As shown in FIG. 1, these connection electrodes 3 are melted,
Electrical connection is made between the diffusion layer and the wiring layer.

Connector wire 5 is attached to wire bonding pad 4.
wire bonding.

FIG. 3 shows a cross section of the main parts of these chips 1 and 2.

In the chip 1 in which only a diffusion layer is formed, a P-type well is formed in an N-type semiconductor substrate 6.

An N+ type semiconductor region 8 is formed in the P type well.

These N+ type semiconductor regions 8 are separated by a field insulating film 9.

Formation of the N+ type semiconductor region 8 and the like can be performed by well-known ion implantation or diffusion techniques.

The N+ type semiconductor region 8 is electrically connected to the connection electrode 3.

The field insulating film 9 is made of, for example, a 5i02 film.

The connection electrode 3 is made of, for example, a polysilicon layer.

The chip 2 on which only the wiring layer is formed is formed by forming an aluminum wiring (AQ-2) 12 on a semiconductor substrate 10 via an insulating film 11.
form. Further, an aluminum wiring (A Q -1) 14 is formed via an interlayer insulating film 13. Protective film 1
A contact hole is formed in 5, and aluminum wiring (A
Q-1)14. ! = Forming a conductive connection electrode 3.

As shown in FIG. 1, these chips 1 and 2 are attached and electrically connected via connection electrodes 3 and 3.

FIG. 2 shows another embodiment of the invention. This example is
Connection electrodes 3 are provided on both surfaces of a chip 1 on which only a diffusion layer is formed.

A chip on which only a wiring layer is formed has an upper wiring and a lower wiring.

A wire bonding pad 4 is provided on the front surface of the chip 2A having upper wiring, and a connection electrode 3 for connection to the chip 1 on which only a diffusion layer is formed is provided on the back surface thereof.

A connection electrode 3 for connection to the chip 1 on which only a diffusion layer is formed is provided on the surface of the chip 2B having the lower wiring.

A chip 2A having an upper wiring and a chip 2B having a lower wiring are adhered and connected to both sides of the chip 1 with the chip 1 having only a diffusion layer formed thereon in the same manner as shown in FIG.

The chip 1.2 according to the present invention is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A specific example of the circuit element is, for example, a MOS transistor, and these circuit elements form the circuit functions of, for example, a logic circuit and a memory.

According to the present invention, the chip 2 on which only the wiring region is formed and the chip 1 on which only the diffusion region is formed can be manufactured separately, and these can be attached as appropriate, so that the process is shortened and the wiring The region is less affected by steps in the diffusion region.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

According to the present invention, the wiring region is not affected by the step difference in the diffusion region, and the assembly process of the semiconductor integrated circuit device is shortened.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the invention, FIG. 2 is a sectional view showing another embodiment of the invention, and FIG. 3 is a configuration diagram showing another embodiment of the invention. 1. Semiconductor integrated circuit device component in which a diffusion region is formed;
2.--Semiconductor integrated circuit device component forming wiring region, 3. Connection electrode, 4. Wire bonding pad, 5.. Connector wire, 6. Semiconductor substrate, 7. Well, 8.. Diffusion region, 9 Field insulating film, 10. Semiconductor substrate, 11. Insulating film, 12. Aluminum wiring,
13... Interlayer insulating film, 14... Aluminum wiring, 1
5...Protective film. Figure 1 Figure 3 ＼ Figure 2

Claims (1)

[Claims] 1. One semiconductor component having a plurality of semiconductor regions formed on its main surface and another semiconductor component having wiring formed on its main surface are attached, and the semiconductor region and the wiring are bonded together. 1. A semiconductor integrated circuit device comprising: electrically connected to each other. 2. The semiconductor integrated circuit device according to claim 1, wherein both of the structural members are provided with connection electrodes for electrically connecting the semiconductor region and the wiring.