JP2007123407A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2007123407A
JP2007123407A JP2005311257A JP2005311257A JP2007123407A JP 2007123407 A JP2007123407 A JP 2007123407A JP 2005311257 A JP2005311257 A JP 2005311257A JP 2005311257 A JP2005311257 A JP 2005311257A JP 2007123407 A JP2007123407 A JP 2007123407A
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forming
bump
seed layer
pad
liquid metal
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Tetsuya Naito
哲也 内藤
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Renesas Technology Corp
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Renesas Technology Corp
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract

<P>PROBLEM TO BE SOLVED: To provide the technology to realize flatness of a surface of bump. <P>SOLUTION: A seed layer 31 having a flat surface shape is formed by coating a liquid metal compound on a barrier layer 30 that has been formed for electrical connected with a pad 7 formed of a conductive film of the same layer as the uppermost wiring layer, and then reducing this liquid metal compound to a single metal film. Thereafter, a bump 8 having the flat surface shape is formed on the seed layer 31 with the plating method by tracing the flat surface shape of the seed layer 31. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置の製造技術に関し、特に、ＬＣＤ（Liquid Crystal Display）ドライバの突起状の接続電極、いわゆるバンプの形成方法に適用して有効な技術に関するものである。   The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique that is effective when applied to a method of forming a projection connection electrode of a LCD (Liquid Crystal Display) driver, a so-called bump.

バンプ電極上面の平坦性を向上させるためにバンプ形成部から離れた位置においてビアホールを形成し、バンプ下部にはビアホールを形成しない技術が開示されている（たとえば特許文献１、２参照）。   In order to improve the flatness of the upper surface of the bump electrode, a technique is disclosed in which a via hole is formed at a position away from the bump forming portion and no via hole is formed under the bump (see, for example, Patent Documents 1 and 2).

また、半導体基板上のパッド電極上に保護絶縁膜を形成し、その保護絶縁膜に複数の小さな開口部を設けた後に複数の開口部を介してパッド電極に接続するようにバンプ電極をメッキ成長させることにより、バンプ電極上面の凹凸差を小さくして外部リードとの接続性を向上させる技術が開示されている（たとえば特許文献３、４参照）。   In addition, a protective insulating film is formed on the pad electrode on the semiconductor substrate, and a plurality of small openings are provided in the protective insulating film, and then bump electrodes are grown so as to be connected to the pad electrode through the plurality of openings. Thus, a technique for reducing the unevenness difference on the upper surface of the bump electrode and improving the connectivity with the external lead is disclosed (for example, see Patent Documents 3 and 4).

また、基板上にマスク材を形成し、開口部を埋めるようにバンプ用金属を埋め込んだ後に表面を所定量削って上面を平坦化して均一な高さとなるバンプを形成する技術が開示されている（たとえば特許文献５参照）。   Further, a technique is disclosed in which a mask material is formed on a substrate, a bump metal is embedded so as to fill the opening, and then a predetermined amount of the surface is shaved to flatten the upper surface to form a bump having a uniform height. (For example, refer to Patent Document 5).

また、バンプの高さを均一にするために、ホトレジストとステンシルを重ねてバンプ金属ペーストを充填し、その後、ホトレジストとステンシルを除去して均一なバンプ高さを形成する技術が開示されている（たとえば特許文献６参照）。
特開２００３−１７５２１号公報（段落［００５１］〜［００５４］、図１２） 特開２００２−２４６４０７号公報（段落［００４０］〜［００４４］、図１１） 特開２００３−３１８２１１号公報（段落［００４１］〜［００４６］、図２） 特開平７−１６１７２２号公報（段落［０００９］〜［００１１］、図１、図２） 特開平７−２９７１９６号公報（段落［００１２］〜［００１７］、図１） 特開２００２−２８９６３７号公報（段落［０００８］〜［００１１］、図１〜図３） Further, in order to make the bump height uniform, a technique is disclosed in which a photoresist and a stencil are stacked and filled with a bump metal paste, and then the photoresist and the stencil are removed to form a uniform bump height ( For example, see Patent Document 6).
JP 2003-17521 A (paragraphs [0051] to [0054], FIG. 12) JP 2002-246407 A (paragraphs [0040] to [0044], FIG. 11) JP 2003-318211 (paragraphs [0041] to [0046], FIG. 2) JP-A-7-161722 (paragraphs [0009] to [0011], FIGS. 1 and 2) JP 7-297196 A (paragraphs [0012] to [0017], FIG. 1) JP 2002-289637 A (paragraphs [0008] to [0011], FIGS. 1 to 3)

近年のＬＣＤドライバにおいては、その高機能化により入出力ピン数が増加しているため、ＬＣＤドライバのチップ面積におけるバンプの占有面積が増大している。一方で、ＬＣＤドライバの低コスト化および液晶パネルの実装面積の省スペース化を図るため、ＬＣＤドライバのチップサイズの縮小が要求されている。そこで、本発明者は、チップ内部のデバイスの上層にバンプを配置する構造を検討した。   In recent LCD drivers, the number of input / output pins has increased due to their higher functionality, and therefore the area occupied by bumps in the chip area of the LCD driver has increased. On the other hand, in order to reduce the cost of the LCD driver and to save the mounting area of the liquid crystal panel, it is required to reduce the chip size of the LCD driver. Therefore, the present inventor examined a structure in which bumps are arranged on the upper layer of the device inside the chip.

一般に、バンプの材質は金または金を含む合金が用いられ、バンプはメッキ法により金属パッド上に形成される。しかし、メッキ法ではバンプ材が等方的に成長するため、下地の形状を反映してバンプは形成される。従って、前述したチップ内部のデバイスの上層にバンプを配置する構造では、バンプの表面がデバイスの表面の凹凸をトレースするので、その表面に凹凸が生じてしまう。このため、バンプの表面段差が実装時の歩留まりを左右する実装方法、たとえばガラス基板上に形成された電極へバンプを接着させるＣＯＧ（Chip On Glass）実装またはテープ上に形成されたインナーリードへバンプを接着させるＴＣＰ（Tape Carrier Package）実装を採用した場合は、ガラス基板上に形成された電極またはテープ上に形成されたインナーリードとの接合不良が発生しやすく、実装時に歩留まりの低下を招くという問題が生ずる。   In general, the bump is made of gold or an alloy containing gold, and the bump is formed on a metal pad by a plating method. However, since the bump material isotropically grows in the plating method, the bump is formed reflecting the shape of the base. Therefore, in the structure in which the bumps are arranged on the upper layer of the device inside the chip described above, the bump surface traces the unevenness on the surface of the device, and thus the surface is uneven. For this reason, a bumping method in which the bump surface step affects the yield during mounting, for example, COG (Chip On Glass) mounting in which bumps are bonded to electrodes formed on a glass substrate or bumps to inner leads formed on tape When TCP (Tape Carrier Package) mounting is used, bonding failure with an electrode formed on a glass substrate or an inner lead formed on a tape is likely to occur, resulting in a decrease in yield during mounting. Problems arise.

本発明の目的は、バンプの表面の平坦化を図ることのできる技術を提供することにある。   An object of the present invention is to provide a technique capable of flattening the surface of a bump.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

本発明による半導体装置の製造方法は、パッドと電気的に接続するバリア層上に液体金属化合物を塗布し、さらに熱処理または化学反応処理によりこの液体金属化合物を単体金属膜に還元してシード層を形成した後、シード層上にメッキ法によりバンプを形成する工程を有するものである。   In the method of manufacturing a semiconductor device according to the present invention, a liquid metal compound is applied on a barrier layer electrically connected to a pad, and the liquid metal compound is reduced to a single metal film by heat treatment or chemical reaction treatment to form a seed layer. After forming, there is a step of forming bumps on the seed layer by plating.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。   Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

液体金属化合物を用いることにより、その表面が平坦なシード層がバンプの下地に形成されるので、シード層の表面形状をトレースして形成されるバンプの表面は平坦な形状となる。   By using the liquid metal compound, a seed layer having a flat surface is formed on the base of the bump, so that the surface of the bump formed by tracing the surface shape of the seed layer has a flat shape.

本実施の形態において、便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。   In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related.

また、本実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。さらに、本実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。同様に、本実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。   Also, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, the constituent elements (including element steps and the like) are not necessarily essential unless particularly specified and apparently essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

また、本実施の形態で用いる図面においては、平面図であっても図面を見易くするためにハッチングを付す場合もある。また、本実施の形態においては、電界効果トランジスタを代表するＭＩＳ・ＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）をＭＩＳと略し、ｐチャネル型のＭＩＳ・ＦＥＴをｐＭＩＳと略し、ｎチャネル型のＭＩＳ・ＦＥＴをｎＭＩＳと略す。   In the drawings used in the present embodiment, hatching may be added even in a plan view for easy understanding of the drawings. In this embodiment, a MIS • FET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MIS • FET is abbreviated as pMIS, and an n-channel type MIS • FET. Is abbreviated as nMIS.

また、本実施の形態を説明するための全図において、同一機能を有するものは原則として同一の符号を付し、その繰り返しの説明は省略する。以下、本発明の実施の形態を図面に基づいて詳細に説明する。   In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals in principle, and the repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

本実施の形態によるＬＣＤドライバの外観概略図を図１に示す。   FIG. 1 is a schematic external view of an LCD driver according to this embodiment.

半導体チップ１の内部には、ＬＣＤドライバを構成する、たとえば増幅回路２、デコーダ回路３、レベルシフタ回路４、バイアス回路５、ランダムロジック回路６など（以下、メイン回路２〜６と記す）が配置されている。このメイン回路２〜６を囲んで、半導体チップ１の周辺部に所定数のパッド７が形成され、さらにパッド７にシード層（図示は省略）を介して電気的に接続するバンプ（図中、網掛けのハッチングで示す）８が形成されている。パッド７は、たとえばＬＣＤドライバの最上層配線と同一層の導体膜によって構成され、その導体膜は、たとえばアルミニウムまたはその合金等からなる。また、バンプ８は、たとえば金またはその合金等からなる。   Inside the semiconductor chip 1, for example, an amplifier circuit 2, a decoder circuit 3, a level shifter circuit 4, a bias circuit 5, a random logic circuit 6 (hereinafter referred to as main circuits 2 to 6) constituting an LCD driver are arranged. ing. A predetermined number of pads 7 are formed on the periphery of the semiconductor chip 1 so as to surround the main circuits 2 to 6, and further bumps that are electrically connected to the pads 7 through seed layers (not shown) (in the drawing, 8) (shown by shaded hatching). The pad 7 is made of a conductor film in the same layer as the uppermost layer wiring of the LCD driver, for example, and the conductor film is made of, for example, aluminum or an alloy thereof. The bump 8 is made of, for example, gold or an alloy thereof.

さらに、バンプ８の一部は上記メイン回路２〜６の形成領域に重なって形成されており、このようにバンプ８を形成することにより、バンプ８を全て上記メイン回路２〜６以外の領域に形成する場合よりも、半導体チップ１の面積を小さくすることができる。なお、バンプ８の全部を上記メイン回路２〜６の形成領域に重ねて形成してもよい。また、バンプ８を長方形状に形成しているが、正方形状であってもよい。   Further, a part of the bump 8 is formed so as to overlap the formation region of the main circuits 2 to 6, and by forming the bump 8 in this way, the bump 8 is entirely placed in a region other than the main circuits 2 to 6. The area of the semiconductor chip 1 can be made smaller than when it is formed. Note that all of the bumps 8 may be formed so as to overlap the formation region of the main circuits 2 to 6. Moreover, although the bump 8 is formed in a rectangular shape, it may be a square shape.

次に、本実施の形態によるＬＣＤドライバの製造方法を図２〜図７に示す半導体基板の要部断面図を用いて工程順に説明する。なお。ＬＣＤドライバを構成する半導体デバイスとしてＣＭＯＳ（Complementary Metal Oxide Semiconductor）デバイスを例示する。   Next, a manufacturing method of the LCD driver according to the present embodiment will be described in the order of steps with reference to cross-sectional views of the main part of the semiconductor substrate shown in FIGS. Note that. A CMOS (Complementary Metal Oxide Semiconductor) device will be exemplified as a semiconductor device constituting the LCD driver.

まず、図２に示すように、たとえばｐ型のシリコン単結晶からなる半導体基板（円形の薄い板状に加工した半導体ウエハ）９を用意する。次に、素子分離領域に絶縁膜からなる分離部１０を形成した後、半導体基板９に不純物をイオン注入してｐウエル１１およびｎウエル１２を形成する。ｐウエル１１にはｐ型の導電性を示す不純物（たとえばボロン）をイオン注入し、ｎウエル１２にはｎ型の導電性を示す不純物（たとえばリンまたはヒ素）をイオン注入する。   First, as shown in FIG. 2, a semiconductor substrate (semiconductor wafer processed into a circular thin plate) 9 made of, for example, p-type silicon single crystal is prepared. Next, after forming an isolation portion 10 made of an insulating film in the element isolation region, impurities are ion-implanted into the semiconductor substrate 9 to form a p-well 11 and an n-well 12. Impurities (eg, boron) having p-type conductivity are ion-implanted into the p-well 11, and impurities (eg, phosphorus or arsenic) having n-type conductivity are ion-implanted into the n-well 12.

次に、ｎＭＩＳおよびｐＭＩＳを構成するゲート絶縁膜１３、ゲート電極１４およびキャップ絶縁膜１５を形成し、さらにゲート電極１４の側壁にサイドウォール１６を形成する。続いて、ゲート電極１４の両側のｐウエル１１にｎ型の導電性を示す不純物（たとえばリンまたはヒ素）をイオン注入し、ｎＭＩＳのソース・ドレインとして機能するｎ型半導体領域１７をゲート電極１４およびサイドウォール１６に対して自己整合的に形成する。同様に、ゲート電極１４の両側のｎウエル１２にｐ型の導電性を示す不純物（たとえばフッ化ボロン）をイオン注入し、ｐＭＩＳのソース・ドレインとして機能するｐ型半導体領域１８をゲート電極１４およびサイドウォール１６に対して自己整合的に形成する。   Next, the gate insulating film 13, the gate electrode 14, and the cap insulating film 15 constituting the nMIS and pMIS are formed, and the side wall 16 is formed on the side wall of the gate electrode 14. Subsequently, an impurity (for example, phosphorus or arsenic) having n-type conductivity is ion-implanted into the p-well 11 on both sides of the gate electrode 14, and the n-type semiconductor region 17 functioning as the source / drain of the nMIS is formed in the gate electrode 14 and It is formed in a self-aligned manner with respect to the sidewall 16. Similarly, an impurity exhibiting p-type conductivity (for example, boron fluoride) is ion-implanted into the n-well 12 on both sides of the gate electrode 14, and the p-type semiconductor region 18 functioning as the source / drain of the pMIS is formed into the gate electrode 14 and It is formed in a self-aligned manner with respect to the sidewall 16.

次に、半導体基板９上に絶縁膜１９を形成した後、レジストパターンをマスクとしたエッチングにより絶縁膜１９を加工して接続孔２０を形成する。この接続孔２０はｎ型半導体領域１７またはｐ型半導体領域１８上などの必要部分に形成する。続いて、接続孔２０の内部に、たとえばタングステンを主導体とするプラグ２１を形成した後、プラグ２１に接続する第１層目の配線２２を形成する。配線２２は、たとえばアルミニウムを主導体とする導体膜からなる。   Next, after forming the insulating film 19 on the semiconductor substrate 9, the insulating film 19 is processed by etching using the resist pattern as a mask to form the connection hole 20. The connection hole 20 is formed in a necessary portion such as on the n-type semiconductor region 17 or the p-type semiconductor region 18. Subsequently, after a plug 21 having, for example, tungsten as a main conductor is formed in the connection hole 20, a first-layer wiring 22 connected to the plug 21 is formed. Wiring 22 is made of, for example, a conductor film whose main conductor is aluminum.

次に、半導体基板９上に絶縁膜２３を形成した後、レジストパターンをマスクとしたエッチングにより絶縁膜２３を加工して接続孔２４を形成する。この接続孔２４は第１層目の配線２２上などの必要部分に形成する。続いて、接続孔２４の内部を含む半導体基板９上に、たとえばアルミニウムを主導体とする導体膜を堆積し、レジストパターンをマスクとしたエッチングによりこの導体膜を加工して第２層目の配線２５を形成する。さらに、上層の配線を形成するが、その図示および説明は省略する。   Next, after forming the insulating film 23 on the semiconductor substrate 9, the insulating film 23 is processed by etching using the resist pattern as a mask to form the connection hole 24. The connection hole 24 is formed in a necessary portion such as on the first-layer wiring 22. Subsequently, a conductor film having, for example, aluminum as a main conductor is deposited on the semiconductor substrate 9 including the inside of the connection hole 24, and this conductor film is processed by etching using a resist pattern as a mask to form a second layer wiring. 25 is formed. Further, although upper layer wiring is formed, illustration and description thereof are omitted.

次に、図３に示すように、半導体基板９上に絶縁膜２６を形成した後、レジストパターンをマスクとしたエッチングによりこの絶縁膜２６を加工して開口部（図示は省略）を形成する。なお、絶縁膜２６は下地の凹凸をトレースすることにより、その表面に凹凸を生じている。   Next, as shown in FIG. 3, after forming the insulating film 26 on the semiconductor substrate 9, the insulating film 26 is processed by etching using the resist pattern as a mask to form an opening (not shown). The insulating film 26 has unevenness on the surface by tracing the unevenness of the base.

次に、絶縁膜２６に形成された接続孔の内部を含む半導体基板９上に、たとえばアルミニウムを主導体とする導体膜を堆積し、レジストパターンをマスクとしたエッチングによりこの導体膜を加工して最上層配線（図示は省略）を形成する。前述したパッド７は、この最上層配線と同一層の導体膜によって形成される。続いて、ＣＭＯＳデバイスの特性を安定化させるために、水素アニール処理を施した後、パッド７（および最上層配線）を覆うパッシベーション膜２８を形成する。パッシベーション膜２８は、たとえばプラズマＣＶＤ（Chemical Vapor Deposition）法で形成されるシリコン窒化膜とすることができ、外部からの水分や不純物の侵入防止、またはα線の透過抑制などの機能を有している。続いて、レジストパターンをマスクとしたエッチングによりパッシベーション膜２８を加工することにより、パッド７上に開口部２９を形成してパッド７の表面を露出させる。   Next, a conductor film having, for example, aluminum as a main conductor is deposited on the semiconductor substrate 9 including the inside of the connection hole formed in the insulating film 26, and this conductor film is processed by etching using a resist pattern as a mask. Uppermost layer wiring (not shown) is formed. The aforementioned pad 7 is formed of a conductor film in the same layer as the uppermost layer wiring. Subsequently, in order to stabilize the characteristics of the CMOS device, a hydrogen annealing process is performed, and then a passivation film 28 covering the pad 7 (and the uppermost layer wiring) is formed. The passivation film 28 can be a silicon nitride film formed by, for example, a plasma CVD (Chemical Vapor Deposition) method, and has a function of preventing moisture or impurities from entering from the outside or suppressing transmission of α rays. Yes. Subsequently, the passivation film 28 is processed by etching using the resist pattern as a mask, thereby forming an opening 29 on the pad 7 to expose the surface of the pad 7.

次に、開口部２９を含む半導体基板９上に、たとえばチタンタングステン（ＴｉＷ）膜またはチタンパラジウム（ＴｉＰｄ）膜等からなるバリア層３０を形成する。バリア層３０は、たとえばスパッタリング法により形成でき、バリア層３０の形成により、パッド７の材質であるアルミニウムと後述するシード層の材質との反応を抑えることができる。バリア層３０の厚さは、たとえば２００ｎｍ程度であって相対的に薄いため、下地のパッシベーション膜２８の凹凸のある表面形状を引き継ぐことになる。   Next, a barrier layer 30 made of, for example, a titanium tungsten (TiW) film or a titanium palladium (TiPd) film is formed on the semiconductor substrate 9 including the opening 29. The barrier layer 30 can be formed by, for example, a sputtering method, and the formation of the barrier layer 30 can suppress a reaction between aluminum which is a material of the pad 7 and a material of a seed layer which will be described later. Since the thickness of the barrier layer 30 is, for example, about 200 nm and is relatively thin, the uneven surface shape of the underlying passivation film 28 is taken over.

次に、バリア層３０上に液体金属化合物３１ａを、たとえばスピンコータを用いて形成する。液体金属化合物３１ａは、たとえばトリエチルアルミニウム（Ａｌ（Ｃ２Ｈ５）３）、コバルトカルボニル化合物（Ｃｏ（ＣＯ２）４）またはニッケルカルボニル化合物（Ｎｉ（ＣＯ２）４）等であり、常温では液体であるが、熱処理または化学反応処理等を施すことにより単体金属に還元する金属化合物である。従って、その後、たとえばトリエチルアルミニウムに１００℃程度、コバルトカルボニル化合物またはニッケルカルボニル化合物に２００〜３００℃程度の熱処理を施すことにより、図４に示すように、バリア層３０上に、たとえばアルミニウム、コバルトまたはニッケルを主導体とするシード層３１が形成される。液体金属化合物３１ａを塗布することにより、バリア層３０の表面の凹部には厚く、凸部には薄くシード層３１が形成されて、シード層３１の平坦な表面が得られる。シード層３１の厚さは、たとえば１００〜１５００ｎｍ程度であり、バリア層３０の表面の凹凸を平坦化する厚みを有している。 Next, the liquid metal compound 31a is formed on the barrier layer 30 using, for example, a spin coater. The liquid metal compound 31a is, for example, triethylaluminum (Al (C 2 H 5 ) 3 ), cobalt carbonyl compound (Co (CO 2 ) 4 ), nickel carbonyl compound (Ni (CO 2 ) 4 ), etc., and is liquid at room temperature. However, it is a metal compound that is reduced to a single metal by heat treatment or chemical reaction treatment. Therefore, after that, for example, triethylaluminum is subjected to a heat treatment at about 100 ° C. and a cobalt carbonyl compound or a nickel carbonyl compound at a temperature of about 200 to 300 ° C., as shown in FIG. A seed layer 31 having nickel as a main conductor is formed. By applying the liquid metal compound 31a, the seed layer 31 is formed thick on the concave portion of the surface of the barrier layer 30 and thinly on the convex portion, and a flat surface of the seed layer 31 is obtained. The thickness of the seed layer 31 is, for example, about 100 to 1500 nm, and has a thickness that flattens the irregularities on the surface of the barrier layer 30.

次に、図５に示すように、シード層３１上にレジストパターンＲＰを形成し、バンプ８が形成される領域のシード層３１の表面を露出させた後、メッキ法によりシード層３１上に金からなるバンプ８を形成する。バンプ８は下地のシード層３１の表面をトレースして成長するが、シード層３１の表面は平坦であるので、バンプ８の表面は平坦となる。続いて、図６に示すように、レジストパターンＲＰ、レジストパターンＲＰ下のシード層３１およびバリア層３０を順次除去することにより、外部接続用電極として突き出したバンプ８が得られる。   Next, as shown in FIG. 5, a resist pattern RP is formed on the seed layer 31 to expose the surface of the seed layer 31 in the region where the bumps 8 are formed, and then gold is deposited on the seed layer 31 by plating. A bump 8 is formed. The bump 8 grows by tracing the surface of the underlying seed layer 31. Since the surface of the seed layer 31 is flat, the surface of the bump 8 is flat. Subsequently, as shown in FIG. 6, the bump 8 protruding as an external connection electrode is obtained by sequentially removing the resist pattern RP, the seed layer 31 and the barrier layer 30 under the resist pattern RP.

その後、図７（ａ）に示すように、ガラス基板３２上に形成された電極３３にバンプ８を接続するＣＯＧ実装、または、図７（ｂ）に示すように、テープ３４上に形成されたインナーリード３５にバンプ８を接続するＴＣＰ実装等により、ＬＣＤドライバをパッケージ基板に実装する。   After that, as shown in FIG. 7A, COG mounting for connecting the bumps 8 to the electrodes 33 formed on the glass substrate 32, or formed on the tape 34 as shown in FIG. 7B. The LCD driver is mounted on the package substrate by TCP mounting for connecting the bumps 8 to the inner leads 35.

なお、本実施の形態では、シード層３１を液体金属化合物で形成したが、これに限定されるものではなく、たとえば液体金属化合物に代えてアマルガム（銀すず合金と水銀との化合物）を用いても同様な効果が得られる。たとえばバリア層３０上にアマルガムを塗布し、その後、熱処置を施すことによりアマルガムが還元されて銀を主導体とするシード層３１が形成される。   In the present embodiment, the seed layer 31 is formed of a liquid metal compound. However, the seed layer 31 is not limited to this. For example, amalgam (a compound of a silver tin alloy and mercury) is used instead of the liquid metal compound. The same effect can be obtained. For example, amalgam is applied on the barrier layer 30 and then heat treatment is performed, whereby the amalgam is reduced to form a seed layer 31 having silver as a main conductor.

このように、本実施の形態によれば、ＬＣＤドライバのパッシベーション膜２８の表面に凹凸があっても、液体金属化合物を用いることによって、その表面が平坦なシード層３１をパッシベーション膜２８とバンプ８との間に形成することができるので、バンプ８は下地であるシード層３１の表面形状をトレースして、バンプ８の表面は平坦な形状となる。これにより、たとえばＬＣＤドライバにＣＯＧ実装またはＴＣＰ実装を採用しても、ガラス基板３２上に形成された電極３３またはテープ３４上に形成されたインナーリード３５との接合不良が発生しにくくなるので、接続不良に起因する実装時の歩留まりの低下を防ぐことができる。   As described above, according to the present embodiment, even if the surface of the passivation film 28 of the LCD driver is uneven, the seed layer 31 having a flat surface is formed on the passivation film 28 and the bumps 8 by using the liquid metal compound. Therefore, the bump 8 traces the surface shape of the seed layer 31 as a base, and the surface of the bump 8 becomes a flat shape. Thereby, even if COG mounting or TCP mounting is adopted for the LCD driver, for example, it becomes difficult to cause a bonding failure with the electrode 33 formed on the glass substrate 32 or the inner lead 35 formed on the tape 34. It is possible to prevent a decrease in yield due to poor connection during mounting.

以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

なお、前記実施の形態では、ＬＣＤドライバのバンプに適用した場合について説明したが、たとえば多ピンマイコンのバンプにも適用することが可能であり、同様の効果が得られる。   In the above-described embodiment, the case of applying to the bump of the LCD driver has been described. However, it can be applied to the bump of a multi-pin microcomputer, for example, and the same effect can be obtained.

本発明の半導体装置の製造方法は、バンプを用いて半導体装置を実装基板の電極やインナーリード等に直接実装する半導体装置の高密度実装に適用することができる。   The method for manufacturing a semiconductor device of the present invention can be applied to high-density mounting of a semiconductor device in which the semiconductor device is directly mounted on an electrode, an inner lead or the like of a mounting substrate using bumps.

本発明の一実施の形態によるＬＣＤドライバの外観概略図である。1 is a schematic external view of an LCD driver according to an embodiment of the present invention. 本発明の一実施の形態であるＬＣＤドライバの製造工程を示す半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the LCD driver which is one embodiment of this invention. 本発明の一実施の形態であるＬＣＤドライバの製造工程を示す半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the LCD driver which is one embodiment of this invention. 本発明の一実施の形態であるＬＣＤドライバの製造工程を示す半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the LCD driver which is one embodiment of this invention. 本発明の一実施の形態であるＬＣＤドライバの製造工程を示す半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the LCD driver which is one embodiment of this invention. 本発明の一実施の形態であるＬＣＤドライバの製造工程を示す半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the LCD driver which is one embodiment of this invention. （ａ）、（ｂ）は、本発明の一実施の形態であるＬＣＤドライバの製造工程を示す半導体基板の要部断面図である。(A), (b) is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the LCD driver which is one embodiment of this invention.

符号の説明Explanation of symbols

１ 半導体チップ
２ 増幅回路
３ デコーダ回路
４ レベルシフタ回路
５ バイアス回路
６ ランダムロジック回路
７ パッド
８ バンプ
９ 半導体基板
１０ 分離部
１１ ｐウエル
１２ ｎウエル
１３ ゲート絶縁膜
１４ ゲート電極
１５ キャップ絶縁膜
１６ サイドウォール
１７ ｎ型半導体領域
１８ ｐ型半導体領域
１９ 絶縁膜
２０ 接続孔
２１ プラグ
２２ 配線
２３ 絶縁膜
２４ 接続孔
２５ 配線
２６ 絶縁膜
２８ パッシベーション膜
２９ 開口部
３０ バリア層
３１ シード層
３１ａ 液体金属化合物
３２ ガラス基板
３３ 電極
３４ テープ
３５ インナーリード
ＲＰ レジストパターン DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Amplifying circuit 3 Decoder circuit 4 Level shifter circuit 5 Bias circuit 6 Random logic circuit 7 Pad 8 Bump 9 Semiconductor substrate 10 Separation part 11 P well 12 N well 13 Gate insulating film 14 Gate electrode 15 Cap insulating film 16 Side wall 17 n-type semiconductor region 18 p-type semiconductor region 19 insulating film 20 connecting hole 21 plug 22 wiring 23 insulating film 24 connecting hole 25 wiring 26 insulating film 28 passivation film 29 opening 30 barrier layer 31 seed layer 31a liquid metal compound 32 glass substrate 33 Electrode 34 Tape 35 Inner lead RP Resist pattern

Claims (5)

（ａ）半導体基板上に導体膜からなるパッドを形成する工程と、
（ｂ）前記半導体基板上にパッシベーション膜を形成した後、前記パッドの表面が露出する開口部を前記パッシベーション膜に形成する工程と、
（ｃ）前記パッドと電気的に接続するバリア層を形成する工程と、
（ｄ）前記バリア層上に液体金属化合物を塗布する工程と、
（ｅ）前記液体金属化合物に熱処理または化学反応処理を施すことにより、前記液体金属化合物を単体金属に還元してシード層を形成する工程と、
（ｆ）前記シード層上にメッキ法によりバンプを形成する工程と、
を有することを特徴とする半導体装置の製造方法。 (A) forming a pad made of a conductor film on a semiconductor substrate;
(B) after forming a passivation film on the semiconductor substrate, forming an opening in the passivation film where the surface of the pad is exposed;
(C) forming a barrier layer electrically connected to the pad;
(D) applying a liquid metal compound on the barrier layer;
(E) performing a heat treatment or a chemical reaction treatment on the liquid metal compound to reduce the liquid metal compound to a single metal to form a seed layer;
(F) forming a bump on the seed layer by a plating method;
A method for manufacturing a semiconductor device, comprising: 請求項１記載の半導体装置の製造方法において、前記液体金属化合物は、トリエチルアルミニウム、コバルトカルボニル化合物またはニッケルカルボニル化合物であることを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the liquid metal compound is triethylaluminum, a cobalt carbonyl compound, or a nickel carbonyl compound. 請求項１記載の半導体装置の製造方法において、前記液体金属化合物はスピンコータを用いて形成されることを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the liquid metal compound is formed using a spin coater. （ａ）半導体基板上に導体膜からなるパッドを形成する工程と、
（ｂ）前記半導体基板上にパッシベーション膜を形成した後、前記パッドの表面が露出する開口部を前記パッシベーション膜に形成する工程と、
（ｃ）前記パッドと電気的に接続するバリア層を形成する工程と、
（ｄ）前記バリア層上にアマルガムを塗布する工程と、
（ｅ）前記アマルガムに熱処理を施すことにより、前記アマルガム中の金属を析出させてシード層を形成する工程と、
（ｆ）前記シード層上にメッキ法によりバンプを形成する工程と、
を有することを特徴とする半導体装置の製造方法。 (A) forming a pad made of a conductor film on a semiconductor substrate;
(B) after forming a passivation film on the semiconductor substrate, forming an opening in the passivation film where the surface of the pad is exposed;
(C) forming a barrier layer electrically connected to the pad;
(D) applying amalgam on the barrier layer;
(E) applying a heat treatment to the amalgam to deposit a metal in the amalgam to form a seed layer;
(F) forming a bump on the seed layer by a plating method;
A method for manufacturing a semiconductor device, comprising: 請求項１または４記載の半導体装置の製造方法において、半導体チップのメイン回路形成領域に前記バンプの一部または全部が重なって形成されることを特徴とする半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein a part or all of the bumps are formed so as to overlap a main circuit formation region of the semiconductor chip.
JP2005311257A 2005-10-26 2005-10-26 Manufacturing method of semiconductor device Pending JP2007123407A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009117761A (en) * 2007-11-09 2009-05-28 Renesas Technology Corp Semiconductor device and method of manufacturing the same
JP2011029396A (en) * 2009-07-24 2011-02-10 Renesas Electronics Corp Semiconductor device
JP2014116621A (en) * 2014-01-23 2014-06-26 Renesas Electronics Corp Semiconductor device
JP2015228522A (en) * 2015-09-02 2015-12-17 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2020532112A (en) * 2017-08-25 2020-11-05 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ Compressible intermediate layer with defined crack protection edge extension

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009117761A (en) * 2007-11-09 2009-05-28 Renesas Technology Corp Semiconductor device and method of manufacturing the same
US8552552B2 (en) 2007-11-09 2013-10-08 Renesas Electronics Corporation Semiconductor device and a method of manufacturing the same
JP2011029396A (en) * 2009-07-24 2011-02-10 Renesas Electronics Corp Semiconductor device
JP2014116621A (en) * 2014-01-23 2014-06-26 Renesas Electronics Corp Semiconductor device
JP2015228522A (en) * 2015-09-02 2015-12-17 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2020532112A (en) * 2017-08-25 2020-11-05 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ Compressible intermediate layer with defined crack protection edge extension

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