JPH0575015A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve a manufacturing yield of devices as a whole by a method wherein a common input/output lead is connected electrically with each of stacked chips and the whole is sealed with resin or a cap. CONSTITUTION:In a semiconductor device 1 wherein four semiconductor chips 2 are stacked, each of the semiconductor chips 2 is provided with bumps 3 on the opposite sides and copper foil leads 4 are connected to the bumps 3 respectively. These chips 2 are stacked with insulating layers 5 interposed. The leads 4 are connected electrically by studs 6 and the stud of the lowermost layer is connected to a lead frame 7. The lead frame 7 is fixed on a base made of plastic and resin packing is conducted in this state. According to this constitution, the number of input/output terminals formed on each chip can be lessened and the quality of the semiconductor chips having the respective functions can be inspected before the chips are assembled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a device in which a plurality of semiconductor chips are vertically stacked.

[0002]

2. Description of the Related Art ICs formed on a silicon semiconductor substrate,
The manufacturing technology of LSIs and the like has advanced day and night, and the degree of integration of transistors and the like has also dramatically increased. As the degree of integration has increased, the functions of semiconductor devices (semiconductor chips) have also dramatically improved, and have come to be regarded as a system larger than simple components.

At the same time, a CPU (logical circuit), a mask ROM, an EPROM, an E as system components
EPROM, flash EPROM, DRAM, SRA
M, I ² L, high-speed input / output unit (bipolar, bi-CMD
Independent devices such as S) are being efficiently manufactured using their own dedicated manufacturing processes. In addition, the demand for large-scale systems in which a large number of components of the same kind such as neuronet elements are aggregated has increased.

[0004]

In view of such technical requirements, the following problems have recently occurred in the prior art. With the increase in the scale of LSI integration,
This is because the number of external connection terminals of the input / output section is increased and the area ratio of the bonding pad and the input / output protection circuit on the chip surface is increased. This results in reduced integration efficiency.

Further, in the conventional LSI manufacturing process which is formed on one two-dimensional surface along with the sophistication of system functions required for devices such as LSI, a manufacturing process including all the above-mentioned components is constructed. It is very difficult to do so, and even if such a complicated manufacturing process could be constructed, the minimum wiring width dimension (the number of elements that can be integrated per unit area) is restricted, and each individual It is much less efficient than a dedicated manufacturing process, and at the same time, it is only possible to reduce the operating speed and other performance of the resulting device, resulting in very poor cost performance.

[0006]

In view of the above circumstances, the present inventor has completed the semiconductor device of the present invention as a result of earnest research, and its characteristic feature is TAB.
A plurality of semiconductor chips mounted by the method are stacked one above the other, and a common input / output lead is electrically connected between the stacked chips and resin encapsulation or cap sealing is performed.

The semiconductor chip used in the present invention is TAB.
It is a semiconductor chip mounted by the method. The TAB method corresponds to the wire bonding method and the flip chip method, and is one of the methods of extracting the electrodes of the semiconductor chip to the outside. Usually, the carrier film is provided with a metal layer to be an inner lead, and the metal layer is connected to the electrode of the semiconductor chip and the outer lead by forming a wiring by a punching process or the like. The present invention was developed by taking advantage of this TAB method. That is, in the TAB method, the planar leads are present before being connected to the external electrodes or the external leads.

The upper and lower layers of the semiconductor device need only be stacked one above the other with an insulating layer interposed therebetween. Then, the leads from each chip may be electrically connected. As a connecting method, a stud (electrically passing protrusion) may be provided in advance on the lead and ordinary outer lead bonding may be repeated.

When all the chips to be stacked are of the same type, for example, when only 5 SRAMs are stacked, a single lead terminal that cannot be shared is connected to each external pin, and a common lead terminal is used for each chip. Connect between,
It will be connected to one external pin as one terminal. This means that the memory capacity is quintupled. In addition, since they are stacked on top of each other, the projected area is the same as the conventional one. Such applications include:
This is a case where a large-scale memory capacity is required, and a large number of SRAMs and DRAMs of the same kind are stacked. Similarly, in the case of a neuro network, those having the same type of function are stacked.

In the device of the present invention, different types of chips can be mixed and stacked. in this case,
Since it is not possible to connect all the leads, a dummy pad not involved in the operation may be provided in that part, or the number of inner leads may be reduced. As an example of such stacking, a stacking of a CCD chip, a CPU chip (logic circuit), an SRAM, a mask ROM, an EPROM, and the like from above may be considered. It can be used as a device dedicated to image information processing. In this case, naturally, the encapsulating resin is transparent such as acrylic resin.

The semiconductor device of the present invention is novel in that semiconductor chips are stacked on top of each other and each lead is electrically connected (in some cases, a dummy pad) and then integrated together. As for itself, a conventional one can be manufactured as long as a slight manufacturing complexity is allowed, and it is not necessary to be special.

[0012]

[Function] With the above device, a high degree of integration can be obtained,
And by sharing the input / output data bus line,
The number of input / output terminals can be reduced.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail based on the embodiments shown in the drawings. FIG. 1 is a sectional view showing an example of a semiconductor device 1 of the present invention. Four semiconductor chips 2 are stacked. Bumps 3 are provided on both sides of each semiconductor chip 2, and copper foil leads 4 are connected to the bumps 3. In this example, all semiconductor chips are SRA
M is the same kind. The chips 2 are stacked with the insulating layer 5 interposed therebetween.

The individual leads 4 are electrically connected by studs 6, and the studs in the lowermost layer are connected to the lead frame 7. The lead frame 7 is fixed to the substrate (made of plastic). In this state, resin filling is performed up to the portion indicated by the broken line. This completes the semiconductor device 1. This has a memory capacity four times as large as that of a conventional device having one stacked SRAM and the required area is the same. The height is only twice that of the conventional one. This height is usually relatively generous and often does not pose a problem. As a result, the degree of integration per unit area is greatly improved. In each semiconductor chip, a part of the copper foil lead 4 is removed in advance so that the copper foil lead 4 is not connected to the bump 3 that is not connected to the lead frame 7.

FIG. 2 is a schematic perspective view showing a connection state of each layer of FIG. It can be seen that the leads 4 emerge from each layer and they are individually connected up and down via studs.
In addition, a lead frame that finally becomes an external terminal is connected to the lowermost layer.

Next, the manufacturing method will be described. On a wafer-shaped semiconductor substrate that has almost completed the wafer creation process,
An adhesive metal and a metal layer as a base of plating are formed by vacuum vapor deposition or sputtering. After that, a photolithography technique is used to form a resist layer having openings only in the bump formation portions. Then, a metal such as Au, which is a bump forming material, is electroplated in the opening portion in a plating solution to form protrusions of about 10 to 30 μm. The unnecessary metal layer formed by vapor deposition or sputtering is removed by etching using the raised portion as a mask,
The bump forming process is completed. FIG. 3 shows the semiconductor chip. The thickness of the semiconductor chip is
The thickness is preferably about 100 to 300 μm.
Of course, a transfer bump method in which bumps are formed on the lead side instead of the semiconductor chip side may be used.

Next, FIG. 4 shows one of the leads used in the present invention.
Here is an example: The lead used in the present invention is not particularly limited, but the lead of this embodiment is suitable. In this example,
Leads 4 are formed on a carrier tape 9 made of polyimide, and studs 6 are provided on the leads 4.
This stud may be formed by using a photoresist.

Next, the bump-formed semiconductor chip shown in FIG. 3 is subjected to inner bonding (gang bonding) performed in a normal TAB process with respect to the TAB tape, and the leads and bumps are mechanically and electrically connected. Join. At this time, an electrical function test of each chip is performed to remove defective products. FIG. 5 shows a state in which the lead 4 and the semiconductor chip 2 are joined. The semiconductor chip shown in FIG. 5 is provided with an insulating layer 5 below it.

Next, the lead frame 7 used in the present invention will be described. FIG. 6 is a sectional view showing the lead frame 7 used in the present invention. This need only be provided with studs on a normal leadframe and need not be special.

Finally, in the lead frame 7 shown in FIG.
The semiconductor chip 2 shown in FIG. 5 is overlaid and outer lead bonding is repeated. The insulating layer 5 is unnecessary for the lowermost layer. Also, the topmost layer does not require studs. Finally, in the case of resin mold or ceramic, cap sealing is performed and assembly is completed.

[0021]

In the semiconductor device described in detail above, the memory capacity can be easily increased by simply stacking the semiconductor devices on top of each other, except that the size of the device itself is slightly increased. It doesn't change. Therefore, the degree of integration can be increased. In addition, by combining various semiconductor chips, a large-scale system can be configured with one semiconductor device.

Furthermore, by connecting the leads by stacking them on top of each other, the number of input / output terminals formed on each chip can be reduced. In addition, since the quality of the semiconductor chips having the respective functions can be inspected before assembling each chip, the manufacturing yield of the device as a whole is increased and a great cost merit is obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of a semiconductor device of the present invention.

FIG. 2 is a schematic perspective view showing a connection state of each layer of the example shown in FIG.

FIG. 3 is a sectional view showing an example of a semiconductor chip used in the present invention.

FIG. 4 is a sectional view showing an example of a lead used in the present invention.

FIG. 5 is a sectional view showing an example of a semiconductor chip connected for the present invention.

FIG. 6 is a sectional view showing an example of a lead frame used in the present invention.

[Explanation of symbols]

 1 Semiconductor Device 2 Semiconductor Chip 3 Bump 4 Lead 5 Insulating Layer 6 Stud 7 Lead Frame 8 Plastic Substrate 9 Carrier Tape

Claims (1)

[Claims] 1. A plurality of semiconductor chips mounted by the TAB method are stacked one above the other, in which common input / output leads are electrically connected between the stacked chips and a resin encapsulation or cap seal is used. Semiconductor device characterized by performing.