JPH0563081A - Laying-out method for integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a cell base type integrated circuit device having high integration by reducing a layout area. CONSTITUTION:When cells previously prepared in a cell library according to logical connection information are once automatically disposed and then diffused regions of the same potential exist at the ends of adjacent cells, the cells are so redisposed that the diffused regions of the same potential are superposed, and a layout area is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of laying out an integrated circuit device by a cell-based method to obtain a layout pattern.

[0002]

2. Description of the Related Art A gate array type integrated circuit device is a typical device that allows a user to manufacture a desired integrated circuit at low cost in a short period of time. In the gate array integrated circuit device, the process up to the diffusion region forming process is common to all integrated circuits, an intermediate product up to the process is manufactured in advance, and wiring is used to realize customization. This gate array integrated circuit device can be developed in a short period of time because the diffusion region formation process is common, but on the other hand, the degree of freedom in design is low and unnecessary regions that are not actually used are used. There is also the drawback that there are many.

As an integrated circuit device that solves these drawbacks, there is a cell-based integrated circuit device. The cell-based integrated circuit device is manufactured by automatically arranging and wiring prepared cells, and the manufacturing time is slightly longer than that of the gate array integrated circuit device, but the degree of integration is high in advance. Since the design is performed using the designed cells, it is possible to manufacture an integrated circuit device having a higher density and a smaller chip area. Moreover, since the wiring region is not fixed, a more flexible and high-density design is possible.

A conventional configuration example of such a cell-based integrated circuit device and a mask data creating procedure will be described below.

FIG. 1 is a main schematic diagram showing the structure of a poly-cell type cell-based integrated circuit device composed only of cells having substantially the same height, and FIG. 2 includes macro cells such as ROM, RAM and ALU. It is a main schematic diagram which shows the structure of the possible building type cell-based integrated circuit device. In FIGS. 1 and 2, reference numeral 1 denotes an integrated circuit device, and a plurality of input / output buffer circuits 2 for interfacing signals between an internal circuit of the integrated circuit device 1 and the outside are arranged on the periphery of the integrated circuit device 1. Has been done. Inside these input / output buffer circuits 2, an internal region 3 is provided in which various cells 4 such as various gates and flip-flops for realizing the logical functions required by the integrated circuit device 1 are formed. ..
Further, in the building type cell-based integrated circuit device shown in FIG. 2, the macro cell 5 such as ROM, RAM, ALU for realizing the logical function required by the integrated circuit device 1.
Are provided in addition to the various cells 4 described above. The layout patterns of the cells 4 and macro cells 5 are prepared in advance as a cell library, and are extracted from the cell library and automatically arranged when necessary.

Next, an inverter circuit will be described as an example of the cell 4. 3, FIG. 4, and FIG. 5 are a symbol diagram of an inverter circuit in which the load driving capacity is twice the standard, a transistor circuit diagram of the inverter circuit, and a main schematic diagram of a layout pattern of the inverter circuit. As shown in FIG. 4, this inverter circuit has a configuration in which two P-channel transistors 6a and 6b are connected in parallel and two N-channel transistors 7a and 7b are connected in parallel.
A reference voltage is applied to the source electrodes of the P-channel transistors 6a and 6b, the gate electrodes of the P-channel transistors 6a and 6b are connected to the input terminal A, and the drain electrodes of the P-channel transistors 6a and 6b are connected to the output terminal B. Connected to the
The source electrodes of the N-channel transistors 7a and 7b are grounded, the gate electrodes of the N-channel transistors 7a and 7b are connected to the input terminal A, and the drain electrodes of the N-channel transistors 7a and 7b are connected to the output terminal B. There is.

The layout pattern of the inverter circuit will be described with reference to FIG. Gate polysilicon 12a, 12b
Constitute the gate electrodes of the P-channel transistors 6a and 6b in FIG. The P type diffusion regions 14a and 14c are P in FIG.
The source electrodes of the channel transistors 6a and 6b are formed, and the P-type diffusion region 14b is formed of the drain electrodes of the P channel transistors 6a and 6b in FIG. The gate polysilicons 13a and 13b form the gate electrodes of the N channel transistors 7a and 7b in FIG. The N-type diffusion regions 15a and 15c are the N-channel transistors 7a and 7b in FIG.
And the N-type diffusion region 15b constitutes the drain electrodes of the N-channel transistors 7a and 7b in FIG. The P-type diffusion regions 14a and 14c are electrically connected to the VDD wiring 8a made of the first layer aluminum through the contact hole 10, and the N-type diffusion regions 15a and 15c are made of the first layer aluminum through the contact hole 10. It is electrically connected to the GND wiring 8b. Gate polysilicon 12a, 12b,
13a and 13b are electrically connected through a contact hole 10 to a signal wiring 8e made of a first layer of aluminum. Signal wiring
8e is electrically connected to the signal wiring 9a made of the second layer aluminum through the through hole 11, and this signal wiring 9a constitutes a connection line to the input terminal A in FIG. P type diffusion region 14b
Is electrically connected to the signal wiring 9b made of the second layer aluminum through the contact hole 10, the signal wiring 8c made of the first layer aluminum, and the through hole 11, and the N-type diffusion region 15b is connected to the contact hole 10, the first layer. Signal wiring 8d made of aluminum,
It is electrically connected to the signal wiring 9b through the through hole 11, and the signal wiring 9b constitutes a connection line to the output terminal B in FIG. In addition, a cell frame 16 is provided at a position separated from the layout data inside the cell by a predetermined distance so that the layout design is not violated no matter how the cells are arranged.

Next, a mask data creating procedure of such a cell-based integrated circuit device will be described with reference to FIG. According to the logical connection information for realizing a desired logic function, a desired cell is selected from a cell library prepared in advance and automatically arranged in the internal area 3, and a macro cell is arranged. The various cells are arranged with their cell frames 16 in contact with each other. As an example of such arrangement processing, FIG.
FIG. 7 shows a layout pattern in which two inverter circuits (cells 20 and 30) whose load driving capacity shown in FIG. Note that, in FIG. 7, the parts given the same numbers as in FIG. 5 indicate the same parts. After performing the placement process, automatic wiring between cells is performed to obtain layout pattern data of a cell-based integrated circuit device that realizes a desired logic function. Then, mask data for the manufacturing process is created from the obtained layout pattern data.

[0009]

In the layout process of the conventional cell-based integrated circuit device, various cells are arranged so that the cell frames provided at positions separated from the internal layout data by a predetermined distance are in contact with each other. is doing. Therefore, even if there are diffusion regions of the same potential at the ends of adjacent cells, a region for separating each diffusion region in each cell is necessary, and such a region is present at all points where the cells touch. Since it is always present, it occupies a large layout area, which causes a problem of increasing the area of the integrated circuit device and countering high integration.

The present invention has been made in view of the above circumstances, and provides a layout method of an integrated circuit device which can reduce a layout area of the integrated circuit device and obtain a cell-based integrated circuit device having a high degree of integration. The purpose is to do.

[0011]

According to the method of laying out an integrated circuit device according to the present invention, when there is a diffusion region of the same potential at the end of an adjacent cell when arranging the cells, the diffusion region of the same potential is used. The cells are rearranged so that they overlap.

[0012]

In the present invention, a desired plurality of cells are once arranged,
After this arrangement, the cells are arranged again so that the diffusion regions of the same potential existing at the ends of the adjacent cells overlap. By doing so, the layout area is reduced by the amount of overlap, and the degree of integration is increased.

[0013]

EXAMPLES Examples of the present invention will be specifically described below.

FIG. 8 is a flowchart showing a mask data creating procedure of the cell-based integrated circuit device using the present invention. First, logic design is performed using logic symbols (for example, symbols of inverter circuits as shown in FIG. 3) so as to realize desired functions. According to the logical connection information which is the result of this logic design, a desired cell is selected from a cell library prepared in advance, and the selected various cells are stored in the internal area 3 of the integrated circuit device 1 as shown in FIGS. To automatically place. At this time, as in the conventional case, the various cells are arranged with the cell frame 16 in contact with each other. After automatic placement, if there is a diffusion area of the same potential at the edge of adjacent cells,
The cells are rearranged so that the diffusion regions of the same potential overlap. After performing the placement process as described above, automatic wiring between cells is performed to obtain layout pattern data of a cell-based integrated circuit device that realizes a desired logic function. Then, mask data for the manufacturing process is created from the obtained layout pattern data.

Next, the cell rearrangement, which is the gist of the present invention, will be specifically described with reference to the drawings.

(First Embodiment) An example will be described in which the present invention is applied to the case where the above-mentioned inverter circuits whose load driving capacity is twice the standard are arranged side by side. First, as shown in FIG. 7, the inverter circuits are arranged side by side with the cell frame 16 in contact with each other by automatic arrangement. In this embodiment, the cells are rearranged after this. Of the cells arranged next to each other, the P-type diffusion region at the right end of the cell 20 arranged on the left side
When the 14c, N-type diffusion region 15c and the P-type diffusion region 14a, N-type diffusion region 15a at the left end of the cell 30 arranged on the right side are electrically at the same potential, the cell 20 arranged on the left side is Cell frame 16
The left side of the cell frame 16 of the cell 30 arranged on the right side is moved to the middle position of the contact hole 10 by moving the right side of the The cells 30 on the right side are rearranged so that the cell frames 16 of are contacted with each other, and the diffusion regions are made common. FIG. 9 shows the layout pattern after rearrangement. Common P-type diffusion region
A common N-type diffusion region 15 is formed. Further, in this embodiment, since the diffusion regions are made common in this way, the layout area is reduced as is apparent from comparison with the conventional example (see FIG. 7). Although illustration is omitted, the same rearrangement is performed for the cells arranged further to the right of the rearranged right cell 30. Thereafter, in the same manner, all the cells arranged in the internal area of the integrated circuit device 1 are rearranged if the rearrangement conditions are satisfied.

In the above example, the cell frame 16 is moved to the midpoint position of the contact hole 10 and
Although the rearrangement is performed so that the 10 overlap, the cell frame 16 may be moved to any position from the position in contact with the diffusion region to the midpoint position of the contact hole 10 to perform the rearrangement.

(Second Embodiment) In the first embodiment described above,
The case where the diffusion regions sandwiching the isolation region between the adjacent cells have the same electric potential has been described. For example, the diffusion region at the right end of the cell arranged on the left side and the diffusion region at the right end of the cell arranged on the right side are described. The present invention can be applied to the case where and are electrically the same potential. Such an example will be described below as a second embodiment.

FIG. 10 shows a layout pattern after the automatic arrangement of the inverter circuits side by side with the cell frame 16 in contact with each other. The cell 40 arranged on the left side is an inverter circuit having the same load driving capacity as that of the cells 20 and 30 described above, which is double the standard, and the cell 50 arranged on the right side is a normal inverter circuit (one by one). 4 is a circuit in which the P-channel transistor 6b and the N-channel transistor 7b are removed in FIG. 4). Even in such an example, the P-type diffusion region of the cell 40 on the left side
14c, N-type diffusion region 15c and P-type diffusion region 14 of the cell 50 on the right side
When the a and N type diffusion regions 15a have the same electric potential, the cell 50 on the right side is rearranged so as to overlap them. FIG. 11 shows the layout pattern after rearrangement. A common P-type diffusion region 14 and a common N-type diffusion region 15 are formed. In addition, in the present embodiment, the conventional example (see FIG.
The layout area can be reduced, as is clear from the comparison with (1).

[0020]

As described above, according to the layout method of the integrated circuit device of the present invention, when the diffusion regions of the same potential are present at the ends of the adjacent cells after the arrangement, the cells are re-aligned so that these diffusion regions overlap. Since they are arranged, the present invention has excellent effects such as reducing the layout area and obtaining an integrated circuit device having a high degree of integration.

[Brief description of drawings]

FIG. 1 is a main schematic diagram showing the configuration of a polycell type cell-based integrated circuit device.

FIG. 2 is a main schematic diagram showing the configuration of a building block type cell-based integrated circuit device.

FIG. 3 is a symbol diagram of an inverter circuit in which the load driving capability is double the reference.

FIG. 4 is a transistor circuit diagram of an inverter circuit in which the load driving capability is double the reference.

FIG. 5 is a main schematic diagram of a layout pattern of an inverter circuit in which the load driving capability is twice as large as the reference.

FIG. 6 is a flowchart of mask data creation of a conventional cell-based integrated circuit device.

FIG. 7 is a diagram showing a layout pattern of a conventional cell-based integrated circuit device.

FIG. 8 is a flowchart of mask data creation of the cell-based integrated circuit device according to the present invention.

FIG. 9 is a diagram showing a layout pattern of a cell-based integrated circuit device according to the present invention.

FIG. 10 is a diagram showing a layout pattern of a conventional cell-based integrated circuit device.

FIG. 11 is a diagram showing a layout pattern of a cell-based integrated circuit device according to the present invention.

[Explanation of symbols]

 1 Integrated circuit device 14,14a, 14b, 14c P-type diffusion region 15,15a, 15b, 15c N-type diffusion region 20, 30, 40, 50 cells

Continued Front Page (72) Inventor Isao Takimoto 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation Custom LSI Design Technology Development Center

Claims (1)

[Claims] 1. A method of laying out an integrated circuit device according to a cell-based method using a cell prepared in advance having a diffusion region, the step of arranging the cell prepared in advance, and the cells being adjacent to each other after the arranging step. A layout of the integrated circuit device, which includes the step of rearranging the cells so that the diffusion regions having the same potential are overlapped with each other when the potentials of the diffusion regions adjacent to each other are equal. Method.