JP2000040810A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid illegal circuit copy of a circuit mounted on a gate array by comprising a plurality of kinds of master chips different in layout of basic cells for a dummy circuit incorporating normally on- and off-type transistors and changing over these master chips in use. SOLUTION: A plurality of kinds of master chips different in layout of basic cells D for dummy circuits are prepared and changed over for use by, for example, developed model or lot. By changing over the master chips, the layout pattern of the basic cells D for dummy circuits in the master chip is diversified, compared with the case where the master chip is single. It is difficult to analyze a circuit mounted on a gate array by discriminating the basic cells D for dummy circuits from the actual chip and the illegal circuit copy can be more strictly avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of preventing illegal circuit copying of a circuit mounted on a gate array.

[0002]

2. Description of the Related Art FIGS. 7 and 8 show an example of a circuit and a layout pattern of a basic cell of a conventional gate array. In FIG. 7, N1 and N2 are N-type MOS transistors (hereinafter referred to as N-type transistors), and P1 and P2 are P-type MO transistors.
This is an S transistor (hereinafter referred to as a P-type transistor).

In FIG. 8, N + is an N-type transistor N
An N + diffusion region forming the source and drain of 1, N2,
P + is a P + diffusion region forming sources and drains of the P-type transistors P1 and P2, and PLY is polysilicon forming a gate of each transistor. This basic cell is N
-Type transistors N1 and N2 and P-type transistor P
1 and P2, the circles in the circuit diagram of FIG. 7 are terminals that can be drawn out of the basic cells, and a desired circuit is formed by wiring between the terminals of the basic cells arranged in an array.

[0004]

However, in a conventional gate array, a circuit is constituted by basic cells and wiring arranged regularly in an array, and the layout pattern is very simple. However, by analyzing the structure of the basic cells and the wiring between the basic cells from the layout pattern of the actual chip, there is a problem that the circuit mounted on the gate array can be easily copied.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a semiconductor device capable of preventing an illegal circuit copy of a circuit mounted on a gate array.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention has a dummy cell basic cell in which always-on and always-off transistors are incorporated in a basic cell of a gate array. A semiconductor device comprising a plurality of types of master chips having different cell arrangements.

[0007]

According to the semiconductor device of the present invention, a plurality of types of master chips having different arrangements of dummy circuit basic cells incorporating always-on and always-off transistors are provided, and the master chips are switched for each development model or lot. ,
This makes it difficult to analyze a real chip, thereby preventing illegal circuit copying of a circuit mounted on the gate array.

[0008]

Embodiments of the present invention will be described below. FIGS. 1 and 2 show an example of a circuit and a layout pattern of a basic cell for a dummy circuit used in the present invention.
In FIG. 1, N1 and N2 are N-type transistors, P1,
P2 is a P-type transistor, and transistors N1 and P1 surrounded by broken lines are always-on or always-off transistors having threshold voltages different from normal. By using one or more dummy circuit basic cells and wiring the transistors of each cell according to the circuit, a dummy circuit having a different logic operation from the circuit analyzed from the apparent layout pattern of the actual chip is formed. can do. Further, a dummy circuit can be formed by using a dummy circuit basic cell and a normal basic cell together.

In FIG. 2, N1 + and N2 + are N + forming sources and drains of N-type transistors N1 and N2.
The diffusion regions P1 + and P2 + are P-type transistors P1 and P2.
P + diffusion region forming the source and drain of P2, PLY
Is polysilicon forming the gate of each transistor. N1 + and P1 + indicated by broken lines are N + and P + diffusion regions having different impurity concentrations from those of the normal region, and form transistors N1 and P1 that have a threshold voltage different from the normal and are always on or always off. N2 + and P2 + are N + and P + diffusion regions forming normal transistors N2 and P2.

The arrangement pattern of always-on and always-off transistors in a dummy circuit basic cell is shown in FIG.
The present invention is not limited to the example shown in FIG. 2, and may be any type. For each transistor, any type of always-on type, always-off type or normal transistor may be selected to form a dummy circuit basic cell. For example, the diffusion region N2 in FIG.
+ And P2 + are also diffusion regions having different impurity concentrations from normal,
Transistors N1 and N2 are always on, transistor P
1 and P2 may be of the always-off type to constitute a dummy circuit basic cell. In addition, one to three transistors of the four transistors in FIGS. 1 and 2 may be configured as always-on or always-off transistors to form a dummy circuit basic cell. The structure of the dummy circuit basic cell is not limited to the examples shown in FIGS. 1 and 2, but may be, for example, transistors N1, P1 and N2.
A structure in which the gates of P2 are separated may be used, and the transistor configuration is not limited to a four-transistor configuration, but may be another transistor configuration such as a six-transistor configuration.

FIGS. 3 and 4 show examples of the configuration of a dummy circuit using the dummy circuit basic cells described above. In the following description, the threshold voltage of an always-on P-type transistor is described as “higher than normal” because it has a more positive value than a normal P-type transistor. Has been described as "lower than normal" because the threshold voltage has a value in the minus direction as compared with a normal P-type transistor. In FIGS. 3 and 4, the always-on and always-off transistors are surrounded by broken lines.

FIG. 3 shows an example of a dummy circuit of a NAND gate.
Shown in In FIG. 3, N1 and N2 are N-type transistors, and P1 and P2 are P-type transistors, which are circuits that usually constitute NAND gates for inputs A, B and output C. In the circuit shown in FIG. 3, the threshold voltage of the N-type transistor N1 is set lower than usual to be always on, and the threshold voltage of the P-type transistor P1 is set lower than usual to be always off so that the actual Although the apparent layout pattern of the chip is a NAND gate for inputs A, B and output C, a dummy circuit that actually operates as an inverter for input B and output C can be configured.

FIG. 4 shows an example of a NOR gate dummy circuit. In FIG. 4, N1 and N2 are N-type transistors,
P1 and P2 are P-type transistors.
This circuit constitutes a NOR gate of B and output C. FIG.
In this circuit, the threshold voltage of the N-type transistor N1 is set higher than usual so that the normally-off type and the P-type transistor
By setting the threshold voltage of 1 higher than usual and making it always on, the NOR gates of inputs A, B and output C can be obtained in the apparent layout pattern of the actual chip.
Actually, a dummy circuit that operates as an input B and output C inverter can be configured.

If an appropriate dummy signal causing a malfunction is connected to the input A of the dummy circuit shown in FIGS. 3 and 4, the original circuit operates as an input B and output C inverter. Circuits analyzed from the apparent layout pattern include NAND gates of inputs A and B and output C,
Since it operates as a NOR gate, normal operation becomes difficult. By configuring the dummy circuit shown above using dummy circuit basic cells and mixing the dummy circuit with the circuit mounted on the gate array, the circuit analyzed from the actual chip differs in logic operation from the original circuit. Since it does not operate normally, illegal circuit copy can be prevented.

FIG. 5 shows a first embodiment of the present invention using the dummy circuit basic cell and the dummy circuit described above. FIG. 5 shows a master chip of a gate array in which basic cells are arranged in an array. The cell indicated by D is a basic cell for a dummy circuit in which always-on and always-off transistors are incorporated. In FIG. 5, A and B are master chips of the same type having the same number of mounted basic cells, but different in arrangement of the dummy circuit basic cells D. According to the present invention, when the above-described dummy circuit is mounted on the gate array, a plurality of types of master chips having different arrangements of basic cells for the dummy circuit are prepared as shown in FIG. It is switched and used for each model and lot. By switching the master chip, the layout pattern of the dummy circuit basic cells in the master chip is diversified compared to the case of a single master chip, and the dummy circuit basic cells are determined from the actual chip and mounted on the gate array. It becomes more difficult to analyze the copied circuit, and illegal circuit copying can be more strictly prevented.

FIG. 6 shows a second embodiment of the present invention. In this embodiment, a plurality of types of dummy circuit basic cells D1, D
2 and D3, a plurality of types of master chips A and B having different arrangements of the plurality of types of dummy circuit basic cells are prepared, and these master chips are switched and used. By switching the master chip, the layout pattern of the basic cells for the dummy circuit in the master chip can be further diversified, the analysis of the actual chip becomes more difficult, and the illegal circuit copy can be prevented even more severely.

[0017]

According to the present invention as described above,
In a gate array, a plurality of types of master chips having different arrangements of basic cells for dummy circuits incorporating always-on and always-off transistors are provided. By switching between these master chips, a circuit mounted on the gate array can be used. Unauthorized circuit copy can be prevented,
Its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a circuit of a dummy circuit basic cell used in the present invention.

FIG. 2 is a layout diagram showing an example of a layout pattern of a basic cell for a dummy circuit used in the present invention.

FIG. 3 is a circuit diagram showing an example of a dummy circuit used in the present invention.

FIG. 4 is a circuit diagram showing an example of a dummy circuit used in the present invention.

FIG. 5 is an explanatory diagram of the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a basic cell of a conventional gate array.

FIG. 8 is a layout diagram of a basic cell of a conventional gate array.

[Explanation of symbols]

 N1, N2... N-type transistor P1, P2... P-type transistor N +, N1 +, N2 +... N + diffusion region P +, P1 +, P2 +.

Claims (2)

[Claims] 1. A semiconductor device comprising a dummy circuit basic cell in which always-on and always-off transistors are incorporated in a basic cell of a gate array, and a plurality of types of master chips having different dummy circuit basic cell arrangements. A semiconductor device characterized by the following. 2. The semiconductor device according to claim 1, further comprising a plurality of types of dummy circuit basic cells having different arrangement patterns of the always-on type and always-off type transistors, and arranging the plurality of types of dummy circuit basic cells. A plurality of types of master chips different from each other.