JP2671883B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for improving the degree of integration of semiconductor integrated circuit devices, especially large-scale integrated circuit devices.
The present invention relates to improvement of circuit cell arrangement by a so-called standard cell method. The progress of large-scale semiconductor integrated circuit devices (hereinafter abbreviated as LSI) and the speed of expansion and diversification of systems using them are increasing more and more. How to make the logic circuit part of the system into LSI The problem is that it determines the most basic part of the performance and price of the system hardware, and has a great influence on the performance of the entire system as its feedback. It was a serious concern. In order to realize a higher-level LSI under the constraint conditions such as system diversification, shortening of development period, and improvement of economic efficiency, a gate array method is used as a means for converting a logic circuit into a custom LSI. The standard cell method has been introduced. The gate array method is a method in which a silicon wafer is stocked in a state where a bulk pattern (a diffusion region such as a transistor element that constitutes a circuit cell) has been formed, and circuit connection is performed according to the customer's request to complete an LSI. Therefore, the number of mask layers to be customized is about 1/3 of the total number of masks used for LSI manufacturing. The standard cell method is, for example, NAND (NAND), NOR (NOR),
A pattern of a unit circuit such as an inverter or a flip-flop is designed in advance, registered as a library, and called a cell. The design of the entire chip is based on the functional requirements of the customer.
ter Aided Design) method,
All layers of the mask are customized. The advantage of the standard cell system is that (a) the pattern information and electrical characteristic information that the chip designer should consider are much less than in the conventional pure custom design, and at the same time, this information is stored in CAD. Since it is organized in a library that is easy to mount, it is possible to design the entire LSI chip with good controllability. (B)
In connection with the above advantages, it is easy to prevent chip design errors, and (c) the chip area is used more efficiently than the gate array method. As described above, the standard cell method has a high degree of freedom and eliminates the conventional LSI bottleneck such as the possibility of realizing the LSI design work without the need for specialized knowledge of circuit element design and the dispersion of development risk. It is expected as a means, and in order to make more effective use of such advantages, it is required to increase the degree of integration more than ever before. As described above, in the standard cell system, cells in which patterns of gates and other unit circuits are designed in advance are prepared as a standardized library. Figure 4 (a)
Uses a complementary MOS field effect transistor (hereinafter, abbreviated as C-MOS FET) as an example of a cell.
A completed pattern of the input NAND gate is shown, and FIG. 4B is an equivalent circuit diagram thereof. As shown in FIG. 4 (a), assuming that the cell frame that defines the contour of the cell is shown by a broken line, each element forming the cell is inside the cell frame, and each node (connection point) is on the cell frame. Located in. In the example shown in the figure, the hatched pattern is aluminum (Al) wiring, B _VDD is a positive potential power supply line, B _VSS is a ground potential power supply line, and I
Reference numerals ₁ and I ₂ denote an input wiring and a gate electrode, which are made of an impurity diffusion layer. Incidentally O _T indicates the output node. A mask pattern for each process such as diffusion and wiring necessary for forming a completed pattern as in the above example of each cell is designed, and a library is provided as a set of mask pattern information having the same cell frame. Be registered with. L
At the design stage of the SI chip, the designer does not go back to the pattern in the cell, and if he / she selects this by the name of the cell and decides the layout, the required pattern can be obtained as a computer output. In the conventional manufacturing method, when arranging the cells, the cell frames of adjacent cells (shown by broken lines in the drawing) are matched as shown in FIG. In this conventional example, cell 1 is a 3-input NAND gate, cell 2 is a 4-input NAND gate,
The content of the pattern is similar to that of the 2-input NAND gate, but the pattern shapes of the power supply wiring connection regions (abbreviated as power supply terminal portions) 1 and 2 (shown by broken lines) having the same function in both cells are unique. Is designed to. The standard cell type LSI design performed by the procedure described above is as follows:
The application is gradually expanded due to the advantages as described above, but the degree of integration obtained by this does not reach the method of designing and wiring in units of elements such as transistors called the specific function method, and the standard cell There is a demand for a semiconductor integrated circuit device that retains the advantages of the method and has a higher degree of integration than before. The problem is that a plurality of circuit cells are arranged on a substrate, and a first circuit cell of the plurality of circuit cells has a first logic function. A first bulk pattern forming a predetermined element group forming a logic circuit is provided, and the first bulk pattern has a first power supply wiring connection region on at least one side of the first circuit cell. The second circuit cell of the plurality of circuit cells is the second circuit cell.
Has a second bulk pattern forming a predetermined element group forming a logic circuit having the logic function of, and the second bulk pattern has a second power supply on at least one side of the second circuit cell. A third circuit cell of the plurality of circuit cells has a wiring connection region, and a circuit cell of the same pattern as the first circuit cell and a circuit cell of the same pattern as the second circuit cell are adjacent to each other on the substrate. At least some of the circuit cells having the same pattern as the adjacent first circuit cell and the circuit pattern having the same pattern as the second circuit cell adjacent to each other share the respective power supply wiring connection regions. This is solved by the standard cell type semiconductor integrated circuit device. According to the present invention, the area occupied by the substrate is reduced by partially overlapping the cell frames of the adjacent cells in the vicinity of their sides so that the power supply wiring connection region is shared between the adjacent cells of different types. Decrease and increase integration. However, the cells sharing the power supply wiring connection region may have different functions from each other, or may be cells having the same function, for example, having structures in which patterns are inverted from each other. The power supply wiring connection region is a region for connecting and applying a non-grounded or grounded power supply potential to each element such as a transistor. In addition to the connection with the bus line crossing over the cell, the source of the transistor element, A pattern for connecting the drain region and the like, a pattern for connecting to the semiconductor substrate and the like are included, and the above-mentioned sharing is usually possible without impairing the function. According to the present invention, when designing the pattern of each cell, such a pattern of the power supply terminal portion is standardized to enable the superposition, and the information for displaying the pattern area is used as the cell information. Add it. When designing an LSI chip, the information for displaying the overlapping area of the selected cell is used, and if necessary, an operation such as pattern inversion is added to superimpose the overlapping area portion. Place cells. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings with reference to the accompanying drawings. FIG. 1 shows an embodiment of the present invention corresponding to the conventional example shown in FIG. 5, in which cell 1 is a 3-input NAND gate and cell 2 is a 4-input NAND gate.
The cells 1 and 2 are arranged so as to partially overlap each other as shown in the figure. The overlapped regions are the power supply terminal portions 1 and 2 for connecting the power supplies V _DD and V _SS to the semiconductor substrate or the like, and there is no functional problem even if they are shared between adjacent cells. In the prior art example shown in FIG. 5, the pattern shape of the power supply terminal portion is not unified in the cell 1 and the cell 2, whereas in the present invention, it is a standardized pattern common to different cells. Allows superposition, and
Information for displaying the power supply terminal portion is added to the pattern information and registered in the library in advance. When the two cells are arranged adjacent to each other,
Although the standardized power supply terminal portions are overlapped, this processing can be performed without tracing back to the pattern inside the cell, as in the conventional standard cell method.
Also, the figure shown by the solid line in FIG. 2 (a) is the C used in the present invention.
An example of a completed pattern of a MOS inverter cell is shown. The pattern shown by the solid diagonal lines is Al wiring, B _VDD is a positive potential power supply line, B _VSS is a ground potential power supply line, G _A is a gate electrode and wiring, and O _T Indicates an output node. When the two cells are arranged adjacent to each other,
According to the present invention, one cell is inverted as shown in FIG. 2 (b) and the power supply terminal portions 1 and 2 shown by broken lines in FIG. As described above, by sharing the power supply terminal portion between the adjacent cells, by comparing FIG. 1 and FIG. 5, or by comparing with the conventional arrangement indicated by a broken line in FIG. 2 (b) and FIG. 2 (a). As is clear from the comparison of the above, the reduction of the used area of the wafer is realized. FIG. 3 is a plan view showing another embodiment of the present invention. In this embodiment, the cell 3 is an inverter,
The cell 4 is a 2-input NAND, the cell 5 is a 2-input NOR, and the cell 6 is a 3-input NAND. The cells 3 and 4 and the cells 5 and 6 share the power supply terminal portion as in the above embodiment. There is. Even when cells having different functions are adjacent to each other as in the present embodiment, the present invention can be applied to reduce the wafer use area. In each of the above embodiments, the C-MOS is used.
Although a cell having an FET as an element is targeted, since the supply of the power supply potential is common to the semiconductor integrated circuit device regardless of the structure of the transistor element, the present invention is a semiconductor integrated circuit having a transistor element having an arbitrary structure. It can be applied to the standard cell design of circuit devices. As described above, according to the present invention, the use area of the wafer is maintained without impairing the characteristics of the standard cell system and without increasing the load on the manufacturing process unlike the reduction of the pattern size. Can be reduced, and a great effect can be obtained in improving the degree of integration of a semiconductor integrated circuit device, particularly a logic circuit device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a first embodiment of the present invention. FIG. 2 is a plan view showing a second embodiment of the present invention. FIG. 3 is a plan view showing a third embodiment of the present invention. FIG. 4 is a plan view showing an example of a cell. FIG. 5 is a plan view showing a conventional cell arrangement. Power lines I ₁ of the power supply line B _VSS ground potential of the Reference Numerals] B _VDD positive _{potential, I 2, I 3, I} 4 input nodes O _T output node G _A gate electrode and the wiring 2 power supply wiring connection area ( Power supply terminal)

Claims (1)

(57) [Claims] A first bulk pattern in which a plurality of circuit cells are arranged on a substrate, and a first circuit cell of the plurality of circuit cells forms a predetermined element group forming a logic circuit having a first logic function. The first bulk pattern has a first power supply wiring connection region on at least one side of the first circuit cell, and the second circuit cell of the plurality of circuit cells is a second circuit cell. A second bulk pattern forming a predetermined element group forming a logic circuit having a logic function of, and the second bulk pattern having a second power supply on at least one side of the second circuit cell. A wiring connection region, and a third circuit cell of the plurality of circuit cells is the first circuit cell.
Circuit cell having the same pattern as the circuit cell and the second circuit
A circuit cell having the same pattern as the cell is arranged adjacent to each other on the substrate, and is the same as the adjacent first circuit cell.
Same pattern as one pattern circuit cell and the second circuit cell
A standard cell type semiconductor integrated circuit device, wherein at least some of the circuit cells of the standard cell system share respective power supply wiring connection regions.