JPH05243378A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the development cost and the development period of the title integrated circuit in a redesigning operation by a method wherein fundamental cells according to a gate array system are inserted into a cell row according to a standard system, only a process after a wiring process is changed and a circuit correction operation is executed. CONSTITUTION:Fundamental cells 7 according to a gate array system are arranged in unarranged regions 9 in a cell row 8 in which standard cells 6 have been arranged in the transverse direction. The standard cells 6 and the fundamental cells 7 are arranged in such a way that both of them are provided with power-supply interconnections on the side of a high-potential side and with those on the side of a low potential in identical positions. When a feedthrough cell through which an interconnection is passed is installed at the inside of the standard cell row 8, the fundamental cells 7 are arranged also in its region. It is possible to comply with the change and the correction of the title integrated circuit after its trial production when a wiring operation is executed to the fundamental cells 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit designed by the standard cell system.

[0002]

2. Description of the Related Art There are a gate array system and a standard cell system as means for designing a semi-custom semiconductor integrated circuit. The former is a method of producing a semiconductor integrated circuit by performing a wiring process on a wafer on which basic cells are arranged in a matrix after the diffusion process is completed. Although this method has an advantage that the design and production TAT can be shortened, it has a drawback that the integration degree does not increase and the performance is inferior.

On the other hand, the standard cell method is a method of arranging registered functional blocks designed at the same height and wiring them to each other. Unlike the gate array method, the manufacturing process also includes diffusion processing. , Especially in terms of manufacturing TA
T becomes longer. However, since each functional block is optimized and uniquely designed, high density is possible and good characteristics can be expected.

[0004]

In the conventional standard cell method, a highly integrated and high performance integrated circuit can be realized, but when the circuit is modified after the trial manufacture, the trial manufacture must be repeated from the first diffusion step. Since it disappears, there is a problem that the delay of TAT at the time of re-trial production is large and the development cost is remarkably increased. Therefore, the object of the present invention is to maintain the advantages of the standard cell method,
It is to make it possible to easily modify a circuit without requiring a large number of steps.

[0005]

A semiconductor integrated circuit according to the present invention has a plurality of standard cell rows in which a plurality of standard cells each having a specific logic function are arranged, and one or more standard cell rows are arranged. In the standard cell column of, the basic cell is arranged between the standard cells and / or at the end of the standard cell column, and a basic cell capable of realizing a specific logic function is arranged by wiring.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. 1A and 1B are layout diagrams of a standard cell (functional block) and a basic cell used in an embodiment of the present invention, respectively. Figure 1 (a)
As shown in FIG. 1, the standard cell 6 includes a first Al region 1, a second Al region 2, a p-type diffusion region 3, and an n-type diffusion region 4.
Further, a polysilicon electrode 5 is provided, and a 2-input CMOS NOR gate is formed here.

The wirings in the first Al region 1 on the upper and lower sides of the cell are wirings which give the highest potential and the lowest potential,
This wiring is set to the same position and the same width as the wiring of the same type of other standard cells. Therefore, when standard cells are arranged side by side, the highest and lowest potential wirings are connected.

FIG. 1B shows a basic cell 7 of a CMOS type gate array which is composed of a first Al region 1, a p-type diffusion layer 3, an n-type diffusion layer 4 and a polysilicon electrode 5.
It is shown. The first Al region 1 that gives the highest potential and the lowest potential of the basic cell 7 is also set to the same position and width as that of the standard cell.

In the present invention, design is performed using these two types of cells. First, at the time of the initial design, standard standard cell type cell 6 is used to perform normal standard cell type cell placement and routing. However, all the standard cell rows 8 generated at the time of design do not have the same width, and therefore, unarranged regions 9 are formed at both ends of some cell rows 8 as shown in FIG. In this embodiment, the above-mentioned basic cell 7 is arranged in this non-arranged region 9.

By arranging in this way, even when it is necessary to add a functional block for changing or modifying a circuit after trial manufacture, wiring is performed using the basic cells 7 arranged at both ends of the cell row 8. It can be handled only by modifying after the process.

FIG. 3 is a layout diagram showing a second embodiment of the present invention. In the figure, 10 is a wiring area, and 11
Is a pad, and 12 is an I / O buffer. Normally, when using the standard cell type placement / wiring program,
It requires dummy data called feedthrough cells. That is, it is a cell for passing a wire in the second Al region, and a power supply wire for connecting the highest and lowest potential wires between the cells at both ends of the standard cell when the interval between the standard cells is widened is arranged in this cell. ..

In the second embodiment of the present invention, as shown in FIG. 3, the basic cells 7 are arranged at both ends of the standard cell row, and the basic cells 7 are arranged inside the standard cell row 8. Used as a feedthrough cell. With such a configuration, it is possible to arrange a larger number of basic cells 7 than in the first embodiment, and the degree of freedom in design is increased, so that the modification of the circuit by the addition of the functional block is further facilitated. It will be easier.

[0013]

As described above, according to the present invention, the unarranged region at the end of the cell row in which the standard cell type logic cell having a small element area is arranged and the inside of the cell row for passing the wiring are provided. Since the gate array type basic cell is arranged in the area of the feedthrough cell, according to the present invention, a high-density and high-performance integrated circuit can be obtained, and the circuit modification after trial manufacture changes the wiring. This is possible only by reducing the development cost and TAT at the time of redesign.

[Brief description of drawings]

FIG. 1 is a layout diagram of standard cells and basic cells used in an embodiment of the present invention.

FIG. 2 is a layout diagram showing a first embodiment of the present invention.

FIG. 3 is a layout diagram showing a second embodiment of the present invention.

[Explanation of symbols]

1 ... 1st Al area | region, 2 ... 2nd Al area | region, 3 ... p
Type diffusion layer, 4 ... N type diffusion layer, 5 ... Polysilicon electrode, 6 ... Standard cell, 7 ... Basic cell,
8 ... Standard cell row, 9 ... Unplaced area,
10 ... Wiring region, 11 ... Pad, 12 ... I /
O buffer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9169-4M H01L 21/82 M

Claims (1)

[Claims] 1. A standard cell row in which a plurality of standard cells each having a specific logic function are arranged,
In a semiconductor integrated circuit in which a plurality of semiconductor integrated circuits are arranged via a wiring region, in one or a plurality of standard cell rows, wiring is provided between standard cells and / or at the end of the standard cell row to provide a specific logical function. A semiconductor integrated circuit in which achievable basic cells are arranged.