JP4964929B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a structure of a basic collective element incorporated in a large-scale semiconductor integrated circuit, and more particularly to a cell-based basic collective element.

  Semi-custom LSIs are roughly classified into PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), gate array, and cell-based system (also called standard cell).

  Here, the gate array can realize a desired LSI by arranging basic cells constituting a gate on a semiconductor substrate regularly in a grid pattern and wiring according to a user's circuit. FIG. 16 shows a plan view of the gate array. In this gate array, the interval between the gate wirings 100 is uniform because of its configuration (the gate pattern (gate shape) is uniform). A transistor can be formed by the n-type impurity diffusion region, the gate wiring 100, and the adjacent n-type impurity diffusion region. A plurality of n-type impurity diffusion regions adjacent to each other through these gate wirings 100 are referred to as n-type active regions 101. Similarly, a plurality of p-type impurity diffusion regions are referred to as p-type active regions 102. In order to connect a plurality of transistors formed by the gate wiring 100, the n-type active region 101, and the p-type active region 102, the gate wiring 100, the n-type active region 101, and the p-type active region 102 include A contact hole 103 is formed.

  On the other hand, in the cell-based method, a complex circuit such as a CPU, a memory, an A / D converter, or a micro cell is prepared as a standard basic set element in advance, and these are selected according to a function requested by the user. By combining them, a desired LSI can be realized. FIG. 17 shows a plan view of the cell base method. In this cell-based method, the gate pattern (gate shape) of the gate wiring 104 on the active region may be non-uniform. As a result, the cell base method can effectively use the area in one chip as compared with the gate array. Here, a transistor can be formed using the n-type impurity diffusion region, the gate wiring 104, and the adjacent n-type impurity diffusion region. A plurality of n-type impurity diffusion regions adjacent to each other through these gate wirings 104 are referred to as n-type active regions 105. Similarly, a plurality of p-type impurity diffusion regions are referred to as p-type active regions 106. In order to connect a plurality of transistors formed by the gate wiring 104, the n-type active region 105, and the p-type active region 106, the gate wiring 104, the n-type active region 105, and the p-type active region 106 include A contact hole 107 is formed.

  In the cell-based method described above, the gate pattern (gate shape) of the gate wiring 104 on the n-type active region 105 or the p-type active region 106 may be configured unevenly. In this case, since the gate wiring 104 has a non-uniform gate pattern (gate shape), the finish of the gate pattern (gate shape) is kept at a uniform value by performing complicated CAD processing at the time of mask creation. It was. However, this CAD processing has a problem that enormous time and cost are required for the processing.

  Further, as a method for avoiding the above-described difficulty and maintaining the finish of the gate pattern (gate shape) at a uniform value, there is a method of uniformly designing the gate pattern (gate shape) on the active region. However, in the conventional cell-based method, the uniformity of the gate pattern (gate shape) cannot be obtained depending on the necessity / unnecessity of the contact hole on the active region as shown in FIG. In order to make the gate pattern (gate shape) uniform, a method of enlarging the p-type active region 106 as shown in FIG. 18 is conceivable. However, in this method, the area of the p-type active region 106 is increased. There is a problem of increasing the area occupied by the basic assembly element.

  Therefore, the present invention has been made to solve the above-mentioned problems, and can maintain a uniform gate pattern (gate shape) finish after the wafer process without complicated CAD processing, increasing the occupied area. An object of the present invention is to provide a semiconductor integrated circuit including a basic set element that is not allowed to be generated.

  According to a first aspect of the present invention, there is provided a cell-based semiconductor integrated circuit comprising: a first active region and a second active region formed on a semiconductor substrate side by side in a first direction; First intervals that are arranged side by side in a second direction intersecting the first direction on the active region and the second active region, and are uniform in design in the second direction on the first active region and the second active region, respectively. The first active region has a first protrusion protruding in the first direction, and at least a part of the first protrusion is included in the plurality of gate lines. Formed in a lower layer region between two adjacent gate wirings, a first contact hole is formed in the first projecting portion, and a plurality of gate wirings arranged in the second direction on the first active region, A gate wiring formed at one end in the second direction and the first direction of the first active region The second interval, which is the shortest interval with the side closer to the gate wiring at one end of the two sides extending to, is wider than the first interval, and the gate wiring formed at one end in the second direction; A second contact hole is formed between the two sides extending in the first direction of the active region and the side closer to the gate wiring at one end.

  According to a second aspect of the present invention, there is provided a semiconductor integrated circuit according to the first aspect, wherein the second active region has a second projecting portion projecting in the first direction. At least a part of the plurality of gate wirings is formed in a lower layer region between two adjacent gate wirings, a third contact hole is formed in the second protrusion, and a second contact is formed on the second active region. A gate wiring formed at one end in the second direction among a plurality of gate wirings arranged in the direction, and a side closer to the gate wiring at one end of the two sides extending in the first direction of the second active region; The third interval, which is the shortest interval, is wider than the first interval, and the gate wiring formed at one end in the second direction and the gate wiring at one end of the two sides extending in the first direction of the second active region A fourth contact hole is formed between the side closer to.

  According to a third aspect of the present invention, there is provided a cell-based semiconductor integrated circuit comprising: a first active region and a second active region formed side by side in a first direction on a semiconductor substrate; First intervals that are arranged side by side in a second direction intersecting the first direction on the active region and the second active region, and are uniform in design in the second direction on the first active region and the second active region, respectively. And the first active region has a plurality of first protrusions protruding in the first direction, and at least a part of the plurality of first protrusions is a plurality of first protrusions, respectively. Are formed in a lower layer region between two adjacent gate wirings, a first contact hole is formed in each of the plurality of first protrusions, and arranged in the second direction on the first active region. Of the plurality of gate wirings, formed at one end in the second direction The second interval, which is the shortest interval between the gate wiring and the side closer to the gate wiring at one end of the two sides extending in the first direction of the first active region, is wider than the first interval, The first protrusion includes a protrusion provided on a side where the first and second active regions face each other, and a protrusion provided on a side opposite to the side where the first and second active regions face each other. Including.

  According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit according to the third aspect, wherein the second active region has a plurality of second projecting portions projecting in the first direction, and a plurality of second projecting portions. At least a part of each of the protruding portions is formed in a lower layer region between two adjacent gate wirings among the plurality of gate wirings, and a second contact hole is formed in each of the plurality of second protruding portions, Among the plurality of gate wirings arranged in the second direction on the second active region, the gate wiring is formed at one end in the second direction, and at one end of the two sides extending in the first direction of the second active region. The third distance, which is the shortest distance from the side closer to the gate wiring, is wider than the first distance, and the plurality of second protrusions are protrusions provided on the side where the first and second active regions face each other. And a protrusion provided on the side opposite to the side where the first and second active regions face each other Including the door.

  According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit according to any one of the first to fourth aspects, wherein the plurality of gate wirings are regions other than on the first active region and the second active region. Includes a gate wiring formed at a wiring interval wider than the first interval.

  According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit according to any one of the first to fifth aspects, wherein the width of the first protrusion in the second direction is wider than the first interval.

  According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the second or fourth aspect, the second protrusion has a width in the second direction wider than the first interval.

  According to the present invention, the finish of the gate pattern (gate shape) can be kept uniform after the wafer process without complicated CAD processing.

1 is a plan view of a basic collective element of a semiconductor integrated circuit according to a first embodiment of the present invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 1 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 1 of this invention. FIG. 6 is a plan view of a basic collective element of a semiconductor integrated circuit according to a second embodiment of the present invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 2 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 2 of this invention. It is a top view of the basic assembly element of the semiconductor integrated circuit which concerns on Embodiment 3 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 3 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 3 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 3 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 3 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 3 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 3 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 3 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit which concerns on the modification of Embodiment 3 of this invention. It is a top view of the basic set element of the semiconductor integrated circuit of the gate array which concerns on a prior art. FIG. 6 is a plan view of a basic collective element of a cell-based semiconductor integrated circuit according to the prior art. FIG. 6 is a plan view of a basic collective element of a cell-based semiconductor integrated circuit according to the prior art.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

(Embodiment 1)
FIG. 1 shows a plan view of a basic collective element of a semiconductor integrated circuit according to the present embodiment. In particular, FIG. 1 shows a part of a basic collective element composed of a p-channel transistor and an n-channel transistor. This p-channel transistor can be formed of a p-type impurity diffusion region, a gate wiring, and the adjacent p-type impurity diffusion region. A plurality of p-type impurity diffusion regions adjacent to each other through these gate wirings are called p-type active regions 1 (first or second active regions). Similarly, an n-channel transistor can be formed of an n-type impurity diffusion region, a gate wiring, and the adjacent n-type impurity diffusion region, and a plurality of n-type impurity diffusion regions can be formed as n-type active regions. 2 (second or first active region). Three gate wirings 3, 4, and 5 are formed on the p-type active region 1 and the n-type active region 2.

  Next, the p-type active region 1 has protrusions for providing contact holes 6 and 7 on the side opposite to the side facing the n-type active region 2 (upper side of the p-type active region 1 in the figure). Is formed. The contact hole 6 formed in the protruding portion is formed between the gate wiring 3 and the gate wiring 4. Further, the contact hole 7 formed in the protruding portion is formed between the gate wiring 4 and the gate wiring 5. The contact holes 6 and 7 are formed to connect a plurality of transistors formed in the p-type active region 1.

  In the basic collective element thus formed, the contact holes 6 and 7 do not exist between the gate wirings 3, 4, and 5 on the p-type active region 1 other than the protruding portions. Therefore, the gate wirings 3, 4, 5 can be arranged on the p-type active region 1 other than the protruding portions without being restricted by the positions of the contact holes 6, 7. Therefore, the gate patterns (gate shapes) of the gate wirings 3, 4 and 5 can be arranged uniformly on the p-type active region 1 other than the protruding portions. The gate wirings 3, 4, and 5 are formed so as to bypass the protruding portion.

  Even a cell-based basic collective element is configured as shown in FIG. 1, so that after the wafer process without complicated CAD processing, the gate patterns (3, 4 and 5) of the gate wirings 3, 4 and 5 are formed on the p-type active region 1. (Gate shape) It is possible to keep the finish at a uniform value. Further, since it is not necessary to increase the area of the p-type active region 1, the exclusive area of the basic collective element of the present embodiment does not increase.

  Further, the width L1 of the protruding portion for providing the contact hole 6 shown in FIG. 1 (direction parallel to the width between the gates) is larger than the gate width L3 between the gate wirings 3 and 4 on the p-type active region 1. Is bigger. Similarly, the protrusion width L2 for providing the contact hole 7 is larger than the inter-gate width L4 between the gate wirings 4 and 5 on the p-type active region 1. Thereby, the widths L1 and L2 of the protrusions can be set without being limited to the inter-gate widths L3 and L4, and the degree of freedom in the shape of the contact hole is increased. The above relationship also applies to the protrusions in the following modifications and other embodiments (in particular, the width of the protrusion and the width between the gates are not shown in the following drawings).

  2 and 3 are plan views of basic assembly elements of a semiconductor integrated circuit according to a modification of the present embodiment. In the basic collective element of FIG. 2, there are protrusions for providing contact holes 8 and 9 on the side of the p-type active region 1 facing the n-type active region 2 (below the p-type active region 1 in the figure). Is formed. The contact hole 8 formed in the protruding portion is formed between the gate wiring 3 and the gate wiring 4. Further, the contact hole 9 formed in the protruding portion is formed between the gate wiring 4 and the gate wiring 5. The basic collective element shown in FIG. 2 can achieve the same effects as the basic collective element shown in FIG.

  Next, in the basic collective element of FIG. 3, there is a protrusion for providing the contact hole 10 on the opposite side of the p-type active region 1 to the n-type active region 2 and the contact hole 11 on the opposite side. Is formed. The arrangement of the protrusions for providing the contact holes 10 and 11 is not limited to that shown in FIG. 3, and the p-type active region 1 on the side facing the n-type active region 2 and the opposite side thereof. What is necessary is just to form in each. The contact hole 10 formed in the protruding portion is formed between the gate wiring 3 and the gate wiring 4. The contact hole 11 formed in the protruding portion is formed between the gate wiring 4 and the gate wiring 5.

  The basic collective element shown in FIG. 3 can achieve the same effects as the basic collective element shown in FIG. Further, in the basic collective element shown in FIG. 3, the degree of freedom in the arrangement of contact holes is increased, so the degree of freedom in the arrangement of wirings connected to the contact holes is increased.

(Embodiment 2)
In this embodiment, the structure of the contact hole in the p-type active region shown in Embodiment 1 is applied to the n-type active region. FIG. 4 is a plan view of the basic collective element of the semiconductor integrated circuit according to the present embodiment. A p-type active region 21 and an n-type active region 22 are formed on a semiconductor substrate (not shown). Here, a transistor can be formed by the p-type impurity diffusion region, the gate wiring, and the adjacent p-type impurity diffusion region. A plurality of p-type impurity diffusion regions adjacent to each other through these gate wirings are called p-type active regions 21 (first or second active regions). Similarly, a plurality of n-type impurity diffusion regions are referred to as n-type active regions 22 (second or first active regions). Four gate wirings 23, 24, 25 and 26 are formed on the p-type active region 21 and the n-type active region 22.

  Next, contact holes 27, 28, and 29 are provided in the n-type active region 22 on the side opposite to the side facing the p-type active region 21 (below the n-type active region 22 in the figure). A protrusion is formed. The contact hole 27 formed in the protruding portion is formed between the gate wiring 23 and the gate wiring 24. Further, the contact hole 28 formed in the protruding portion is formed between the gate wiring 24 and the gate wiring 25. Further, the contact hole 29 formed in the protruding portion is formed between the gate wiring 25 and the gate wiring 26. The contact holes 27, 28 and 29 are formed to connect a plurality of transistors formed in the n-type active region 22.

  In the basic collective element formed in this way, the contact holes 27, 28, 29 do not exist between the gate wirings 23, 24, 25, 26 on the n-type active region 22 other than the protrusions. Therefore, the gate wirings 23, 24, 25, 26 can be arranged on the n-type active region 22 other than the protrusions without being restricted by the positions of the contact holes 27, 28, 29. Therefore, the gate patterns (gate shapes) of the gate wirings 23, 24, 25, and 26 can be arranged uniformly on the n-type active region 22 other than the protruding portions. The gate wirings 23, 24, 25, and 26 are formed so as to bypass the protruding portion.

  Even with a cell-based basic collective element, the gate wiring 23, 24, 25, 26 on the n-type active region 22 is formed on the n-type active region 22 after a wafer process without complicated CAD processing. It is possible to keep the pattern (gate shape) finish at a uniform value. Further, since it is not necessary to increase the area of the n-type active region 22, the exclusive area of the basic collective element of the present embodiment does not increase.

  5 and 6 are plan views of basic assembly elements of a semiconductor integrated circuit according to a modification of the present embodiment. In the basic collective element of FIG. 5, a protrusion for providing contact holes 30, 31, 32 on the side of the n-type active region 22 facing the p-type active region 21 (upper side of the n-type active region 22 in the figure). Is formed. The basic collective element shown in FIG. 5 can achieve the same effects as the basic collective element shown in FIG.

  Next, in the basic collective element of FIG. 6, a protrusion for providing a contact hole 33 on the opposite side of the n-type active region 22 to the p-type active region 21 and contact holes 34 and 35 on the opposite side. The part is formed. The arrangement of the protrusions for providing the contact holes 33, 34, 35 is not limited to that shown in FIG. 6, but the side of the n-type active region 22 facing the p-type active region 21 and the opposite side thereof. It may be formed on each of the sides.

  The basic collective element shown in FIG. 6 can achieve the same effects as the basic collective element shown in FIG. Furthermore, in the basic collective element shown in FIG. 6, the degree of freedom in the arrangement of contact holes increases, so the degree of freedom in the arrangement of wirings connected to the contact holes increases.

(Embodiment 3)
The present embodiment is a combination of the basic aggregate element shown in the first embodiment and the basic aggregate element shown in the second embodiment. First, FIG. 7 shows a plan view of a basic collective element of a semiconductor integrated circuit according to the present embodiment. A p-type active region 41 and an n-type active region 42 are formed on a semiconductor substrate (not shown). Here, a transistor can be formed by the p-type impurity diffusion region, the gate wiring, and the adjacent p-type impurity diffusion region. A plurality of p-type impurity diffusion regions adjacent to each other through these gate wirings are referred to as p-type active regions 41 (first or second active regions). Similarly, a plurality of n-type impurity diffusion regions are referred to as n-type active regions 42 (second or first active regions). Four gate wirings 43, 44, 45, 46 are formed on the p-type active region 41 and the n-type active region 42.

  Next, in the p-type active region 41, a protrusion for providing contact holes 47, 48, and 49 on the side opposite to the side facing the n-type active region 42 (above the p-type active region 41 in the figure). The part is formed. A contact hole 47 formed in the protruding portion is formed between the gate wiring 43 and the gate wiring 44. The contact hole 48 formed in the protruding portion is formed between the gate wiring 44 and the gate wiring 45. Further, the contact hole 49 formed in the protruding portion is formed between the gate wiring 45 and the gate wiring 46. The contact holes 47, 48 and 49 are formed to connect a plurality of transistors formed in the p-type active region 41.

  Next, contact holes 50, 51, and 52 are provided in the n-type active region 42 on the side opposite to the side facing the p-type active region 41 (the lower side of the n-type active region 42 in the figure). A protrusion is formed. The contact hole 50 formed in the protruding portion is formed between the gate wiring 43 and the gate wiring 44. The contact hole 51 formed in the protruding portion is formed between the gate wiring 44 and the gate wiring 45. Further, the contact hole 52 formed in the protruding portion is formed between the gate wiring 45 and the gate wiring 46. The contact holes 50, 51, 52 are formed to connect a plurality of transistors formed in the n-type active region 42.

  In the basic collective element formed in this way, the contact holes 47, 48, 48 between the gate wirings 43, 44, 45, 46 on the p-type active region 41 and the n-type active region 42 other than the protrusions. 49, 50, 51, 52 no longer exist. Therefore, the gate wirings 43, 44, 45, 46 are not limited by the positions of the contact holes 47, 48, 49, 50, 51, 52, and are on the p-type active region 41 other than the protrusions and n-type. It can be disposed on the active region 42. Therefore, the gate patterns (gate shapes) of the gate wirings 43, 44, 45, 46 can be arranged uniformly on the p-type active region 41 and the n-type active region 42 other than the protrusions. The gate wirings 43, 44, 45, and 46 are formed so as to bypass the protruding portion.

  Even in the case of a cell-based basic collective element, the gate wiring 43 is formed on the p-type active region 41 and the n-type active region 42 after the wafer process without complicated CAD processing by adopting the configuration shown in FIG. , 44, 45, and 46 can be maintained at uniform gate pattern (gate shape) finishes. Further, since it is not necessary to increase the areas of the p-type active region 41 and the n-type active region 42, the exclusive area of the basic collective element of the present embodiment does not increase.

  8 to 15 are plan views of basic assembly elements of a semiconductor integrated circuit according to modifications of the present embodiment. The present embodiment is not limited to FIG. 7, and modifications of FIGS. 8 to 15 are conceivable. First, the basic collective element shown in FIGS. 8 and 9 is formed with a protrusion for providing contact holes 50, 51, 52 below the basic collective element shown in FIG. 7 and the n-type active region 42. In common. However, the basic collective element shown in FIG. 8 is different in that a protrusion for forming contact holes 47, 48, 49 is formed below the p-type active region 41. The basic collective element shown in FIG. 9 is different in that a protrusion for forming contact holes 47 and 49 on the upper side of the p-type active region 41 and a contact hole 48 on the lower side is formed.

  Next, the basic collective elements shown in FIGS. 10 to 12 are common in that protrusions for providing contact holes 50, 51, 52 are formed above the n-type active region 42. However, the basic collective element shown in FIG. 10 is different in that a protrusion for providing contact holes 47, 48, 49 is formed above the p-type active region 41. The basic collective element shown in FIG. 11 is different in that a protrusion for forming contact holes 47, 48 and 49 is formed below the p-type active region 41. The basic collective element shown in FIG. 12 is different in that a protrusion for forming contact holes 47 and 49 on the upper side of the p-type active region 41 and a contact hole 48 on the lower side is formed.

  Further, the basic collective elements shown in FIGS. 13 to 15 are common in that protrusions for forming contact holes 50 and 52 on the upper side of the n-type active region 42 and contact holes 51 on the lower side are formed. To do. However, the basic collective element shown in FIG. 13 is different in that protrusions for providing contact holes 47, 48, and 49 are formed above the p-type active region 41. The basic collective element shown in FIG. 14 is different in that a protrusion for forming contact holes 47, 48 and 49 is formed below the p-type active region 41. The basic collective element shown in FIG. 15 is different in that a protrusion for forming contact holes 47 and 49 on the upper side of the p-type active region 41 and a contact hole 48 on the lower side is formed.

  In the basic collective element shown in FIGS. 9, 12, and 15, the arrangement of the protrusions for providing the contact holes 47, 48, and 49 is not limited to that shown in FIGS. The p-type active region 41 may be formed on the upper side and the lower side, respectively. Further, in the basic collective element shown in FIGS. 13 to 15, the arrangement of the protrusions for providing the contact holes 50, 51, and 52 is not limited to that shown in FIGS. What is necessary is just to be formed in each of the upper side and the lower side of 42.

  The basic collective elements shown in FIGS. 8 to 15 can provide the same effects as the basic collective element shown in FIG. Further, in the basic collective element shown in FIGS. 9 and 12 to 15, the degree of freedom in the arrangement of the contact holes is increased, so the degree of freedom in the arrangement of the wirings connected to the contact holes is increased.

  1, 2, 41 p-type active region, 2, 22, 42 n-type active region, 3, 4, 5, 23, 24, 25, 26, 43, 44, 45, 46 gate wiring, 6, 7, 8, 9, 10, 11, 27, 28, 29, 30, 31, 32, 33, 34, 35, 47, 48, 49, 50, 51, 52 Contact hole, 100 gate wiring, 101 p-type active region , 102 n-type active region, 103 contact hole, 104 gate wiring, 105 p-type active region, 106 n-type active region, 107 contact hole.

Claims (7)

A cell-based semiconductor integrated circuit,
A first active region and a second active region formed side by side in a first direction on a semiconductor substrate;
The first active region and the second active region are provided side by side in a second direction intersecting the first direction, and the second active region and the second active region are respectively in the second direction. And a plurality of gate wirings formed at first intervals that are uniform in design,
The first active region has a first protrusion protruding in the first direction;
At least a part of the first protrusion is formed in a lower layer region between two adjacent gate lines among the plurality of gate lines.
A first contact hole is formed in the first protrusion,
Of the plurality of gate wirings arranged in the second direction on the first active region, a gate wiring formed at one end of the second direction, and two sides extending in the first direction of the first active region Among these, the second interval that is the shortest interval with the side closer to the gate wiring at the one end is wider than the first interval,
Between the gate line formed at one end in the second direction and the side of the first active region extending in the first direction that is closer to the gate line at the one end, a second A semiconductor integrated circuit in which contact holes are formed. The second active region has a second protrusion protruding in the first direction;
At least a part of the second protrusion is formed in a lower layer region between two adjacent gate wirings among the plurality of gate wirings,
A third contact hole is formed in the second protrusion,
Of the plurality of gate wirings arranged in the second direction on the second active region, a gate wiring formed at one end in the second direction, and two sides extending in the first direction of the second active region Among these, the third interval that is the shortest interval with the side closer to the gate wiring at the one end is wider than the first interval,
Between the gate line formed at one end in the second direction and the side of the second active region extending in the first direction that is closer to the gate line at the one end, the fourth line The semiconductor integrated circuit according to claim 1, wherein a contact hole is formed. A cell-based semiconductor integrated circuit,
A first active region and a second active region formed side by side in a first direction on a semiconductor substrate;
The first active region and the second active region are provided side by side in a second direction intersecting the first direction, and the second active region and the second active region are respectively in the second direction. And a plurality of gate wirings formed at first intervals that are uniform in design,
The first active region has a plurality of first protrusions protruding in the first direction;
At least a part of the plurality of first protrusions is formed in a lower layer region between two adjacent gate lines among the plurality of gate lines,
A first contact hole is formed in each of the plurality of first protrusions,
Of the plurality of gate wirings arranged in the second direction on the first active region, a gate wiring formed at one end of the second direction, and two sides extending in the first direction of the first active region Among these, the second interval that is the shortest interval with the side closer to the gate wiring at the one end is wider than the first interval,
The plurality of first protrusions are provided on the opposite side of the protrusion provided on the side where the first and second active regions face each other and the side where the first and second active regions face each other. A semiconductor integrated circuit. The second active region has a plurality of second protrusions protruding in the first direction;
At least a part of the plurality of second protrusions is formed in a lower layer region between two adjacent gate lines among the plurality of gate lines,
A second contact hole is formed in each of the plurality of second protrusions,
Of the plurality of gate wirings arranged in the second direction on the second active region, a gate wiring formed at one end in the second direction, and two sides extending in the first direction of the second active region Among these, the third interval that is the shortest interval with the side closer to the gate wiring at the one end is wider than the first interval,
The plurality of second projecting portions are provided on a side opposite to the projecting portion provided on the side where the first and second active regions face each other and the side on which the first and second active regions face each other. The semiconductor integrated circuit according to claim 3, further comprising a protruding portion.   The plurality of gate wirings include gate wirings formed at a wiring interval wider than the first interval in regions other than the first active region and the second active region. The semiconductor integrated circuit in any one.   6. The semiconductor integrated circuit according to claim 1, wherein a width of the first protrusion in the second direction is wider than the first interval.   5. The semiconductor integrated circuit according to claim 2, wherein a width of the second projecting portion in the second direction is wider than the first interval.

Images