JP3494636B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing method. More specifically, CM
The present invention relates to a structure of a logic cell of an OS type gate array and a method of manufacturing a functional block using the logic cell.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit devices (hereinafter referred to as LSI
The tendency toward higher integration and higher performance along with the process miniaturization is increasing, and the development cost and the development period are increasing accordingly. Under such circumstances, the method of manufacturing an LSI including a gate array cell can be designed only by a wiring pattern using CAD or the like, so that an LSI suitable for shortening product development period, cost reduction, or high-mix low-volume production It has a wide range of uses as a manufacturing method.

The structure of a conventional gate array LSI will be described below with reference to the drawings. FIG. 9 is a layout sectional view of a conventional gate array cell. 940A, 940
Each B indicates a base cell. Reference numeral 980 denotes an N-channel transistor area or a P-channel transistor area in the base cells 940A and 940B.
Is the gate. Connect the transistor region 980 or the gate 990 to the contact VIA 101 in the first layer wiring 2
By connecting with 01, a wiring pattern is formed and a logic cell is formed.

The logic cell 940 configured in this way
A and 940B have an arbitrary number of connection pins 954 for connecting the logic cells, and the contact VIA11.
2, the second layer wiring 202, the contact VIA 123, and the third layer wiring 203 are connected to each other. Furthermore, if necessary, the first layer wiring 201 and the second layer wiring 202 are connected by a contact VIA 112, and the second layer wiring 202 and the third layer wiring 203 are connected by a contact VIA 12.
It is also possible to form a multi-layered wiring logic cell by connecting at 3. In the case of a normal logic cell, in most cases, the logic can be configured by using the third layer wiring. In this case, needless to say, the connection between the logic cells is further performed by using the upper wiring.

In the manufacture of the gate array cell as described above, the base cells 940A, 94 are manufactured at the time when the logic design of the LSI is started and the mask for the wiring layer is manufactured.
Since the manufacturing process up to 0B is completed (master slice method) and the remaining wiring process can be performed from there, it is possible to reduce the development period of the LSI and the design cost.

[0006]

However, the structure and manufacturing method of the conventional gate array LSI have the following problems.

With the miniaturization of processes in recent years, there is a tendency for multilayer wiring to become more and more advanced. For example, in FIG.
The functional block 400 is designed with five layers of wiring, and the logic cells 900A and 900B configured by the gate array are
When the wiring of three layers including the connection between the logic cells is involved, the logic cell 900B and the functional block 400 include the contact VIA 134, the fourth layer wiring 204, and the contact V.
The connection pin 955 is connected through the IA 145 and the fifth layer wiring 205.

Therefore, when the wiring process period is increased and the correction mask is increased when the logic correction is required, the development period and the design cost, which are the characteristics of the gate array LSI, can be shortened. I'm getting hindered.

An object of the present invention is to provide a structure of a semiconductor integrated circuit device and a method of manufacturing the same, which can shorten the development period and the development cost when the gate array type semiconductor integrated circuit device is enlarged. To do.

[0010]

A semiconductor integrated circuit device having a first structure according to the present invention is a CMO arrayed on a semiconductor substrate.
An S-type base cell and an m-layer (m is a natural number) wiring layer are provided, and the base cell and the wiring layer constitute a plurality of gate array type logic cells. In order to solve the above problems, using a wiring between the wiring and the logic cells within the logic cells, the wiring layer of the upper n-layer (n is a natural number) the (n <m), the lower
It is configured without using the (mn) layer,
The lower (mn) wiring layer is the first contact VI.
A and the first wiring pattern connected to the first contact VIA.
Consists of turns and .

A semiconductor integrated circuit device having a second structure according to the present invention.
Is a CMOS type base cell arranged on a semiconductor substrate.
And a wiring layer of m layers (m is a natural number), the base cell
And a wiring layer form a plurality of gate array type logic cells.
Is made. In order to solve the above problems,
Wiring and wiring between logic cells are connected to the upper n layers (n is a natural
Number of wiring layers (n <m) and lower (mn) layers are used
It is configured without any means. Lower (m-
n) wiring layer is a gate, a source of the base cell ,
Connect all connection points including drain and substrate potential to the upper layer
And a second wiring pattern immediately above that is connected to the second contact VIA and second contactors <br/> bets VIA for causing
Only consists of connection cells.

In the above structure, the power supply cell is a semiconductor
A CMOS type base cell arranged on a substrate and an m layer
And a line layer, the lower and the third contact VIA corresponding to at least one grid power in the base cell, the third wiring pattern connected to the third <br/> contact VIA
(M-n) wiring layers having a power source
Is the third wiring pattern between adjacent power cells.
Are connected and placed next to the logic cell.
It may be configured to be shall.

Further, the GND cell is arranged on a semiconductor substrate.
Equipped with arrayed CMOS type base cells and m wiring layers
In addition, a fourth contact VIA corresponding to at least one grid of GND in the base cell and a fourth wiring pattern connected to the fourth contact VIA are connected to the lower order (m-
n) wiring layer, the GND cell is
The fourth wiring pattern of the GND cells adjacent to each other is
Connected and placed adjacent to the logic cell
It is also possible to have a configuration of.

[0014]

A method of manufacturing a semiconductor integrated circuit device according to the present invention is a method of manufacturing the semiconductor integrated circuit device having the second configuration, in which a netlist and a parameter file are input.
The first step to apply and the parameters entered in the first step
Layer based on the wiring layer parameters in the
, And the number of K ( K is
The number of LIB_K that contains the number of connection cells
Use the second step and the LIB_K selected in the second step.
The third step of arranging logic cells and
A fourth step of roughly wiring the placed logic cells;
Fifth process for obtaining the wiring congestion degree after rough wiring in the process
Have a degree. The wiring congestion degree obtained in the fifth step is predetermined.
If it is not within the range, change the wiring layer parameter
Repeat the second to fifth steps to determine the wiring congestion
If is within the specified range, perform detailed wiring.
Output mask data.

[0016]

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An LSI and its manufacturing method according to an embodiment of the present invention will be described with reference to FIGS. Note that elements having the same configurations and functions as those of the conventional example shown in FIG. 9 are designated by the same reference numerals, and detailed description thereof will be omitted.

(Embodiment 1) FIG. 1 is a configuration diagram of a layout of an LSI in Embodiment 1. The present embodiment corresponds to the invention described in claim 1. Logic cell 10
0A and 100B are logic cells 90 in the conventional example of FIG.
0A and 900B are further provided with a second layer wiring 202 and a third layer wiring 203. Then, the first layer wiring 201 and the second layer wiring 202 contact the contact VIA.
At 112, the second layer wiring 202 and the third layer wiring 203 are connected to each other by the contact VIA 123, and the connection pin 954 is provided at the uppermost portion. Logic cells 100A and 10
0B are mutually connected to the contact VIA 134, the fourth layer wiring 204, the contact VIA 145, and the fifth layer wiring 20.
It is connected via 5a. The logic cell 100B and the functional block 400 are connected via the fifth layer wiring 205b and the connection pin 955.

As described above, in the area of the logic cells 100A and 100B, which conventionally used only three wiring layers, up to five wiring layers are used and the logic cell 100 is used.
A and 100B are used up to the lower three layers. Then, by setting the connection between the logic cells to the upper two layers,
When the logic design of the LSI is started and the mask of the wiring layer is created, the diffusion can be promoted to the third wiring layer. Therefore, it is possible to prevent an increase in the LSI manufacturing period and an increase in the correction mask due to the multi-layer wiring.

(Second Embodiment) FIG. 2 is a layout diagram of an LSI according to the second embodiment. The present embodiment corresponds to the invention described in claim 2. In the present embodiment, in the areas of the logic cells 100A, 100B and 100C, up to five wiring layers are used, and the connection cell 2
Since 00A and 200B are inserted in the lower two layers,
The modifiable wiring layers can be the upper three layers.

FIG. 3B shows a connection cell 200 (2
00A or 200B) structure is shown. The connection cell 200 is the base cell 940 (94) shown in FIG.
0A, 940B or 940C) optional grid 21
Contact VIA 220 (101 or 1 corresponding to 0
12) and the wiring pattern 230 (201A or 202B) immediately above which is connected to the contact VIA 220. In FIG. 3A, 240 is a power supply line and 250 is a ground line. 3C shows the base cell 940 of FIG. 3A and the connection cell 200 of FIG. 3B.
Shows the overlapping state. In addition, A- of FIG.
A shows the position of the cross section shown in FIG.

As shown in FIG. 2, logic cells 100B, 1
In 00C, base cells 940A and 940B
Are connection cells 200A and 200B,
It is connected to the third layer wiring 203 via the contact VIA 123. Also, the logic cells 100A, 100C
Has a connection pin 954 on the uppermost surface thereof, and the contact VIA 134, the fourth layer wiring 204, the contact VIA 145, and the fifth layer wiring 20 are mutually connected.
It is connected via 5.

(Third Embodiment) FIG. 4 shows a layout of an LSI according to the third embodiment. The present embodiment corresponds to the invention described in claim 3. In this embodiment, the power supply cell 300 is inserted for the purpose of strengthening the power supply line according to the power consumption of the logic block calculated in advance.
As a result, it is possible to use a structure in which up to five wiring layers are used and only the upper three layers can be modified.

FIG. 5B shows the structure of the power supply cell 300. The power cell 300 is the base cell 9 shown in FIG.
A contact VIA 112 corresponding to at least one grid 210 in the power supply line 240 in 40 and a wiring pattern 302 connected to the contact VIA 112 and connected to an adjacent cell. FIG. 5 (c)
5 shows a state in which the base cell 940 of FIG. 5A and the power supply cell 300 of FIG. 5B overlap each other. Note that FIG.
BB in (c) shows the position of the cross section shown in FIG.

A GND cell can be constructed similarly to the power supply cell 300. That is, if a GND cell is configured from a contact VIA corresponding to at least one grid in the GND in the base cell and a wiring pattern connected to the contact VIA and an adjacent cell, the same as the power supply cell 300 described above. Can be used for.

In FIG. 4, the direction of connection with the adjacent cells is the Y direction, but the same function can be obtained even in the X direction.

(Embodiment 4) FIG. 6 is a flow chart showing an LSI manufacturing method according to Embodiment 4 and showing an automatic layout flow in the manufacturing process. The present embodiment corresponds to the invention described in claim 6. In the manufacturing method of this embodiment, when the connection cell described in the second or third embodiment is inserted into the LSI of the first embodiment, the connection cell is automatically added according to the degree of wiring congestion. Or a method to delete.

LIB_K, which is a set of logic cells including connection cells, is created in advance for each number of connection cells to be inserted. Each aggregate LIB_K is K
The number of connection cells is K (K is a natural number of 1 to (mn-1)). For example, LIB_1 contains one connection cell, LIB_2 contains two, and similarly L
IB_ (m-n-1) includes (m-n-1). In the manufacturing process, each created LIB_K is selected and used.

First, a netlist and a parameter file are input (steps S1 and S2). Next, the wiring layer is determined based on the value of the parameter file, and the LIB_K suitable for the wiring layer is selected to determine the used LIB_K (S3). Next, logic cells are arranged (S4), and rough wiring is performed (S5). Here, the degree of wiring congestion is determined (S6). If the wiring congestion degree is higher or lower than the predetermined range, the wiring layer parameters are changed (S7), and the wiring layer design and the used LIB_K are selected again (S3). The logic cell arrangement (S4) and the general wiring (S5) are repeated, and when it is determined that the wiring congestion degree is within an appropriate range (S6), detailed wiring is performed (S8). Based on the result, mask data is output (S9).

As described above, the necessary wiring resources are secured by automatically changing the number of layers of connection cells based on the congestion degree of wiring between logic cells (net / base cell etc.). You can

(Fifth Embodiment) FIG. 7 shows a structure of wiring between functional blocks manufactured by the method of manufacturing an LSI according to the fifth embodiment. The present embodiment corresponds to the invention described in claim 7. Connection pins 951 of the logic block 403 of the gate array type LSI according to the present embodiment
And 952 are located above the third wiring. However, the existing functional block 401 composed of five layers of wiring
Alternatively, the connection pin of the existing functional block 402 configured by two-layer wiring is not necessarily the connection pin 9 of the logic block 403.
It is not always formed in the same layer as 51 and 952.
When designing a gate array type LSI, since the logic block 403 is designed last, the connection between the functional block 401 and the functional block 402 or the logical block 403 may be changed due to the influence of the logical block 403. Therefore, such a case can be dealt with by designating the wiring layer according to the logic block 403, that is, in the present embodiment, the inter-block wiring in the upper three layers is performed.

A specific example of the above wiring method will be described by taking as an example the case where the functional block 401 and the functional block 402 are formed of the first wiring layer, and the connection pins 957 and 958 are connected.

First, as shown in FIG. 8, a silicon substrate 40
A wiring prohibited area 502 of the lower two layers is set around the functional blocks 401 and 402 formed on the fourth layer. Therefore, as for the wiring in the inter-block wiring area 405, three or more wiring layers are always used where the wiring crosses the wiring prohibition area 502. That is, as shown in FIG.
Wiring is performed by the first layer wiring 201, the contact VIA 112, the second layer wiring 202, the contact VIA 123, and the third layer wiring 203. In addition, 501 of FIG. 8 shows a layer transfer area.

Similarly, the connection pin 9 of the function block 402 is
53 and the connection pin 952 of the logic block 403, and the connection pin 956 of the functional block 401 and the connection pin 951 of the logic block 403 are also connected using three or more wiring layers.

By using the manufacturing method as described above, m
When including at least one wiring layer, it is possible to use at least one wiring layer of n layers (n <m) or more, and it is possible to correct inter-block wiring in upper n or more wiring layers. Become.

[0036]

As described above, according to the present invention, the connection of logic cells, which is conventionally formed by using all the wiring layers, can be connected to the upper n layers.
This can be achieved by changing the layer wiring. As a result, even if a logic change or wiring change occurs in an LSI configured with multilayer wiring,
Since only a few masks need to be modified, the development period and development cost can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a layout of a gate array cell according to a first embodiment.

FIG. 2 is a sectional view showing a layout of a gate array cell according to the second embodiment.

FIG. 3 shows a configuration of a connection cell in the gate array cell of FIG. 2, (a) is a plan view of a base cell,
(B) is a plan view of the connection cell, (c) is (a)
And FIG.

FIG. 4 is a sectional view showing a layout of a gate array cell according to a third embodiment.

5 shows a configuration of a power supply cell in the gate array cell of FIG. 2, (a) is a plan view of a base cell, (b) is a plan view of a power supply cell, (c) is (a) and (b). Plan view showing the stacked state

FIG. 6 is a flowchart showing an LSI manufacturing method according to the fourth embodiment.

FIG. 7 is a cross-sectional view showing a configuration of wiring between functional blocks manufactured by a method of manufacturing an LSI according to a fifth embodiment.

FIG. 8 is a plan view showing the configuration of wiring between the functional blocks of FIG.

FIG. 9 is a cross-sectional view showing a layout of a conventional gate array cell.

[Explanation of symbols]

100A, 100B, 100C, 900A, 900B
Logic cells 101, 112, 123, 134, 145, 220 Contact VIA 201 First layer wiring 202 Second layer wiring 203 Third layer wiring 204 Fourth layer wiring 205, 205a, 205b Fifth layer wiring 200 , 200A, 200B Connection cell 240 Power supply line 250 Ground line 230 Wiring pattern 210 directly above contact VIA Grid 300 Power supply cell 302 Power supply cell Wiring pattern 400, 401, 402 Functional block 403 Logic block 404 Silicon substrate 405 Inter-block wiring area 501 Pin transfer Region 502 Lower two wiring prohibition regions 940A, 940B Base cells 951 to 958 Connection pin 980 Transistor region 990 Gate

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/092 H01L 27/04 D 27/118 (56) References JP-A-9-62725 (JP, A) JP-A-5 -190816 (JP, A) JP 60-1844 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/3205 H01L 21/822 H01L 21/8238 H01L 27/04 G06F 17/50 H01L 27/092 H01L 27/118

Claims (5)

(57) [Claims] 1. A CMOS-type base cell arranged on a semiconductor substrate and an m-layer (m is a natural number) wiring layer, wherein the base cell and the wiring layer form a plurality of gate-array logic cells. In the semiconductor integrated circuit device,
Wiring in the logic cell and wiring between the logic cells,
Using the upper n layers (n is a natural number) of the wiring layers (n <m ) ,
(M-n) layers are not used, and the lower (m-n) wiring layer in the logic cell is
The first contact VIA and the first contact VIA
A semiconductor integrated circuit device comprising: a connected first wiring pattern . 2. A CMOS type substrate arranged on a semiconductor substrate.
Source cell and m wiring layers (m is a natural number),
Multiple gate arrays using the base cell and the wiring layer
In a semiconductor integrated circuit device having a logical cell of the formula,
Wiring in the logic cell and wiring between the logic cells,
Using the upper n layers (n is a natural number) of the wiring layers (n <m),
(M-n) layers are not used, the wiring layer of the lower (m-n) layer in the logic cell provides the gate, source, drain, and substrate potential of the base cell.
The second co <br/> Ntakuto VIA and consist solely connection cell and a second wiring pattern immediately above that is connected to the second contact VIA for connecting all connection points to the upper layer comprising the semiconductor integrated circuit device according to claim. 3. The power supply cells are arranged on a semiconductor substrate.
A third contact VIA corresponding to at least one grid of a power supply in the base cell , which includes a CMOS type base cell and m wiring layers, and a third wiring connected to the third contact VIA. Pa
It has turns in the lower (mn) wiring layer.
The power supply cells are located in front of the power supply cells that are adjacent to each other.
The third wiring pattern is connected to the logic cell.
The semiconductor integrated circuit device according to claim 1 or 2 , wherein the semiconductor integrated circuit device is arranged adjacent to the semiconductor integrated circuit device. 4. The GND cell is arranged on a semiconductor substrate.
And a fourth contact VIA corresponding to at least one grid of GND in the base cell, and a fourth base connected to the fourth contact VIA . Wiring pattern
It has turns in the lower (mn) wiring layer.
The GND cells are located in front of the GND cells adjacent to each other.
The fourth wiring pattern is connected to the logic cell.
The semiconductor integrated circuit device according to claim 1 or 2 , wherein the semiconductor integrated circuit device is arranged adjacent to the semiconductor integrated circuit device. 5. A method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein the first method comprises inputting a netlist and a parameter file.
Of the process and the parameter file input in the first process
Determine the wiring layer based on the wiring layer parameters of
K number ( K is a natural number) of the above , which conforms to the specified wiring layer
Second step to select LIB_K including connection cell
And using the LIB_K selected in the second step,
Row and the third step, the global routing of the logic cells arranged in the third step of disposing the serial logic cells
The fourth step and the wiring congestion degree after the rough wiring in the fourth step are obtained.
And the fifth step, and the wiring congestion degree obtained in the fifth step falls within a predetermined range.
If not, change the wiring layer parameters and change
Repeating the second step to the fifth step, the wiring
If the congestion level is within the specified range, detailed wiring
Which performs masking and outputs mask data
Manufacturing method of integrated circuit device.