JPH02278848A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of processes required for a correction and to shorten the number of days for the correction by a method wherein an element column which has been arranged cyclically and which is not related to a prescribed function is formed in a space region of either an external-function constitution part or an internal-function constitution part of a specific element arrangement structure. CONSTITUTION:In an integrated circuit chip, various functional blocks 30 are arranged in an external-function constitution part incliding an input/output circuit and in an internal-function constitution part 3. They are connected to each other; a main part of functions of an integrated circuit device is constituted. A transistor array 4 is constituted of P-type diffusion layers 41, N-type diffusion layers 42 and polycrystalline silicon gates 43 which have been composed of cyclically arranged cell units 40 and whose shapes are respectively equal. In this integrated circuit, the transistor array 4 is formed by utilizing a blank space which is produced in the internal-function constitution part 3. Accordingly, when a circuit of the integrated circuit device is corrected, this correction can be realized by changing a pattern during a wiring process. Thereby, it is not required that a correction process is traced back to a transistor formation process; the number of days for the correction can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device, and particularly to an integrated circuit device using a standard cell method.

[Conventional technology]

Standard cell type custom integrated circuit devices are manufactured with an element arrangement structure specific to the function of the integrated circuit device from the initial patterning process of wafer manufacturing, and only the functional elements necessary for the integrated circuit device are manufactured, apart from the manufacturing check pattern. is laid out on the chip.

For this reason, standard cells are better than gate arrays, in which a desired circuit is realized on a group of transistors arranged in advance so that they can be commonly used in various circuits, and the remaining elements are left as is. This has the advantage that the chip area can be reduced and costs can be reduced.

[Problem to be solved by the invention]

In the conventional integrated circuit device using the standard cell method described above, when the circuit is modified after prototype production, it is necessary to lay out the circuit again based on the modified circuit and rebuild it from the first step of wafer manufacturing. For this reason, there is a problem in that more days are required for modification than in the case of gate arrays, in which circuit modification can be performed in most cases just by the wiring process during wafer manufacturing.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device in which the number of days required for modification can be shortened by reducing the number of steps required for modification.

[Means to solve the problem]

In the integrated circuit device of the present invention, an element having periodicity and not related to the predetermined function is arranged in a space region of either an external functional component or an internal functional component configured with a specific element arrangement structure. forming a line.

Further, the element array can have a common configuration with the gate array.

[Operation] In this configuration, when a problem occurs in the circuit operation of the integrated circuit device, the circuit can be corrected by using a part of the element array to move the placement position of the functional block or add a circuit due to the circuit change etc. This correction can be realized by changing the pattern of the wiring process, thereby eliminating the need to trace the correction process back to the transistor formation process, and simply correcting the wiring process, reducing the number of days required for correction.

Furthermore, by sharing the element array with the gate array, circuit connections for forming block-level functions are not required.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a first embodiment of the invention. In the figure, 1 is an integrated circuit chip, 2 is an external functional component including an input/output circuit (buffer), and a bonding pad is usually included in this area.

Reference numeral 3 denotes an internal functional component, in which various functional blocks 30 are arranged as partially enlarged in FIG. 2, and are interconnected to constitute the main functions of the integrated circuit device. That is, in FIG. 2, a P-type diffusion layer 31 and an N-type diffusion layer 32 . Polycrystalline silicon gates 33 of different lengths and widths are formed to form various P-channel and N-channel transistors. This is to form transistors suitable for each designed circuit in order to improve area efficiency in the integrated circuit.

4 is a transistor array related to the present invention, which, as shown in FIG. 3, is composed of cell units 40 arranged periodically. That is, each cell unit 40 is composed of a P-type diffusion layer 41, an N-type diffusion layer 42, and a polycrystalline silicon gate 43, each having the same shape.

In addition, in a normal integrated circuit, the areas of the external functional component 2 and the internal functional component 3 are almost never all used, and free space is created in either the external or internal functional component. There is. For this reason, in this embodiment, the transistor array 4 is formed using the empty space created in the internal functional configuration section 3, and by forming this transistor array 4, the integrated circuit chip l is enlarged. Never.

Therefore, in an integrated circuit configured in this way, if a defect is discovered after the chip l is first physically realized and it is necessary to add a circuit function to correct or improve the defect, , the circuit can be modified by interconnecting the transistors on the transistor array 4, configuring the desired circuit function, and connecting it to the original circuit. The manufacturing mask to be changed here does not require at least the transistor formation process, and only the wiring is required, and if the manufacturing process before the boundary is carried out in advance, the process required for modification will be the remaining process. That's all,
The number of days required for revisions can be shortened.

In other words, if you have both standard cell and gate array functional blocks in the same manufacturing process, you can use the gate array block as is by forming a common transistor play with the gate array in transistor array 4. At least, it becomes unnecessary to make circuit connections for forming block-level functions, and efficient handling becomes possible.

FIG. 4 shows another embodiment of the present invention, in which the same parts as in FIG. 1 are given the same reference numerals. In this embodiment, a transistor array 4A is configured using the empty space created in the external functional configuration section 2.

However, when configured in this way, a wide power supply path line often passes through the external functional configuration section 2, and a transistor array is arranged under the path line. Therefore, in such a case, for example, since the power supply pass line is formed of the second layer aluminum wiring, only the first eyebrow wiring is used for the circuit on the transistor array. Note that if it is difficult to construct a circuit using only this first layer wiring, it is possible to use polycrystalline silicon as the wiring, although the manufacturing process for correction will be longer. In the process, by assigning the third layer wiring to the power supply bus, it is possible to use the first and second wiring layers for the circuit configuration on the transistor array.

〔Effect of the invention〕

As explained above, the present invention forms element rows that have periodic arrangement and are not related to the functions of each functional component in the space area of either the external functional component or the internal functional component. Therefore, when modifying the circuit of an integrated circuit device, it can be realized by changing the pattern in the wiring process, thereby eliminating the need to trace the modification process back to the transistor formation process, and reducing the number of days required for modification. Furthermore, by sharing the element array with the gate array, it becomes unnecessary to perform circuit connections for forming block-level functions, and efficient handling becomes possible.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is an enlarged layout diagram of a part of the internal functional components, FIG. 3 is an enlarged layout diagram of a part of the transistor array, and FIG. 4 is a diagram illustrating the invention. FIG. 3 is a plan view of another embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Integrated circuit chip, 2... External functional component, 3
...Internal functional component, 4,4A...Transistor array, 30...Cell unit, 31...P type diffusion layer, 32...N type diffusion layer, 33...Polycrystalline silicon gate , 40... Functional block, 41... P type diffusion layer, 42... N type diffusion layer, 43... Polycrystalline silicon gate. Figure 1, I X 4 rII Fh + , 7':l''2nd
Zuushin S SoP gx-up-up-go-sho〉Nokogi゛-L

Claims (1)

[Claims] 1. In an integrated circuit device comprising an external functional component and an internal functional component configured with a specific element arrangement structure for configuring a predetermined function, the external functional component or the internal functional component An integrated circuit device characterized in that an element array having periodicity and not related to the predetermined function is formed in any one of the space regions. 2. The integrated circuit device according to claim 1, wherein the element array has a common configuration with a gate array.