JP2000299382A - Layout cell for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily correct a circuit with a small number of masks by arranging a spare transistor for circuit modification in a layout cell. SOLUTION: In a layout cell for a semiconductor integrated circuit, a P- channel MOS transistor 104 and a spare P-channel MOS transistor 110 are provided in a P-channel MOS transistor region 102 in a layout cell frame 101. Also an N-channel MOS transistor 105 and a spare N-channel MOS transistor 111 are provided in an N-channel MOS transistor region 103. Then, based on the layout cell for an integrated circuit where layout design is made, a circuit modification is made. Also by having only a metal wiring layer which is easily changed, an NOR, OR, or inverter circuit is obtained, to easily modify the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout cell for a semiconductor integrated circuit, and more particularly, to a layout cell designed as a component of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art When a semiconductor integrated circuit having a certain function is realized, a design / manufacturing method is selected according to the use of the integrated circuit, required characteristics, and the like. In the case of a general-purpose integrated circuit, an FPGA (Field Programmer) that realizes the required performance by arranging only the logic cells which are the constituent units of the integrated circuit and arranging the cells by the user is provided.
BLE Gate Array), but in applications where the degree of integration and operation speed are required, the ASIC (Application Speech
cific IC). A
Among SIC design methods, a cell-based method of arranging and wiring standard cells having basic functions on a chip is widely used as a main method.

In recent years, in the design of semiconductor integrated circuits,
Higher integration is required to reduce the size of devices using the circuit, etc.In order to carry out design that satisfies the performance and specifications required by users due to the higher functionality and complexity of integrated circuits on a chip Since the number of steps tends to increase and the cost tends to increase, an efficient design method is required.

For this reason, instead of creating a circuit diagram or the like as before, a hardware description language (HDL: Hardware Descripti) such as VHDL or Verilog-HDL is used.
on Language), and based on the description, a design method of generating a gate circuit using a logic synthesis tool, a placement / wiring tool, or the like is often used. When an ASIC is designed by such a method, after a logic design that performs logic synthesis or the like based on the HDL description, a standard cell, a more complicated macro cell, or the like is used in a cell-based ASIC in accordance with the logic design. Are arranged and wired to form a mask pattern.

[0005] Logic design and layout design are performed in accordance with specifications determined according to the design of a system in which an integrated circuit or a chip including the integrated circuit is used, but the system design itself is becoming complicated and difficult. Nowadays, there are cases where the system design cannot be completed before the start of the logical design, and the specification must be changed after the start of the logical design. Furthermore, it is difficult to achieve the specifications required by the system design in the logic design and the layout design due to the above-mentioned complicatedness and the like. However, there is a problem that the number of man-hours to cope with such restrictions in the layout design process increases.

Further, even when it is desired to make small-scale changes after the layout design due to specification changes or discovery of design errors, it is necessary to repeat the layout design in consideration of timing constraints. The problem is that efficient design and manufacture cannot be achieved, and when modifying the mask for each physical layer created in post-design manufacture, the effect of the man-hour and cost for this is particularly large. Had become.

In order to solve such a problem by the conventional technique, a spare cell (not used in the designed circuit) is inserted at the time of the layout design, and the layout design and the mask are performed. In the event that a circuit change is required after the creation, some methods have been proposed assuming that the change is made using a spare cell so that the change can be made easily and at low cost.

As one of such methods, Japanese Patent Laid-Open No.
There is an apparatus disclosed in “Semiconductor Integrated Circuit Device” in JP-A-198680. According to this method, a P-channel MOS transistor having a gate connected to a power supply and an N-channel MOS transistor having a gate connected to the ground are provided as transistors for circuit correction.
A cell composed of a channel type MOS transistor is prepared and incorporated in advance at the time of layout design, so that a circuit change involving later mask correction can be easily performed.

A method disclosed in Japanese Patent Application Laid-Open No. 6-295955 entitled "Layout method of integrated circuit and semiconductor device" discloses a spare logic circuit composed of two or more cells at the time of automatic placement and routing. Is prepared, and is arranged as a spare cell at a predetermined position such as at both ends of a cell row or in a plurality of rows, and thereafter wiring is performed so that subsequent changes can be easily made. By performing such placement and wiring, the wiring of the spare logic circuit crosses the wiring area, so that the wiring can be easily corrected by using this wiring.

[0010]

As described above, during the period from system design to semiconductor integrated circuit production, particularly, the man-hour and cost for changes after layout design are increased in the design and production of semiconductor integrated circuits. Had been a problem. According to the method of arranging the spare cells in advance and easily changing the spare cells using the spare cells, it is necessary to store the characteristic values and the like of the spare cells in the library. Therefore, the data amount of the library increases. In addition, since the spare cells are arranged, the chip area increases, and it is difficult to suppress the circuit scale.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and makes it possible to easily perform circuit correction after layout design with a small number of masks without greatly increasing the amount of data to be processed and the circuit scale. It is an object of the present invention to provide a layout cell for a semiconductor integrated circuit that can be used.

[0012]

In order to achieve the above object, a layout cell for a semiconductor integrated circuit according to a first aspect of the present invention is a layout cell for a semiconductor integrated circuit designed to be laid out as a component of the semiconductor integrated circuit. , A spare transistor for circuit correction is arranged in the layout cell.

A layout cell for a semiconductor integrated circuit according to a second aspect of the present invention is a layout cell for a semiconductor integrated circuit that is laid out with the semiconductor integrated circuit as a constituent element. Only the metal wiring layer is used.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 The layout cell for a semiconductor integrated circuit according to the first embodiment of the present invention is designed to easily perform circuit correction by arranging a spare transistor in advance in an empty area in the layout cell. FIG. 1 is a diagram for explaining a configuration of a layout cell for a semiconductor integrated circuit according to a first embodiment of the present invention and a circuit modification in the layout cell. Same figure
(a) is a layout cell for a semiconductor integrated circuit according to the first embodiment, which is configured to realize a NAND circuit. FIG. 1B shows a layout cell for a semiconductor integrated circuit which realizes an AND circuit obtained by modifying the circuit shown in FIG. 1A.

As shown in FIG. 1A, a layout cell for a semiconductor integrated circuit according to the first embodiment has a layout cell frame 1
01, a P-channel MOS transistor region 102,
An N-channel MOS transistor region 103, a power supply wiring 106, and a ground supply wiring 107 are provided.
A P-channel MOS transistor 104 and a spare P-channel MOS
The transistor 110 and the N-channel MOS transistor region 103 include the N-channel MOS transistor 1
05 and a spare N-channel MOS transistor 111. The power supply wiring 106 is a power supply terminal 108, and the ground supply wiring 107 is a ground terminal 109.
And are connected to a power supply and a ground, respectively.

In the figure, each transistor has a contact layer 112, and an input to the entire layout cell for a semiconductor integrated circuit is a signal input terminal 11.
3 and 114, and the output from the semiconductor integrated circuit layout cell is output from the signal output terminal 115. As shown in the figure, the hatched portion (upward to the right) indicates the metal wiring layer (first), and the hatched portion in a lattice shape indicates the polysilicon layer.

When an input signal is input from the input terminals 113 and 114 of the layout cell for an integrated circuit according to the first embodiment shown in FIG. The result of the NAND operation processing is output from the terminal 115. The spare P-channel M in the P-channel MOS transistor region 102
The gate input of the OS transistor 110 is fixed to the power supply, and the spare N-channel MOS transistor 111 in the N-channel MOS transistor region 103
Are fixed to the ground, and these spare transistors are not used in a circuit that executes NAND operation processing.

FIG. 2B is a diagram showing an AND circuit designed by modifying the circuit based on the layout cell for the integrated circuit whose layout has been designed as shown in FIG. 1A. As shown in FIG.
The first metal wiring layer indicated by the hatched portion (upward to the right) and the second metal wiring layer indicated by the oblique line (upward to the left) are modified from the NAND circuit of FIG. (a)
Unlike the case of P-channel MOS transistor 110
The N channel MOS transistor 111 is used for signal processing. When an input signal is input from the input terminals 113 (similar to FIG. 1A) and 114 (same) of the integrated circuit layout cell, signal processing is performed in the cell,
The output terminal 115 (same output) outputs the result of the AND operation processing.

As described above, according to the layout cell for the semiconductor integrated circuit of the first embodiment shown in FIG.
With the provision of the channel MOS transistor 110 and the spare N-channel MOS transistor 111, these are not used for signal processing in the state of FIG. As shown in FIG.
And the circuit can be modified with a small number of masks.

In the first embodiment, it is assumed that spare transistors are arranged in the NAND circuit shown in FIG. 1A, and a circuit is modified by using the spare transistors to obtain an AND circuit. However, this is an exemplification, and it is also possible to obtain a NOR circuit, an OR circuit, or an inverter circuit by easily changing only the same metal wiring layer. It is also possible to create an inverter cell independently of the NAND circuit shown in FIG.

Further, spare transistors are arranged in a layout cell other than the NAND circuit, which performs logical operation processing, that is, a layout cell functioning as a NOR circuit, an OR circuit, an inverter circuit, or the like, and the circuit is modified using the spare transistor. Embodiment 1 is also possible.
As in the example shown in FIG. 7, the number of masks at the time of circuit correction can be suppressed, and the man-hour and cost can be reduced.

Embodiment 2 FIG. The layout cell for a semiconductor integrated circuit according to the second embodiment of the present invention is designed to easily perform circuit correction by performing signal processing in the layout cell only with the metal wiring layer. FIG. 2 is a diagram for explaining a configuration of a layout cell for a semiconductor integrated circuit according to a second embodiment of the present invention and a circuit modification in the layout cell. Figure (a)
Is a layout cell for a semiconductor integrated circuit according to the second embodiment, which is configured to realize a NOR circuit. FIG. 1B shows a layout cell for a semiconductor integrated circuit which realizes a buffer circuit obtained by modifying the circuit shown in FIG. 1A.

As shown in FIG. 2A, the layout cell for a semiconductor integrated circuit according to the second embodiment has a layout cell frame 2
01, a P-channel MOS transistor region 202,
An N-channel MOS transistor region 203, a power supply wiring 206, and a ground supply wiring 207 are provided. The power supply wiring 206 has a power supply terminal 208, and the ground supply wiring 207 has a ground terminal 209, which are connected to a power supply and a ground, respectively.

In the figure, each transistor has a contact layer 212, and an input to the entire layout cell for a semiconductor integrated circuit is a signal input terminal 21.
3 and 214, and the output from the semiconductor integrated circuit layout cell is output from the signal output terminal 215. As shown in the figure, the hatched portion (upward to the right) indicates the metal wiring layer (first), and the hatched portion in a lattice shape indicates the polysilicon layer. In the layout cell for an integrated circuit according to the second embodiment, all signal processing is performed only by the metal wiring layer.

When an input signal is input from the input terminals 213 and 214 of the layout cell for an integrated circuit according to the second embodiment shown in FIG. The result of the NOR operation processing is output from the terminal 215.

FIG. 2B is a diagram showing a buffer circuit designed by modifying the circuit based on an integrated circuit layout cell for which the layout has been designed as shown in FIG. 1A. As shown in FIG.
The first metal wiring layer indicated by oblique lines (upward to the right) is modified from the NOR circuit of FIG.

FIG. 3 shows a layout cell for an integrated circuit whose layout has been designed by a conventional technique.
This is a NOR circuit that performs the same NOR operation processing as. In the same figure, as in FIG. 2, the hatched portion (upward to the right) indicates the metal wiring layer (first), and the hatched portion in a lattice shape indicates the polysilicon layer. As shown in the figure, in a layout cell for an integrated circuit according to the conventional technology, a polysilicon layer is frequently used for connecting a gate layer, and a diffusion layer is shared between a source and a drain, thereby reducing the circuit size. And so on. However, when the circuit modification to the buffer circuit is to be performed based on such a layout cell as in the case shown in FIG. 2, the modification cannot be performed only by changing the metal wiring layer. As a result, the number of steps and costs cannot be reduced.

As described above, according to the semiconductor integrated circuit layout cell of the first embodiment shown in FIG. 1A, signal processing is performed only on the metal wiring layer, and it is easy to change only the metal wiring layer. The circuit shown in FIG. 5B can be obtained by such a circuit correction, and the circuit correction can be performed with a small number of masks.

In the second embodiment, the signal processing in the NOR circuit shown in FIG. 2A is exclusively performed by a metal wiring layer, and the circuit is easily modified to obtain a buffer circuit. However, this is only an example, and it is possible to obtain a NAND circuit, an inverter circuit, and the like by easily changing only the same metal wiring layer.

Further, in a layout cell other than the NOR circuit, which performs logical operation processing, that is, in a layout cell functioning as a NAND circuit, an OR circuit, an inverter circuit, or the like, signal processing is performed only on the metal wiring layer.
As a result, the circuit can be easily corrected, and similarly to the example shown in the second embodiment, it is possible to reduce the number of masks at the time of circuit correction and to reduce the number of steps and cost.

Embodiment 3 The layout cell for a semiconductor integrated circuit according to the third embodiment of the present invention has a configuration in which a spare transistor is disposed in advance in a vacant area in the layout cell, and further, signal processing is performed only on the metal wiring layer. It is intended to be easily performed. FIG. 4 is a diagram for explaining a configuration of a layout cell for a semiconductor integrated circuit according to a third embodiment of the present invention and a circuit modification in the layout cell. FIG. 3A shows a layout cell for a semiconductor integrated circuit according to the third embodiment.
It is configured to realize an inverter circuit.
FIG. 1B shows a layout cell for a semiconductor integrated circuit which realizes an AND circuit obtained by modifying the circuit shown in FIG. 1A.

As shown in FIG. 3A, the layout cell for a semiconductor integrated circuit according to the third embodiment has a layout cell frame 4
01, a P-channel MOS transistor region 402,
The semiconductor device includes an N-channel MOS transistor region 403, a power supply wiring 406, and a ground supply wiring 407.
A P-channel MOS transistor 404 and a spare P-channel MOS
The transistor 410 and the N-channel MOS transistor region 403 include the N-channel MOS transistor 4
05 and a spare N-channel MOS transistor 411. The power supply wiring 406 is connected to the power supply terminal 408, and the ground supply wiring 407 is connected to the ground terminal 409.
And are connected to a power supply and a ground, respectively.

In the figure, each transistor has a contact layer 412, and an input to the entire layout cell for the semiconductor integrated circuit is a signal input terminal 41.
3 and 414, and the output from the semiconductor integrated circuit layout cell is output from the signal output terminal 415. As shown in the figure, the hatched portion (upward to the right) indicates the metal wiring layer (first), and the hatched portion in a lattice shape indicates the polysilicon layer. In the layout cell for an integrated circuit according to the third embodiment, all signal processing is performed only by the metal wiring layer.

When an input signal is input from the input terminals 413 and 414 of the layout cell for an integrated circuit according to the third embodiment shown in FIG. 4 (a), the signal is processed in the cell and the output is performed. The result of the logical inversion operation is output from the terminal 415. The spare P channel M in the P channel MOS transistor region 402
The gate input of OS transistor 410 is fixed to the power supply, and spare N-channel MOS transistor 411 in N-channel MOS transistor region 403
Are fixed to the ground, and these spare transistors are not used in a circuit that performs a logical inversion operation.

FIG. 4B is a diagram showing an AND circuit designed by performing circuit correction based on the layout cell for the integrated circuit for which the layout has been designed as shown in FIG. As shown in FIG.
The first metal wiring layer indicated by the hatched portion (upward to the right) and the second metal wiring layer indicated by the oblique line (upward to the left) are modified from the NAND circuit of FIG. (a)
Unlike the case of P-channel MOS transistor 410
The N channel MOS transistor 411 is used for signal processing. When an input signal is input from the input terminals 413 (similar to FIG. 4A) and 414 (same) of the integrated circuit layout cell, signal processing is performed in the cell,
The output terminal 415 (same output) outputs the result of the AND operation processing.

As described above, according to the layout cell for the semiconductor integrated circuit of the third embodiment shown in FIG.
Since the channel MOS transistor 410 and the spare N-channel MOS transistor 411 are provided and the signal processing is performed only on the metal wiring layer, the circuit shown in FIG. By using these transistors, which are not used for signal processing in the state, for signal processing, the circuit shown in FIG. 2B can be obtained, and circuit correction can be performed with a small number of masks. .

In the third embodiment, it is assumed that a spare transistor is arranged in the inverter circuit shown in FIG.
Although the case where a circuit is obtained is shown, this is an exemplification, and a NOR circuit, an OR circuit, or a NAND circuit can be obtained by a simple change only in a similar metal wiring layer.

Further, spare transistors are arranged in layout cells other than the inverter circuit, which perform logical operation processing, ie, layout cells functioning as a NOR circuit, an OR circuit, or a NAND circuit, and signal processing is performed only by the metal wiring layer. As a modification, the circuit can be modified, and the number of masks at the time of circuit modification can be suppressed to reduce the man-hour and cost as in the example shown in the third embodiment.

[0039]

According to the layout cell for a semiconductor integrated circuit of the present invention, in a layout cell for a semiconductor integrated circuit designed to be laid out as a component of the semiconductor integrated circuit, a spare transistor for circuit correction is provided in the layout cell. Is arranged, the circuit can be easily repaired by using the spare transistor. Therefore, the number of masks at the time of repair can be suppressed, and the man-hour and cost can be reduced.

A layout cell for a semiconductor integrated circuit according to a second aspect of the present invention is a layout cell for a semiconductor integrated circuit designed to be laid out with the semiconductor integrated circuit as a constituent element. By using only the metal wiring layer,
Since the circuit can be easily corrected, it is possible to reduce the number of masks at the time of the correction and reduce the man-hour and cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a layout cell for a semiconductor integrated circuit according to a first embodiment of the present invention and a circuit modification in the cell.

FIG. 2 is a block diagram showing a configuration of a layout cell for a semiconductor integrated circuit according to a second embodiment of the present invention and a circuit modification in the cell.

FIG. 3 is a diagram showing a layout cell for a semiconductor integrated circuit according to a conventional technique.

FIG. 4 is a block diagram showing a configuration of a layout cell for a semiconductor integrated circuit according to a second embodiment of the present invention and a circuit modification in the cell;

[Explanation of symbols]

101, 201, 401 Layout cell frame 102, 202, 402 P-channel MOS transistor formation region 103, 203, 403 N-channel MOS transistor formation region 104, 204, 404 P-channel MOS transistor 105, 205, 405 N-channel MOS transistor 106, 206, 406 Power supply wiring 107, 207, 407 Ground supply wiring 108, 208, 408 Power supply terminal 109, 209, 409 Ground terminal 110, 410 Spare P-channel MOS transistor 111, 411 Spare N-channel MOS transistor 112, 212, 412 Contact Layer 113,213,413 Signal input terminal 114,214,414 Signal input terminal 115,215,415 Signal output terminal

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Masahide Kanno 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yasuhiko Kajimoto 1006 Okadoma Kadoma City, Osaka Matsushita Electric Industrial Co. 72) Inventor Yasushi Takenaka 1006 Kadoma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Shinichi Hashimoto 1006 Odaka Kadoma, Kadoma City, Osaka Pref. Matsushita Electric Industrial Co., Ltd. 1006 Kadoma, Kadoma Matsushita Electric Industrial Co., Ltd. F-term (reference)

Claims (2)

[Claims] 1. A layout cell for a semiconductor integrated circuit which is designed as a layout element as a component of the semiconductor integrated circuit, wherein a spare transistor for circuit correction is arranged in the layout cell. . 2. A semiconductor integrated circuit layout cell designed to be laid out using a semiconductor integrated circuit as a component, wherein only a metal wiring layer is used as a signal processing wiring in the layout cell. Layout cell for integrated circuits.