JPH09191095A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce consumed power by forming a channel width in such a manner that each transistor constituting a logic circuit in a gate array satisfies the optimum drive capability. SOLUTION: In a semiconductor integrated circuit wherein basic transistor cells are formed in an array type, a desired logic circuit function is constituted by changing an impurity diffusion layer mask, a contact mask and a wiring layer mask. In the basic transistor cell, the size of an impurity diffusion region having at least the contact region of a power supply wiring region and a source.drain is minimized, and an impurity diffusion size variable region which can be changed into a desired channel width is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which basic transistor cells are formed in an array on a semiconductor substrate, and a mask for forming an impurity diffusion layer, a mask for forming a contact and a mask for forming a wiring layer are provided. The present invention relates to a semiconductor integrated circuit that is manufactured by changing it, and particularly to a semiconductor integrated circuit that can change the channel width of a basic transistor.

[0002]

2. Description of the Related Art In a gate array LSI, a semiconductor substrate is provided with a region (hereinafter referred to as a basic cell region) provided with a plurality of unwired basic transistor elements of uniform size, and an input / output buffer region around the region. It is normal. The semiconductor device is called a bulk and has unwired basic cells 1 and input / output buffers 2 as shown in FIG. FIG. 2 is a schematic plan view showing a basic cell region of a gate array according to a conventional example. Generally, a basic cell has a structure in which two rows of gates are arranged together. 3 is a PchMOS transistor configuration region, 4 is N
chMOS transistor configuration region, 5 is a gate of a MOS transistor, 6 is a basic cell including 3 and 4, and is a basic cell,
Reference numeral 7 is a PchMOS impurity diffusion region, and 8 is an NchMOS impurity diffusion region. In FIG. 2, three uniform basic cells are arranged.

Here, in the conventional gate array method, a transistor element having a fixed channel width called a bulk before contact and wiring layer formation is usually prepared in advance, and only the contact and wiring layer are changed to be desired. It is a design method that configures the function of. In designing a gate array, use of an automatic layout system is a prerequisite for completing the design in a short period of time.

A conventional gate array design flow is shown in FIG. On the design side, based on the connection information S1 (hereinafter referred to as a netlist) of the completed logic circuit, the layout process of logic cells and the wiring process S between logic cells are performed by using the automatic layout system.
2, the layout data S3 satisfying the desired circuit function is created, and the wiring layer mask and the contact mask S4 are created from this data. On the other hand, on the semiconductor manufacturing side, P
When the semiconductor device before the contact and wiring called the bulk is manufactured in the step 1 and the wiring layer mask and the contact mask S4 can be created, the step P2 of contact formation and wiring layer formation is performed by the mask. By doing so, an IC satisfying the desired function is completed.

[0005]

In the conventional gate array, the size of the basic transistor in the basic cell region is usually designed to be a uniform size according to the place (eg, output part) where the maximum driving capability is required. Yes, therefore, in a place where a smaller drive capacity is required, the drive capacity becomes excessive, resulting in waste. Therefore, as compared with the case where individual transistor sizes are designed so that each unit has a required minimum driving capability, such a gate array often has excessive performance. Of course, in the conventional method, due to the nature of the gate array in which only the wiring layer is changed, it is impossible to predetermine individual transistor sizes as in a custom IC. Therefore, there is a problem that power consumption is unnecessarily increased due to excessive driving capability of the transistor.

In addition, when a change occurs in the manufacturing process of an already designed IC, the characteristics such as the transistor driving ability, the wiring resistance, and the wiring capacitance change depending on the manufacturing process, and the channel width of the transistor in the conventional gate array is changed. Is fixed, the timing change due to the process change cannot be coped with, and the timing malfunction occurs. Therefore, when there is a change in the manufacturing process, there is a problem in that it is usually necessary to start again from the placement and wiring of the logic cell.

A first object of the present invention is to reduce the power consumption by forming a channel width so that each transistor forming a logic circuit in a gate array satisfies an optimum driving capability. Secondly, it is possible to improve reusability so that the layout and wiring data of the already designed IC can be used in another manufacturing process by changing the channel width of the present invention.
The purpose is. Furthermore, a third object is to facilitate design automation by providing a variable region of the impurity diffusion layer in the basic cell and providing a structure in which the channel width can be changed by changing only the impurity diffusion layer.

[0008]

In order to solve such a problem, the present invention provides a mask and a contact formation for forming an impurity diffusion layer in a semiconductor integrated circuit in which basic transistor cells are formed in an array on a semiconductor substrate. The mask for forming the wiring layer and the mask for forming the wiring layer are changed so that the semiconductor manufacturing mask other than the mask for forming the impurity diffusion layer, the mask for forming the contact, and the mask for forming the wiring layer are not changed, and It is characterized in that it constitutes the function of a logic circuit.

Further, in the basic transistor cell, the impurity diffusion region having at least the power supply wiring region and the source / drain contact regions is set as the minimum size, and the channel width can be changed according to the desired transistor capability. It is characterized by having.

[0010]

According to the present invention, the channel width of the transistor can be optimized according to the connection state of the circuit and the cell arrangement / wiring state, so that the power consumption can be minimized with an equivalent function.
In addition, even for conventional gate array ICs developed with the highest priority for trial delivery, mass production after functional verification is completed.
By applying the present invention of optimizing the channel width of each transistor, power consumption can be minimized with an equivalent function.

Further, it becomes easy to reuse layout data having a proven record as a gate array IC for another manufacturing process.

Further, by setting the basic transistor size of the minimum channel width, the processing when changing the channel width can be easily realized by simply extending it in the variable region direction.

The channel-change type gate array according to the present invention means a gate array capable of forming transistors of a plurality of sizes by not fixing the impurity diffusion layer, instead of forming a circuit by a basic cell having a uniform size. What is different from the conventional gate array system is that the mask of the wiring layer and the contact is conventionally changed, whereas the mask is changed in the present invention to the impurity diffusion layer, the wiring layer and the contact.

[0014]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail below with reference to the drawings. FIG. 4 is a schematic plan view of a basic cell showing a first embodiment of the present invention, 7 is a PchMOS transistor constituting region, 8 is an NchMOS transistor constituting region,
9 is the gate of the MOS transistor, 10P is PchMO
S-transistor minimum channel width impurity diffusion region, 10
N is an impurity diffusion region of the NchMOS transistor minimum channel width. 11P is an impurity diffusion region having the maximum channel width of the PchMOS transistor, and 11N is an NchMOS.
This is an impurity diffusion region having the maximum channel width of the transistor.
12P is an impurity diffusion region which is an example of changing the PchMOS transistor channel width, and 12N is an impurity diffusion region which is an example of changing the NchMOS transistor channel width.

The size of the impurity diffusion region that determines the channel width of the transistor of each basic cell is determined by the driving capability required for the transistor.

FIG. 5 shows a NAN showing a second embodiment of the present invention.
In the D circuit layout diagram, 13 is a PchMOS transistor configuration region, 14 is an NchMOS transistor configuration region, 15 is a PchMOS impurity diffusion region, and 16 is an Nch.
MOS impurity diffusion region, 17 is Pch channel width variable region, 18 is Nch channel width variable region, 19 is VDD,
20 is VSS, 22 and 23 are NAND input terminals, 24
Is an output terminal. Based on a minimum channel width 21 having a power supply wiring region and a minimum impurity diffusion region capable of connecting the drain and source contacts of a transistor,
A MOS transistor structure capable of changing to a desired channel width is realized when more drive capability is required. With the basic cell structure, when the channel width is changed, only the impurity diffusion layer needs to be expanded and contracted in the directions of the variable regions 17 and 18. That is, the number of layers to be changed is one, and the change parameter is only one in the variable direction, and the basic cell structure of the present invention facilitates automation of layout change.

FIG. 6 is a diagram showing a channel width changing type gate array design flow of the present invention. On the design side, layout and wiring processing S2 is performed using an automatic layout system based on the netlist S1 of the logic circuit for which the logic design has been completed, and layout data satisfying the desired circuit function is created.
A wiring layer mask and a contact mask S4 are created from the layout data S3. Next, the transistor channel width optimization processing S5 is performed on the layout data S3 after the arrangement and wiring to create a mask of the impurity diffusion layer.

The channel width optimizing process S5 can be performed by the processing methods shown in FIGS. 7 and 8, for example.

In S3-1 of FIG. 7, the layout data S3-1 of the logic cell in which the total channel width is maximized is changed to the delay data S5- such as wiring capacitance as in the conventional gate array method.
1 is extracted, and the sum of the fan-out value of each logic cell, the capacity of its output net, and the fan-in value is compared and evaluated S5-2
If the driving capability is excessive, the channel width of the logic cell is reduced and changed S5-3. The channel width changing process is performed on all logic gates to determine the channel width of each transistor. After that, a transistor-level netlist in which the channel width is optimized is created, and timing verification S5-4 is performed using a high-speed analog circuit simulator or the like. It can be realized by the flow.

Alternatively, in the processing method of FIG. 8, the layout data S3-2 is arranged and wired with the minimum total channel width.
From the above, delay data S5-6 such as wiring capacitance is extracted in the same manner as described above, and a logic simulation after wiring in S5-7, that is, an actual wiring simulation is performed. Here, for the transistor having the timing error, the channel width is enlarged and changed to a size suitable for the timing S5-8. After that, a transistor level netlist in which the channel width is optimized is created in the same manner as described above, and timing verification S5-9 is performed using a high speed analog circuit simulator or the like. It can be realized by the flow.

On the other hand, on the semiconductor manufacturing side, the semiconductor manufacturing process before the impurity diffusion layer forming process is completed in advance, the impurity diffusion layer is formed by using the mask of the impurity diffusion layer, and then the conventional process before the contact formation is performed. Perform the manufacturing process. Next, a contact and a wiring layer are formed using the contact mask and the wiring mask to complete an IC satisfying a desired function and minimizing power consumption.

When the design flow and the manufacturing flow of the present invention are used, for example, in the case where the priority is given to the trial delivery, the conventional gate layer system in which only the wiring layer is changed is developed, and then the circuit of the present invention is constructed in the mass production. By the flow of optimizing the channel width of each transistor, it can be said that mass production of an IC with the equivalent power consumption and the lowest power consumption is achieved by short-term prototype development.

Further, according to the present invention, the layout data of the existing proven gate array can be reused for another manufacturing process. That is, conventionally, when the manufacturing process is changed, a timing error occurs due to a change in the wiring capacity or the transistor driving ability, so that it is necessary to start over from the arrangement of the logic cells and the wiring process. However, in the present invention, since the channel width can be changed, the timing error can be eliminated by reusing the existing placement and routing data S2 as it is and optimizing the channel width S5, as explained in the design flow of FIG. S6, S7 on the manufacturing side
The impurity diffusion layer mask created in step 1 and the existing contact mask and wiring mask can be integrated into ICs in different manufacturing processes.
Therefore, the existing layout data of the gate array can be reused for another manufacturing process.

[0024]

As described above, according to the present invention, the channel width of the transistor can be optimized according to the connection state of the circuit and the cell arrangement / wiring state, so that the power consumption can be minimized with an equivalent function. Further, even for the conventional gate array IC developed with the highest priority on the prototype delivery date, by applying the present invention of optimizing the channel width of each transistor in the mass production after the function verification, the equivalent function is obtained. Therefore, the power consumption can be minimized.

Further, there is an effect that it is easy to reuse the layout data having a proven record as the gate array IC for another manufacturing process.

Further, by setting the basic transistor size of the minimum channel width, the processing when changing the channel width can be easily realized by simply extending it in the variable region direction.

[Brief description of the drawings]

FIG. 1 is a bulk diagram for a gate array according to a conventional example.

FIG. 2 is a schematic plan view of a basic cell according to a conventional example.

FIG. 3 is a conventional gate array design flow chart.

FIG. 4 is a schematic plan view of a basic cell showing the first embodiment of the present invention.

FIG. 5 is a NAND circuit layout diagram showing a second embodiment of the present invention.

FIG. 6 is a flow chart of a channel width changing type gate array design of the present invention.

FIG. 7 is a flowchart showing a first channel width optimization processing example.

FIG. 8 is a flowchart showing a second channel width optimization processing example.

[Explanation of symbols]

1 basic cell 2 input / output buffer 3 PchMOS transistor configuration region 4 NchMOS transistor configuration region 5 MOS transistor gate 6 basic cell 7 PchMOS impurity diffusion region 8 NchMOS impurity diffusion region 9 MOS transistor gate 10P PchMOS transistor minimum channel width impurity diffusion region 10N NchMOS Transistor minimum channel width impurity diffusion region 11P PchMOS transistor maximum channel width impurity diffusion region 11N NchMOS transistor maximum channel width impurity diffusion region 12P PchMOS transistor channel width modification example impurity diffusion region 12N NchMOS transistor channel width modification example Certain impurity diffusion region 13 PchMOS transistor configuration region 14 Nc MOS transistor configuration region 15 PchMOS impurity diffusion region 16 NchMOS impurity diffusion region 17 Pch channel width variable region 18 Nch channel width variable region 19 VDD 20 VSS 21 Minimum channel width 22, 23 NAND input terminal 24 NAND output terminal S1 netlist S2 Placement. Wiring S3 Layout data S4 Contact mask, wiring mask S5 Channel width optimization S6 Impurity diffusion layer data S7 Impurity diffusion layer mask P1 Bulk forming process P2 Contact. Wiring layer forming step P1-1 Bulk forming step before impurity diffusion P1-2 Impurity diffusion layer forming step P1-3 Contact. Wiring layer forming process S3-1 Maximum layout data for all channel widths S5-1 Delay data extraction S5-2 Evaluation of driving capability S5-3 Change of channel width S5-4 Analog simulation verification S3-2 Minimum layout data for all channel widths S5-6 Delay Data extraction S5-7 Real wiring simulation S5-8 Changing channel width of transistor with timing error S5-9 Analog simulation verification

Claims (2)

[Claims] 1. In a semiconductor integrated circuit in which basic transistor cells are formed in an array on a semiconductor substrate, the mask for forming an impurity diffusion layer, the mask for forming a contact, and the mask for forming a wiring layer are changed, A semiconductor integrated circuit characterized by constituting a desired logic circuit function without changing a semiconductor manufacturing mask other than a mask for forming an impurity diffusion layer, a mask for forming a contact, and a mask for forming a wiring layer. 2. The basic transistor cell according to claim 1, wherein an impurity diffusion region having at least a power supply wiring region and a source / drain contact region is set as a minimum size, and a channel width can be changed according to a desired transistor capability. A semiconductor integrated circuit having a variable diffusion size region.