JPH0685064A - Manufacture of semiconductor integrated circuit and its device - Google Patents

Abstract

PURPOSE:To raise usage efficiency of chip area by preprocessing before execution of automatic arrangement/routing for variable cell height. CONSTITUTION:The information on a basic logical gate cell and logical macro cell in the circuit information stored in a memory 100 are converted into the information of such as a single transistor cell for each conduction type, series connection transistor cell, parallel connection transistor cell and connection between these cells, and then automatic arrangement/routing is processed by an arrangement/routing executing part 202. By this, each gate type and macro type can be designed into cells of different heights so that automatic arrangement/routing, accompanied by high usage efficiency of chip area, is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (hereinafter,
The present invention relates to a manufacturing apparatus and manufacturing method, and more particularly to a manufacturing apparatus and method for manufacturing a complementary MOS semiconductor integrated circuit to which automatic placement and wiring is applied.

[0002]

2. Description of the Related Art With the progress of semiconductor technology, there has been a strong tendency for electronic circuits, which are conventionally formed by combining individual transistors and standard gate ICs, to be integrated into semiconductor circuits. Since many of these are small-quantity, multi-product products and require a short development period, the design by automatic placement and routing using a calculation means such as a calculator is often used for the pattern design of the integrated circuit. That is, as shown in FIG. 42, the cells necessary for designing a desired circuit in the computer 101 are calculated based on the circuit information stored in the memory 100, and the cells are automatically connected by wiring. The configuration is such that placement and wiring are performed.

The most typical example of this is a complementary MOS type gate array. The gate array will be described below. 43 shows an example of a gate array chip configuration. In the figure, reference numerals 1a, 1b, 1c and 1d denote peripheral circuit portions 2a to 2a, each including a power supply input / output terminal and a circuit for connecting them to an internal circuit. Reference numeral 2g denotes a cell row composed of basic cells, and wiring regions 3a to 3f for connecting the basic cells are provided between the cell rows.

FIG. 44 shows the cell arrays 2a to 2a of the gate array.
It is a figure which shows the example of the basic cell which comprises 2g, 4a, 4b are N type MOS transistors, 5a, 5b in the figure.
Is a P-type MOS transistor. As shown in the figure, the basic cells that make up the cell array of the gate array are two N-type M
It is composed of an OS transistor and two P-type MOS transistors. These peripheral circuits 1a to 1d and the cell row 2
The positions a to 2g are fixed in advance to form a transistor level on the chip, and each basic cell is connected based on the circuit information to realize a desired integrated circuit.

A simple example of the connection between the cells is shown according to the drawing. FIG. 45 shows a 3-input × 2 AND-OR gate. In the figure, 6 indicates an AND-OR gate body, 7a to 7f indicate its input, and 8 indicates its output. This 3
FIG. 46 shows the AND × OR gate 6 of input × 2 by connecting N-type and P-type transistors.

In the figure, 9a and 9b are the three-input N of the preceding stage.
The output of the AND gate, where 10 is a power supply (hereinafter, VS
S) and 11 are + power supplies (hereinafter, referred to as VDD). FIG. 47 shows the circuit of FIG. 46 realized by interconnection of basic cells. The circuit is realized by five basic cells, the metal wiring of the first layer is a dotted line, and the metal wiring of the second layer is a broken line. It is shown in.

In the circuit of FIG. 46, the 3-input NAND in the preceding stage is used.
Three N-type and P-type transistors are used in each part, but the basic cell is an N-type and P-type transistor 2.
Since each transistor is formed as a unit, a surplus of the transistor occurs, but this is practically eliminated by connecting the source and drain of the extra transistor to the same potential.

It is possible to prepare many types of integrated circuits by changing the metal wirings by preparing several types of gate arrays or bodies of several dozen types depending on the expected circuit scale. Therefore, it is suitable for the development and production of products that are manufactured in very small quantities.

However, when designing a circuit that is expected to be used in a certain amount, it is difficult to reduce the chip area with the gate array. The biggest cause is
In the gate array, since each basic cell and the positions of the P-type transistor and the N-type transistor forming the basic cell are fixed in the chip, it is necessary to secure a large area for wiring in advance. This is because the utilization efficiency of the area must be lowered. In recent years, there is a type called a spread type gate array in which basic cells are spread over almost the entire internal circuit area of a chip and the basic cell is not used for the area necessary for wiring, but the area is used for the wiring area. However, the drawbacks mentioned above cannot be completely overcome.

As a circuit design method other than the above-mentioned gate array, there is a design method called a standard cell. This is because gates such as inverters, NAND gates and NOR gates, and various kinds of flip-flops, macros such as counters are designed and prepared in advance as cells of the same height, and they are calculated by a calculation means based on circuit information. An integrated circuit chip is constructed by automatically arranging and wiring.

FIG. 48 shows an example of the cell of the 3-input.times.2 AND-OR gate shown in FIG. Corresponding numbers in FIG.
Same as 7. The other cells having the same height H are formed. In the case of the standard cell method, unlike the case of the gate array, the cell arrangement is not fixed in advance, so that the area of the region where the cells are wired can be optimized according to the amount of wiring. As is often the case, the transistors in the cell are wasted.

However, the height of each cell is fixed as in the case of the gate array, and the chip layout cannot be optimized for the entire circuit. For example, if a cell is designed to realize a large-scale counter as a macro, there will be a lot of wasted space in the cell at the basic gate. Conversely, if the cell height is designed to be low, the counter etc. cannot be made into a macro. Need to expand to the level of small cells.

In addition, in the gate array and standard cell systems, there are many circuits whose area is difficult to reduce. As an example thereof, there is a multi-input AND-OR circuit which is often used for a sequential circuit. FIG. 49 shows a 3-input × 5 AND-OR circuit, in which 13a to 13o are inputs and 14 are outputs. If this circuit is manually designed, it can be designed as shown in FIG. That is, by connecting N-type transistors connected in series in a plurality of columns in parallel and pulling up by one P-type transistor, AN
It is realized by forming a D-OR inverter and inverting its output by the inverter. In FIG. 50, 15a to 15e are N-type transistors connected in series, 16 is a P-type pull-up transistor, 17 is an output of an AND-OR inverter, and 18 is an inverter. On the other hand, in the case of the gate array or standard cell method, a multi-input AND
In the -OR circuit, it is necessary to expand these into basic gates, and an increase in area cannot be avoided.

[0014]

Since the conventional gate array and standard cell IC are manufactured as described above, the height of the cell is fixed, so that a chip for a circuit to be integrated is formed. It was difficult to minimize the area.

The present invention has been made to solve the above problems, and a semiconductor capable of realizing a semiconductor integrated circuit with a higher chip area utilization efficiency while using a calculating means such as a calculator. An object is to provide an integrated circuit manufacturing apparatus and a manufacturing method.

[0016]

A semiconductor integrated circuit manufacturing apparatus and manufacturing method according to the present invention include a basic logic gate cell and a logic macro cell in circuit information stored in a storage means as a pre-stage of execution of automatic placement and routing processing. Preprocessing for developing the information of a single transistor cell, a cell in which a plurality of transistors are connected in series, a cell in which a plurality of transistors are connected in parallel, and wiring information for connecting these cells to each other for each conductivity type. It is the one that is supposed to be executed.

[0017]

According to the present invention, since the above-mentioned pre-processing is performed before the automatic placement and routing is performed as described above, the height of the cell can be made variable, and each of the semiconductor integrated circuits can be configured. It becomes possible to optimally arrange the conductive type transistors by using the automatic placement and routing process.

[0018]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a pattern diagram of a semiconductor integrated circuit manufactured by applying a semiconductor integrated circuit manufacturing apparatus according to a first embodiment of the present invention, and here is a diagram showing an example of arrangement of 3 input × 2 AND-OR circuits. 2 is a circuit diagram in which this AND-OR circuit is expanded to the transistor level. In the figure, the same reference numerals as those in FIGS. 42 and 43 denote the same or corresponding portions, and 19a, 19b, 19c are ANDs of 3 inputs × 2.
-N-type series transistor cell forming an OR circuit, 2
Reference numerals 0a, 20b, and 20c are P-type series transistor cells that form a 3-input × 2 AND-OR circuit.

Reference numerals 21a, 21b and 21c are N-type transistor cells used in other circuits, and 22a and 22c.
Reference numerals b and 22c are P-type transistor cells used in other circuits. These 19a to 19c, 20a to 20
c, 21a to 21c, 22a to 22c are expanded to the level of the transistor cell from the circuit information given in advance by a preprocessing method described later. For the placement and routing of these cells, almost the same automatic placement and routing method as that used in the standard cell type IC can be used.

That is, the semiconductor integrated circuit manufacturing apparatus according to the first embodiment of the present invention has a memory 100 as shown in FIG.
The basic logic gate cell and logic macrocell information in the circuit information stored in the memory is stored in a single transistor cell, a serial connection transistor cell, and a parallel connection transistor cell for each conductivity type by the information conversion unit 201 which constitutes the calculation means 200. , And after converting to the connection information between these cells,
The placement and routing execution unit 202 is configured to perform automatic placement and routing processing.

A preprocessing method for expanding circuit information into transistor cells will be described below. First, among circuit information, macros such as various flip-flops and counters are expanded to basic gates such as inverters, NAND gates, NOR gates, and transmission gates. As for this expansion, the description of the expansion of each macro may be made at the basic gate level in advance, as in the hierarchical expansion of the hierarchical circuit description.

Next, a method of expanding the basic gate level circuit description obtained by the above expansion into a transistor level circuit description will be described. In the following example, the circuit information will be described as a binary tree data structure having a specific structure, but the same technique can be realized with other data structures.

FIG. 5 shows a binary tree description of a basic gate of a circuit which takes inputs 1 to i as inputs and takes out outputs as shown in FIG. In the description of FIG. 5, the left element on the paper surface of the binary tree indicates the type of logic circuit, and the right element on the paper surface is the binary tree of the list of input / output nodes. I / O list 2
The tree is a node that connects the output to the left side of the head, and the right side makes the input node a binary tree in order from the node of input 1, and after reaching the last input node i, "empty" on the right side of the binary tree. Has a structure that ends with a NULL.

Therefore, for example, as shown in FIG.
1) In the case of a circuit having a series structure of N-type transistors, a binary tree of the type of “N-type series transistor” is obtained as shown in FIG. 7, and (i-1) pieces as shown in FIG. In the case of the parallel structure of the N-type transistor of FIG.
It is a binary tree of the type "type parallel transistor".

Next, an example of expanding a NAND gate into a transistor in this data structure will be shown. FIG. 10 shows a 3-input NAND gate, and FIG. 11 shows its binary tree description. When the 3-input NAND gate of FIG. 10 is described by a transistor, it becomes as shown in FIG.
As described above, it can be developed into an N-type series transistor and a P-type parallel transistor.

Therefore, the description of the NAND in FIG. 11 is as shown in FIG.
Binary tree of N-type series transistor as shown in Fig. 4 (Fig. 14 (a)
) And a P-type parallel transistor binary tree (FIG. 14 (b)). Single transistor cell of each pattern prepared in advance,
Correspondence between the serially connected transistor cell or the parallelly connected transistor cell and the circuit description by the binary tree corresponds to the length of the input list of each binary tree at the time of placement and wiring.

In order to perform this operation by the calculating means, first of all, the binary tree shown in FIG. 11 is divided as shown by a dotted line, and the binary tree shown in FIG. The binary tree shown in FIG. 16 of only the subsequent input list is extracted.

Then, the binary tree structure of FIG. 15 is duplicated, and as shown in FIG. 17, the left element "NAND" at the beginning of the tree is replaced with the "N-type series transistor", and the NULL at the end of the tree is replaced. Create a binary tree in which the left element is VSS and the right element is a null tree, and the left element "NAND" at the beginning of the tree is replaced with a "P-type series transistor" as shown in FIG. , Replaced the NULL at the end of the tree with a binary tree in which the left element is VDD and the right element is NULL.
Make a tree.

Then, the nulls at the ends of the binary tree of FIG. 17 and the binary tree of FIG. 18 are replaced with the binary trees of the input list created in FIG.
Two binary trees shown in can be generated. A program for causing the computer to perform this operation can be created by a general-purpose programming language or a list processing language such as LISP.

Although the NAND gate has been described above as an example, the NOR binary tree shown in FIG. 20 is converted into the N-type parallel transistor shown in FIG. 21B and two binary trees of the P-type series transistor binary tree of FIG. 21 (b).

As described above, according to this embodiment, the basic logic gate and the logic macro information in the circuit information are set to the single transistor cell, the series connection transistor cell, the parallel connection transistor cell, and each cell for each conductivity type. After the wiring information for connecting between is developed, automatic wiring processing is performed based on the developed information, so that gates and macros can be designed as cells of different heights, and the chip area can be used. Highly efficient automatic placement and routing can be performed.

Example 2. Next, a semiconductor integrated circuit manufacturing apparatus according to a second embodiment of the present invention will be described with reference to the drawings. Although the number of transistors in series is not limited in the above embodiment, it is actually difficult to prepare a corresponding series transistor for all numbers of transistors. It is necessary to set a maximum value for the number of, and to expand partially if there is more. That is, as shown in FIG. 22, the information conversion unit 20
The number of transistors connected in series obtained in 1 is counted, and when the value is larger than a predetermined value, the serial connection transistor cell obtained by expansion is further expanded as a second information expansion unit connected in series. It is necessary to provide the transistor redeployment unit 203. Hereinafter, a method for specifically implementing this in the above-mentioned preprocessing will be shown.

FIG. 23 is an example of a circuit in which seven N-type series transistors are connected in series. In order to expand this series transistor into a maximum of three series transistor arrays, as shown in FIG. 24, three transistors connected to inputs 1 to 3 are taken out from the VSS side, and an intermediate node 1 is provided in the middle, It may be divided into three series transistors and the remaining transistor portion. In FIG. 24, the remaining portion after taking out three transistors becomes four series transistors.
It may be divided into one transistor and the remaining one transistor portion.

The procedure for performing the above-described operation from the circuit information represented by the binary tree is shown below. FIG. 25 corresponds to FIG.
3 is a binary tree representation of a circuit consisting of 7 N-type series transistors of 3. First, the binary tree is divided by a dotted line, as shown in FIG.
As shown in, the type of the transistor cell, 2 up to the output
As shown in FIG. 27, the binary tree of the input list is divided into the binary tree of the input list and the binary tree of the input list. The binary tree of the source of the transistor and the three gate inputs 1 to 3, and Split into subsequent binary trees.

Next, as shown in FIG. 28, the source of the transistor and the binary tree of the three gate inputs 1 to 3 are connected to the binary tree of the series transistor whose output is the intermediate node (see FIG. 28). (a)), and the subsequent binary trees of inputs 4 to 7 are
The output is the original output node and the first input is connected to the binary tree of the series transistor, which is the intermediate node (FIG. 28).
(b)), the target binary tree shown in FIGS. 29 (a) and 29 (b) is developed. Most of the NAND circuits and NOR circuits commonly used in logic circuits have an input number of 5 or less, and most of them have an input number of 3 or less. Therefore, the maximum number of transistors should be 3 to 5. Optimal.

Example 3. Next, a semiconductor integrated circuit manufacturing apparatus according to a third embodiment of the present invention will be described with reference to the drawings. Although the number of transistors in series is restricted in the above-described embodiment, a maximum value is set for the number of transistors in parallel by the same method in this embodiment. It was designed to be deployed. That is, as shown in FIG. 30, a parallel connection transistor re-expansion unit 204 is provided as the second information expansion unit in place of the series connection transistor re-expansion unit of the second embodiment, and the parallel information obtained by the information conversion unit 201 is provided. The number of transistors to be connected is counted, and when the value is larger than a predetermined value, the parallel-connected transistor cell obtained by expansion is further expanded.

A method for implementing this concretely will be described below. FIG. 31 is an example of a circuit in which seven N-type parallel transistors are connected in parallel. Up to 3 parallel transistors
In order to develop the parallel transistor row, as shown in FIG. 32, three transistors connected to the inputs 1 to 3 are taken out from the left side and divided into these three series transistors and the remaining transistor portion. . In FIG. 32, the remaining part where three transistors are taken out becomes four parallel transistors, but the same operation is further performed for this, and it is sufficient to divide into three transistors and the remaining part.

In order to perform the operation described above from the circuit information represented by the binary tree, the following procedure is performed. FIG. 33 is a binary tree representation of the circuit composed of the seven N-type parallel transistors shown in FIG. First, this binary tree is divided by a dotted line to divide the binary tree up to the type of the transistor cell and the output and the binary tree of the input list as shown in FIG. 34, and the binary tree of the input list is further divided. As shown in FIG. 35, a source of a transistor, a binary tree of three gate inputs 1 to 3, and a binary tree after that are divided.

Next, as shown in FIG. 36, the source of the transistor and the binary tree of the three gate inputs 1 to 3 are the binary tree of the parallel transistor whose output is the original output node (see FIG. a)), the binary tree of the subsequent inputs is connected to the binary tree (FIG. 36 (b)) of the parallel transistor whose output is the original output node and whose first input is VSS.
It can be expanded to the two binary trees shown in FIGS. 37 (a) and 37 (b).

Example 4. Next, a semiconductor integrated circuit manufacturing apparatus according to a fourth embodiment of the present invention will be described. Third above
In the embodiment, the number of transistors in parallel is limited, but in general, a parallel-connected transistor cell has a reduction rate of a cell area with respect to a single-transistor cell as compared with a series-connected transistor cell. Therefore, it is conceivable that the arrangement and wiring are performed by using only the transistor cells connected in series and the single transistor cell without using the transistor cells connected in parallel. In this case, the method of the third embodiment can be implemented by expanding the circuit information with the number of transistors in parallel being one.

Example 5. Next, a semiconductor integrated circuit manufacturing apparatus according to a fifth embodiment of the present invention will be described with reference to the drawings. Although the basic gate is shown in each of the above-mentioned embodiments, all the circuit information of the semiconductor integrated circuit according to the present invention is expanded to the transistor level before the placement and wiring, so that the original circuit shown in FIG. Multi-input AND like
It is possible to mix -OR circuits described at the transistor level and perform a pattern arrangement as shown in FIG. In the figure, 10a and 10b are two VSS wirings. When integrating a large-scale sequential circuit such as a CPU into an integrated circuit, a circuit of this configuration is often used, and the number of N-type transistors in the circuit is much larger than the number of P-type transistors. Therefore, in such automatic cell arrangement of a large-scale sequential circuit, by arranging P-type transistors in one row and arranging N-type transistors connected thereto in a plurality of rows adjacent to that row as shown in FIG. Chip area efficiency is improved.

An example of the arrangement of the entire integrated circuit in this case is shown in FIG.
become that way. In the figure, 1a to 1d are peripheral circuits, 3
a to 3f are wiring regions between cells, 23a to 23d are N-type transistor cell lines, and 24a to 24c are P-type transistor cell lines.
The number of type transistor cell rows is smaller than that of N type transistor cell rows.

Example 6. Next, a semiconductor integrated circuit manufacturing apparatus according to a sixth embodiment of the present invention will be described with reference to the drawings. In this embodiment, when the information of the logic gate cell and the logic macro cell is expanded to the single transistor cell information, the single transistor cells of different channel lengths are used to expand the information as necessary.

That is, in the fifth embodiment, the P-type transistor 16 forming the AND-OR inverter of FIG. 38 has the same size as a normal P-type transistor, but in this embodiment, it is shown in FIG. As described above, the size (channel length) can be made variable by designating and arranging another type of transistor 16a in the circuit description.

Example 7. Next, a semiconductor integrated circuit manufacturing apparatus according to a sixth embodiment of the present invention will be described with reference to the drawings. In each of the above-described embodiments, the distance between the P-type cell row and the N-type cell row can be reduced to an interval limited by the number of wirings arranged therein, but When the number of cells is very small, the interval between the P-type cell row and the N-type cell row after the cell arrangement becomes too narrow, and latch-up may occur easily. In this embodiment, in order to avoid the risk of latch-up, it is verified whether or not the distance between the P-type cell row and the N-type cell row is longer than a certain distance after the cell rows are arranged, and if it is short. When an object is found, the interval between the corresponding P-type cell row and N-type cell row is widened to a predetermined distance, and then the wiring is corrected.

FIG. 41 shows a block diagram of this embodiment. In the figure, 205 is a placement and routing execution block 202.
After the placement and routing process is performed in step 1, the placement interval that issues a command to the placement and routing execution unit 202 to verify the spacing between the P and N-type cell rows and increase the spacing for those that may latch up. It is a control unit.

[0047]

As described above, according to the present invention, in the semiconductor integrated circuit in which the placement and routing is automatically performed based on the circuit information by using the calculating means such as a computer, the step is performed before the placement and routing process. , Basic logic gate cells and logic macrocells in the circuit information, information on a single transistor cell for each conductivity type, a cell in which a plurality of transistors are connected in series, a cell in which a plurality of transistors are connected in parallel, and these cells are mutually connected. Since the pre-processing that expands the wiring information to be connected to the cell is performed, the cell height can be made variable, and each conductive type transistor that constitutes the semiconductor integrated circuit can be processed by the automatic placement and wiring processing. The effect is that it can be optimally arranged.

[Brief description of drawings]

FIG. 1 is a diagram showing an arrangement example of a 3-input × 2 AND-OR circuit obtained by a semiconductor integrated circuit manufacturing apparatus according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram in which the three-input × 2 AND-OR circuit is expanded to a transistor level.

FIG. 3 is a block configuration diagram of the semiconductor integrated circuit manufacturing apparatus.

FIG. 4 is a diagram showing a basic gate that receives inputs 1 to i and extracts outputs.

FIG. 5 is a diagram showing a binary tree description of the basic gate.

FIG. 6 is a diagram showing i to 1 N-type transistors connected in series.

FIG. 7 is a diagram showing a binary tree description of the N-type transistors connected in series.

FIG. 8 is a diagram showing i to 1 N-type transistors connected in parallel.

FIG. 9 is a diagram showing a binary tree description of the N-type transistors connected in parallel.

FIG. 10 is a diagram showing a 3-input NAND gate.

FIG. 11 is a diagram showing a binary tree description of the 3-input NAND gate.

FIG. 12 is a circuit diagram in which the three-input NAND gate is described by a transistor.

FIG. 13 is a circuit diagram showing that the three-input NAND gates are connected in series with N
FIG. 3 is a circuit diagram divided into blocks of a type transistor and a P-type transistor connected in parallel.

FIG. 14 is a circuit description of the 3-input NAND gate,
It is a figure showing what was expanded to a binary tree description of a N-type transistor of serial connection and a binary tree transistor of a P-type transistor of parallel connection.

FIG. 15 is a diagram showing a binary tree description obtained by extracting from the binary tree of FIG. 11 to the type and output of the logic circuit.

16 is a diagram showing a binary tree description of the input list, which is the rest of the binary tree of FIG. 11 extracted from the binary tree of FIG. 11;

FIG. 17 is a diagram showing a binary tree description of an N-type series transistor made from the binary tree of FIG. 15;

FIG. 18 is a diagram showing a binary tree description of a P-type parallel transistor made from the binary tree of FIG. 15;

FIG. 19 is a diagram showing a 3-input NOR gate.

FIG. 20 is a diagram showing a binary tree description of the 3-input NOR gate.

FIG. 21 shows the expanded circuit description of the NOR gate of 3 inputs into a binary tree description of an N-type transistor connected in parallel and a binary tree description of a binary tree transistor of a P-type transistor connected in series. It is a figure.

FIG. 22 is a block configuration diagram of a semiconductor integrated circuit manufacturing apparatus according to a second embodiment of the present invention.

FIG. 23 is a circuit diagram of seven N-type series transistors.

FIG. 24 is a diagram showing a circuit obtained by dividing the circuit of the N-type series transistor into three series transistors and the remaining transistors.

FIG. 25 is a diagram showing a binary tree description of the circuit of the N-type series transistor.

FIG. 26 is a diagram showing the binary tree of FIG. 25 divided into two binary trees.

FIG. 27 is a diagram showing the binary tree of the input list of FIG. 26 divided into binary trees up to three gate inputs and binary trees after that.

28 is a diagram showing the binary tree shown in FIG. 27 in which binary trees to which respective inputs are connected are generated.

FIG. 29 is a diagram showing a result of dividing the binary tree of the seven N-type series transistors into a binary tree of three series transistors and a binary tree of the remaining series transistors.

FIG. 30 is a block configuration diagram of a semiconductor integrated circuit manufacturing apparatus according to a third embodiment of the present invention.

FIG. 31 is a circuit diagram of seven N-type parallel transistors.

FIG. 32 is a diagram showing a circuit obtained by dividing the circuit of the N-type parallel transistor into three series transistors and the remaining transistors.

FIG. 33 is a diagram showing a binary tree description of the circuit of the N-type parallel transistor.

FIG. 34 is a diagram showing the binary tree of FIG. 33 divided into two binary trees.

FIG. 35 is a diagram showing the binary tree of the input list in FIG. 33 divided into binary trees up to three gate inputs and subsequent binary trees.

36 is a diagram showing the binary tree of FIG. 35 in which binary trees to which respective inputs are connected are generated.

FIG. 37 is a diagram showing a result of dividing the binary tree of the seven N-type parallel transistors into a binary tree of three parallel transistors and a binary tree of the remaining parallel transistors.

FIG. 38 is a layout diagram of a 3-input × 5 AND-OR circuit manufactured by the semiconductor integrated circuit manufacturing apparatus according to the fifth embodiment of the present invention.

FIG. 39 is a layout diagram of cell columns in the entire chip of the AND-OR circuit of 3 inputs × 5.

FIG. 40 is a layout diagram of a 3-input × 5 AND-OR circuit manufactured by the semiconductor integrated circuit manufacturing apparatus according to the sixth embodiment of the present invention.

FIG. 41 is a block configuration diagram of a semiconductor integrated circuit manufacturing apparatus according to a seventh embodiment of the present invention.

FIG. 42 is a block configuration diagram of a conventional semiconductor integrated circuit manufacturing apparatus.

FIG. 43 is a diagram showing a chip configuration example of a complementary MOS gate array.

FIG. 44 is a diagram showing an example of a basic cell of the gate array.

FIG. 45 is a diagram showing a 3-input × 2 AND-OR gate;

FIG. 46 is a circuit diagram showing the AND-OR gate of 3 inputs × 2 by connecting N-type and P-type transistors.

FIG. 47 is a diagram showing an example in which the 3-input × 2 AND-OR gate is configured by a basic cell of a gate array.

FIG. 48 is a diagram showing an example of a standard cell of the AND-OR gate of 3 inputs × 2.

FIG. 49 is a diagram showing a 3-input × 5 AND-OR circuit;

FIG. 50 is a diagram showing a circuit design example in the case of manually designing the 3-input × 5 AND-OR circuit.

[Explanation of symbols]

1a to 1d Transmission line 2a to 2g Cell array of gate array 3a to 3f Wiring region 4a, 4b N-type MOS transistor 5a, 5b P-type MOS transistor 6 3 input × 2 AND-OR gate 7a to 7f 3 input × 2 AND-OR gate input 8 3 inputs × 2 AND-OR gate output 9a, 9b 3 inputs × 2 AND-OR gate preceding 3-input NAND output 10, 10a, 10b − Power supply (VSS) 11 + Power supply (VDD) 12 3 input × 5 AND-OR gate 13a to 13o 3 input × 5 AND-OR gate input 14 3 input × 5 AND-OR gate output 15a to 15e Series-connected N-type transistor 16 P-type pull-up transistor 16a P-type pull-up transistor with changed dimensions 17 AND-OR inverter output 18 a Bata 19a to 19c N-type series transistor cells 20a to 20c P-type parallel transistor cells 21a to 21c N-type transistor cells 22a to 22c used in other circuits P-type transistor cells 23a used in other circuits -23d N-type transistor cell row 24a-24c P-type transistor cell row 100 Memory (storage means) 200 Calculation means 201 Information conversion section 202 Placement and wiring execution section 203 Series connection transistor re-expansion section 204 Parallel connection transistor re-expansion section 205 Placement interval controller

Claims (14)

[Claims] 1. A complementary MOS semiconductor integrated circuit for automatically arranging and wiring cells based on circuit information including basic logic gate cells for forming a logic circuit, logic macrocell information, and interconnection information thereof. In a device for manufacturing a circuit, storage means for storing circuit information including the basic logic gate cell information, logic macrocell information, and interconnection information thereof, and the basic logic gate cell and logic macrocell information stored in the storage means. To a single transistor cell for each conductivity type, serial connection transistor cell, parallel connection transistor cell information, and wiring information for connecting these cells to each other, and an information conversion unit that automatically converts the cells based on these information. And a calculation means having a placement and routing execution unit for performing wiring placement and wiring connection between cells. The semiconductor integrated circuit manufacturing equipment. 2. The semiconductor integrated circuit manufacturing apparatus according to claim 1, wherein when the number of transistors forming the series-connected or parallel-connected transistor cells is a predetermined value or more, A semiconductor integrated circuit manufacturing apparatus having a second information conversion unit for replacing information with information of a plurality of series transistor cells or parallel connection transistor cells having a predetermined value or less. 3. The semiconductor integrated circuit manufacturing apparatus according to claim 2, wherein the second information conversion unit is configured so that the number of transistors forming the series-connected or parallel-connected transistor cells is 3 to 5 pieces. A semiconductor integrated circuit manufacturing device characterized by performing conversion. 4. The semiconductor integrated circuit manufacturing apparatus according to claim 1, wherein the information conversion section outputs a plurality of types of information having different channel lengths as the information of the single transistor cell during the information conversion. A semiconductor integrated circuit manufacturing apparatus characterized by the above. 5. The semiconductor integrated circuit manufacturing apparatus according to claim 1, wherein the information conversion unit converts each of the basic logic gate cells and the logic macrocell information stored in the storage means for each conductivity type. 2. A semiconductor integrated circuit manufacturing apparatus, wherein the information of the single-transistor cell and the serial-connection transistor cell is used to replace the information of the parallel-connection transistor cell. 6. The semiconductor integrated circuit manufacturing apparatus according to claim 1, wherein the information conversion section is the same as each cell information obtained after the information conversion, except that it is composed of a large number of conductivity type transistor cell information. A semiconductor integrated circuit manufacturing device characterized by being arranged in rows. 7. The semiconductor integrated circuit manufacturing apparatus according to claim 1, wherein the information conversion unit detects a space between adjacent cells having different conductivity after the cells are arranged. If the cells are arranged at intervals less than or equal to a predetermined value, the arrangement and wiring execution unit is controlled so that the distance between the cells is kept at a predetermined value or more, and a rearrangement controller for rearrangement is provided. And a semiconductor integrated circuit manufacturing apparatus. 8. A complementary MOS semiconductor integrated circuit for automatically arranging and wiring cells based on circuit information including basic logic gate cells for forming a logic circuit, logic macrocell information, and interconnection information thereof. In the method for manufacturing the above, the basic logic gate cell and logic macrocell information is replaced with information on a single transistor cell for each conductivity type, a series connection transistor cell, a parallel connection transistor cell, and wiring information for connecting these cells to each other. A method for manufacturing a semiconductor integrated circuit, wherein a complementary MOS semiconductor integrated circuit is manufactured by automatically arranging cells and connecting wirings between the cells based on the information. 9. The method of manufacturing a semiconductor integrated circuit according to claim 8, wherein when the number of transistors forming the series-connected or parallel-connected transistor cells is a predetermined value or more, the series-connected transistor cell or parallel-connected transistor cell. Is replaced with a plurality of serial connection transistor cell information or a plurality of parallel connection transistor cell information each having a predetermined value or less. 10. The method for manufacturing a semiconductor integrated circuit according to claim 8, wherein information conversion is performed so that the number of transistors forming the series-connected or parallel-connected transistor cells is 3 to 5. Manufacturing method of semiconductor integrated circuit. 11. The method of manufacturing a semiconductor integrated circuit according to claim 8, wherein a plurality of kinds of information having different channel lengths are used as the information of the single transistor cell. 12. The method of manufacturing a semiconductor integrated circuit according to claim 8, wherein when converting the basic logic gate cell and logic macrocell information stored in the storage means, a single transistor cell for each conductivity type. A method of manufacturing a semiconductor integrated circuit, characterized in that the information of the parallel-connected transistor cell is obtained by using the information and the serial-connection transistor cell information. 13. The method for manufacturing a semiconductor integrated circuit according to claim 8, wherein each cell information obtained after the information conversion is arranged in the same column only with a large number of conductive type transistor cell information. A method for manufacturing a semiconductor integrated circuit, comprising: 14. The method for manufacturing a semiconductor integrated circuit according to claim 8, wherein when cells having different conductivity are arranged adjacent to each other after the cells are arranged, the distance between the cells is a predetermined value. A method of manufacturing a semiconductor integrated circuit device, comprising rearranging so as to maintain the above.