JP3474591B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of laying out a mask pattern. 2. Description of the Related Art Conventionally, there have been the following methods for laying out a mask pattern of a semiconductor integrated circuit device. First, there is a method of determining the arrangement and wiring of elements such as transistors to be formed on a semiconductor substrate by manual design every time. According to this method, a highly integrated device can be obtained, but a long development period is required. There is another method, such as a gate array, in which elements such as transistors are formed in advance in a semiconductor wafer in an array and prepared, and only a wiring layer is formed on the surface according to the intended use. According to this method, the development period can be shortened. There is also a method in which cells are registered in advance, and the registered cells are combined and laid out. This is generally called the standard cell method, and is located between the above two methods. The shape, arrangement, and wiring of elements in one cell are designed in advance for each cell. By deciding the combination of such cells and the wiring between the cells,
Lay out the mask pattern. After the layout is once determined by any of the methods, there is a case where only the design rule is changed without changing the configuration of the logic circuit. That is, when laying out a pattern, the dimensions of the transistor, the width of the wiring layer, the distance between the wiring layers, the wiring material, and the like are determined based on a certain rule. After the pattern layout of a certain integrated circuit device is determined in this way, another integrated circuit device having the same logical configuration may be manufactured by changing the dimensions and the like of the transistor. In such a case, conventionally, the layout of the existing pattern had to be redone from the beginning, and the same development period and cost as in the case of newly designing from the beginning were required. As described above, when manufacturing another device having the same configuration on a logic circuit as the device on which a pattern has already been laid out and having only a different design rule, conventionally, an existing pattern is used. It takes the same time and cost as designing a new one without using the layout. The present invention has been made in view of the above circumstances, and by shortening the period for laying out a pattern,
Provided is a method for manufacturing a semiconductor integrated circuit device that can reduce a period and cost required for manufacturing. A method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of extracting circuit data from existing pattern data on which a first mask pattern is laid out. The first circuit data
Converting the first mask pattern into the first symbolic data indicating the relative positional relationship of each pattern element corresponding to the mask pattern, and changing the design rule by using the first mask pattern when laying out the first mask pattern. Generating a second symbolic data by changing at least the dimensions of the transistor and the wiring layer on the first symbolic data based on the design rule; and using the second symbolic data to generate the dimension of the transistor. To a minimum necessary size, share a sharable area between adjacent cells, and obtain third symbolic data;
Generating a second mask pattern using the third symbolic data; and forming an element and a wiring layer on a semiconductor substrate using the second mask pattern. Features. According to the present invention, circuit data is extracted from existing pattern data indicating a state in which a first mask pattern is laid out, and this circuit data is extracted from each pattern element corresponding to the first mask pattern. Is converted to first symbolic data indicating the relative positional relationship of By changing the design rule used when laying out the first mask pattern and changing at least the dimensions of the transistor and the wiring layer on the first symbolic data based on the design rule, the second symbolic data is changed. Generate. This second
The size of the transistor is reduced to a necessary minimum by using the symbolic data of (1), a sharable area is shared between adjacent cells, and third symbolic data is obtained. A second mask pattern is generated using the obtained third symbolic data, and an element and a wiring layer are formed on the semiconductor substrate using the second mask pattern. In this way, by changing the cell size on the symbolic data by making use of the existing pattern data, even when newly manufacturing a device in which the circuit on which the pattern data exists and the configuration on the circuit are the same and only the dimensions are different, The generation of mask patterns is easy, and the manufacturing period and cost are reduced.
By sharing the sharable region, a highly integrated device can be manufactured. An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, when a mask pattern of a certain integrated circuit device is laid out, a database is created as symbolic data so that it can be used later as a design resource when designing another device. When manufacturing a device having the same circuit configuration but different element dimensions, the database is used to change the design rules to be referred by a designer when generating a layout, so that the dimensions and wiring layers of the elements are changed. To change the width and so on. First, a layout method for making a laid-out pattern available as a database later will be described. This uses a method called a symbolic method which is an extension of the standard cell method. A symbolic cell is a symbolic representation of a mask layout, in which transistors, contacts, terminals and the like are symbolized and connected by wires called sticks. The symbolic cell is
It is registered in the form of a stick diagram described later, and includes N-channel MOS transistor and P-channel MO
There are S transistors, wires, power supply lines, contacts, vias, and the like. The relative positional relationship between these components and wires corresponds to the relative positional relationship in the mask layout. As an example, a two-input NA as shown in FIG.
The case of generating a mask pattern for an ND gate will be described. The two-input NAND gate generally has two N-channel transistors N as shown in FIG.
1, N2 and P-channel transistors P1 and P2. FIG. 5 shows a stick diagram of the two-input NAND gate. As described above, transistors, contacts, terminals, and the like are symbolically represented as symbolic cells, and each symbolic cell is connected by a wire having no width. In a region 50, a P-channel transistor P
1, P2 are formed. P-channel transistor P
1 and a source 52 of the P-channel transistor P2 are connected to a power supply voltage VDD line 56, respectively. Drain 5 of P-channel transistors P1 and P2
3 is commonly connected to the output terminal C. The gate 54 of the P-channel transistor P1 is connected to the input terminal A,
The gate 55 of the P-channel transistor P2 is connected to the input terminal B
It is connected to the. In the region 60, an N-channel transistor N
1, N2 are formed. N-channel transistor N
1 is connected to the output terminal C, and the gate 63
Are connected to the input terminal B. The source 61 of the N-channel transistor N2 is connected to the ground voltage VSS line 65,
Gate 62 is connected to input terminal A. When such a stick diagram is processed on a computer, the dimensions of each symbolic cell represented by the stick diagram can be changed and set according to the application. For example, when the inverter cells are arranged adjacent to each other, if the diffusion contacts can be used in common, the size of the cells can be reduced by sharing the diffusion contacts. FIG. 6 shows an actual mask pattern generated based on the stick diagram obtained in this manner. In a region 10, P-channel transistors P1,
P2 is formed. The source region 11 of the P-channel transistor P1 and the source region 12 of the P-channel transistor P2 are arranged on both sides of the region 10, and the drain regions 13 of the P-channel transistors P1 and P2 are formed in the center in common. An N-channel transistor N1,
N2 is formed. In this region 20, a source region 21 of the N-channel transistor N2 and a drain region 24 of the N-channel transistor N1 are formed. Further, the gate region 14 of the P-channel transistor P1 and the gate region 22 of the N-channel transistor N2 are connected to the contact region 31 of the input terminal A. Gate region 15 of P-channel transistor P2
And the gate region 23 of the N-channel transistor N1 are connected to the contact region 32 of the input terminal B. Drain regions 13 of P-channel transistors P1 and P2 and N
The drain region 24 of the channel transistor N1 is connected to the contact region 33 of the output terminal C. FIG. 3 shows a procedure for generating a mask pattern using this symbolic method. EWS (ENGINE
A circuit diagram is created using ERING WORKSTATION) (step 121). FIG. 7 shows a specific example of this circuit diagram. A circuit description net is created based on the circuit diagram (step 122). This circuit description net indicates wiring connection information between cells, and FIG. 8 shows an example thereof. Based on the created circuit description net, standard cells are arranged and wired using an automatic routing tool (router) (step 123). Next, the standard cell is replaced with a symbolic cell that can be represented by a stick diagram as described above (step 124). The standard cell and the symbolic cell have a one-to-one correspondence. The dimensions of the transistor, the width of the wiring layer, the spacing, the wiring material, etc. are specified with reference to design rules that define certain rules (step 125), and a mask pattern is generated (step 126). When a mask pattern is generated according to such a procedure, the mask pattern is stored as a database as symbolic data. The present embodiment is characterized in that a semiconductor integrated circuit device is manufactured by effectively utilizing this database to generate a mask pattern having the same logic circuit but different dimensions such as transistors. FIG. 1 shows a method of manufacturing a semiconductor device according to a first embodiment of the present invention for each process. First, there is existing pattern data in which a pattern is laid out based on the above-described procedure. Circuit data is extracted from the existing pattern data (step 101). That is, the pattern data is converted back to the original logic circuit. However, the extracted circuit data and the logic circuit itself are not completely the same. For example, the extracted circuit data includes data such as wiring materials such as aluminum and polycrystalline silicon used in accordance with a pattern, dimensions of a transistor, and the like. On the other hand, there is no specification of the wiring material, the dimensions of the transistor, and the like in the logic circuit. Next, the circuit data is converted into symbolic data (step 102). Then, the design rules used when generating the existing pattern data are changed according to the specifications of the device to be manufactured this time. As described above, the design rules define rules to be referred to by the designer when determining the width, interval, wiring material, and the like of each transistor and wiring layer. Based on the changed design rule, the dimensions and the like of each transistor and wiring layer are changed on the symbolic data (step 103). This allows
New symbolic data is obtained. A mask pattern is generated based on the obtained symbolic data (step 104).
Using this mask pattern, elements such as transistors and wiring layers connecting the elements are formed on a semiconductor substrate (step 105). As described above, after extracting the circuit data from the existing pattern data and converting it into symbolic data,
By changing the design rule to change the dimensions of the transistor, the width of the wiring layer, and the like, it is possible to easily generate a mask pattern having the same logic circuit but different dimensions and materials. Even when the dimensions of a transistor are changed uniformly, all dimensions can be automatically changed at the stage of symbolic data only by changing the design rule, thereby greatly improving productivity. Therefore, the period until the mask pattern is generated is shortened, and the cost is reduced. Next, a second embodiment of the present invention will be described. In the present embodiment, in addition to the steps of the first embodiment, a step for improving the degree of integration is further provided. FIG. 2 shows the procedure of the manufacturing method according to this embodiment. As in the first embodiment, the circuit data is extracted from the existing pattern data (step 101), the circuit data is converted into symbolic data (step 102), and the design rule is changed to change the dimensions of the transistor on the symbolic data. Are changed to generate new symbolic data (step 103). Using this new symbolic data,
Change the dimensions of the transistors and the like to the minimum necessary size. At the same time, patterns that can be shared between adjacent symbolic cells are shared (step 11).
2). The new stick figure obtained in this way is converted into symbolic data to generate a mask pattern (step 113). Using this mask pattern, elements such as transistors and wiring layers connecting the elements are formed on a semiconductor substrate (step 114). FIG. 9 shows a mask pattern before the size is reduced in step 112, and FIG. 10 shows a mask pattern after the size is reduced. Here, a case is shown where the channel width of the P-channel transistor is reduced from 85 μm to 30 μm, and the channel width of the N-channel transistor is reduced from 62 μm to 20 μm. FIG. 11 shows a specific example in which a part of the mask pattern is shared. FIG. 11A shows a mask pattern in a state where two inverters IN1 and IN2 are adjacent to each other. No sharing is attempted in this mask pattern. Here, a contact region for connecting the diffusion layer and the wiring layer can be shared between the inverters IN1 and IN2. That is, the contact region 1 of the inverter IN1 and the contact region 2 of the inverter IN2, and the contact region 3 of the inverter IN1 and the contact region 4 of the inverter IN2 can be shared. In the mask pattern shown in FIG. 11B, a contact region 5 is provided by sharing the contact regions 1 and 2 between the inverters IN1 and IN2, and a contact region is provided by sharing the contact regions 3 and 4. 6 are provided. Thereby, the pattern area can be reduced, and the degree of integration can be improved. The preferred embodiment has been described above.
The present invention is not limited to this embodiment, and includes various modifications and other embodiments within its scope. For example, when changing the design rule, it is not necessary to change all of the dimensions of the transistor, the width of the wiring layer, the interval between the wiring layers, the wiring material, and the like. The invention can be applied. As described above, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, the circuit configuration is the same as that of the logic circuit having the pattern data,
When manufacturing a new device by changing the material, etc., a mask is used to extract circuit data from existing pattern data, change design rules and change transistor dimensions, wiring layer width, etc. on symbolic data. Patterns can be easily generated, and the time and cost required for manufacturing can be reduced. Further, by performing a process of sharing a sharable area with symbolic data obtained by changing a design rule, it is possible to manufacture a highly integrated device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention for each process. FIG. 2 is a flowchart showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention for each process. FIG. 3 is a flowchart showing steps when generating existing pattern data used in the first and second embodiments. FIG. 4 is an explanatory diagram showing symbols on a circuit diagram of a NAND gate. FIG. 5 is an explanatory diagram showing a symbolic diagram of the NAND gate. FIG. 6 is an explanatory diagram showing a mask pattern corresponding to the symbolic diagram. FIG. 7 is a circuit diagram showing an example of a logic circuit applicable to the present invention. FIG. 8 is an explanatory diagram showing a circuit description net corresponding to the circuit shown in FIG. 7; FIG. 9 is an explanatory diagram showing a mask pattern in a stage before the size of a transistor is reduced in the second embodiment of the present invention. FIG. 10 is an explanatory view showing a mask pattern in a stage after the size of the transistor is reduced in the second embodiment. FIG. 11 is an explanatory diagram showing a mask pattern when a contact region is shared by adjacent inverters in the second embodiment of the present invention. [Description of Signs] 1, 2, 3, 4, 5, 6 Contact regions 10, 20, 50, 60 Regions 11, 12, 21, 51, 52, 61 Source regions 13, 24, 53, 64 Drain regions 14, 15, 22, 23 Gate areas IN1, IN2 Inverters OUT1, OUT2 Output terminals

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-63-159980 (JP, A)                 JP-A-4-186865 (JP, A)                 JP-A-4-37155 (JP, A)                 JP-A-4-137661 (JP, A)

Claims (1)

(57) Claims 1. A step of extracting circuit data from existing pattern data in which a first mask pattern is laid out, and extracting the extracted circuit data with the first mask pattern. Converting the first mask pattern into the first symbolic data indicating the relative positional relationship of each pattern element corresponding to the mask pattern; and changing the design rule used when laying out the first mask pattern. Changing at least the dimensions of the transistor and the wiring layer on the first symbolic data based on the design rule to generate second symbolic data; and using the second symbolic data to determine the dimension of the transistor. Obtaining the third symbolic data by reducing the size to the minimum necessary, sharing a sharable area between adjacent cells, and A step of generating a second mask pattern using the third symbolic data; and a step of forming an element and a wiring layer on a semiconductor substrate using the second mask pattern. A method for manufacturing a semiconductor integrated circuit device.