JPH01100942A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable modification of circuit to be realized by change of a process after the process of formation of a wiring layer, by providing a source/drain diffusion layer and a gate wiring layer constituting an MOS transistor together with a wiring layer within a field cell so that the element can be employed when any change is required for modification of the circuit or the like. CONSTITUTION:In order to provide a circuit as represented by an equivalent circuit of Fig. (a), a NOR gate standard cell 31 and an inverter standard cell 32 are arranged and a required number of feed cells, for example three feed cells 13A-13C are arranged in the cell array. A wiring layer is provided to connect the cells 31, 32 with each other. An LSI can be produced in this manner. If it is desired to add another circuit 25 consisting of an inverter 23 and a NAND gate 24 to the LSI thus produced, as shown in Fig (b), such circuit 25 consisting of the inverter 23 and the NAND gate 24 can be added only by changing the final process, namely process of forming the wiring layer of multilayer aluminum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit using a standard cell method, and particularly relates to an improvement that allows the circuit to be easily modified.

(Prior Art) FIG. 5 is a plan view showing the entire configuration of an LSI chip based on a standard cell method automatically designed using an electronic meter. The chip body 10 includes a plurality of cell rows 11 in which a plurality of standard cells are arranged in a row.

Furthermore, in addition to the cell array 11, a macro cell 12 made of, for example, a memory is configured. In each of the cell rows 11, the number of standard cells used is not necessarily the same, so the width alignment between each cell row 11 and each cell row 1
For the purpose of supplying power supply voltage to each cell column 11, a necessary number of feed cells (Feed Ce11) 13 are arranged in each cell column 11.

Conventionally, as shown in the plan view of FIG. 6, this feed cell 13 has a pair of wiring layers 15A made of aluminum, for example, for supplying iffff pressure voltages on a high potential side and a low potential side;
15B, and if the conductivity type of the substrate used is, for example, P type, an N type well region 16 is provided. , and then arrange the required number of feed cells for a certain cell row, and 11g! (not shown)! The power supply voltage on the high potential side and low potential side from the wiring is connected to each pair of wiring WJ15.
A and 15B, respectively, and the signal is supplied to each standard cell in the corresponding cell column.

By the way, in such a standard cell type LSI, if it becomes necessary to modify the circuit due to, for example, a change in specifications after prototyping, conventionally, the circuit is remanufactured from the first step.

For this reason, conventionally there have been problems such as an increase in the LSI development period and the cost for the IFII.

(Problem to be solved by the invention) Conventionally, if a circuit needs to be modified after a prototype is manufactured, it is manufactured again from the beginning, which increases the development period and development cost. There is a problem.

The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide a semiconductor integrated circuit using a standard cell method that can reduce the development period and development cost.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor integrated circuit of the present invention provides a source, drain diffusion layer, and gate wiring layer that constitute at least one MoS transistor together with a wiring layer in a feed cell. That's what I do.

(Function) In the semiconductor integrated circuit of the present invention, in the feed cell, which conventionally only had the function of width adjustment and wiring,
By providing a function as an element together with the wiring layer, this element can be used when modification is required due to a circuit change, etc., and the circuit can be modified by modifying the process after the wiring layer.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing the configuration of a feed cell used in the semiconductor integrated circuit of the present invention. In the figure, 13 is a feed cell, and inside this cell, a pair of aluminum 1WJ15A are arranged as in the conventional case.

15B and an N-type well region 16 are provided.

Furthermore, within this cell is a pair of P-type diffusion regions 11A.

17B and a pair of N-type diffusion regions 18A, 18B are provided between the double head regions 17A, 17B and the double head region 18A.

A polycrystalline silicon layer 19 serving as a gate wiring is continuously provided between the 18B.

For example, when a circuit consisting of a NOR gate 21 and an inverter 22 is constructed from a certain cell row on an actual chip as shown in the equivalent circuit of FIG. 2(a), the plan view of FIG. Standard cell 3 for Noah gate as shown
1 and an inverter standard cell 32 are arranged, and in this cell row, the required number of feed cells 13 having the structure shown in FIG. Then, using a mask pattern for forming a wiring layer designed by an electronic computer, the standard cell 31 for the NOR gate and the standard cell 32 for the inverter are connected to each other! ! a! LSI by forming
is manufactured. At this time, each feed cell 13A to 13
For G, no wiring layers other than 15A and 15B are formed, and these feed cells 13 only perform the functions of simply adjusting the width between the cell columns and supplying the ffi source voltage through the pair of wiring layers 15A and 15B.

After prototyping such an LSI, a circuit 2 consisting of an inverter 23 and a Nandt gate 24 was newly added to the equivalent circuit of FIG. 2(a) as shown in FIG. 2(b) due to changes in usage, etc.
Even if it becomes necessary to add the inverter 23 and the Nandt gate 24, there is no need to remanufacture from the first step. It can be added by changing only the design of a certain multilayer aluminum wiring layer and the process of forming the wiring layer.

As mentioned above, FIG. 4 shows that the above circuit 2
5 is a plan view showing an LSI chip to which 5 is added. FIG. In this example, there are two wiring layers made of aluminum.

In the figure, 41 is a hole connecting the P-type diffusion region and the arrangement 1115A, and 42 is the N-type expanded rll region and the wiring m.
15B, 43 is a newly added first aluminum wiring layer, 44
45 is a contact hole connecting the P-type diffusion region and the wiring layer 43; 46 is a contact hole connecting the N-type diffusion region and the wiring WJ43; 47 is a newly added wiring layer made of aluminum as the second layer; is a through hole that connects the added first aluminum wiring layer 43 and the newly added second WJ aluminum wiring 44. Here, the feed cell 13A
and 138 realize the Nant gate 24 in FIG. 2(b), and the feed cell 13G similarly realizes the inverter 23.

In this way, in the LSI of the above embodiment, the source, which constitutes the MoS transistor together with the wiring layer in the feed cell,
Since a drain diffusion layer and a gate wiring layer are provided, even if it becomes necessary to modify the circuit after prototyping something with a certain circuit function, the circuit can be changed by modifying the process after the wiring layer. Ru. As a result, it is possible to reduce the development period and development cost compared to the conventional method.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, a case has been described in which both a P-channel MOS transistor and an N-channel MOS transistor are substantially provided in the feed cell 13, but only one of them may be provided.

[Effects of the Invention] As explained above, according to the present invention, the development period and cost can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the configuration of a cell used in a circuit according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the circuit to be realized in this embodiment, and FIG. 3 is a diagram showing the configuration of a cell on an actual chip. FIG. 4 is a plan view showing the structure of the cell row; FIG. 5 is a plan view showing the changed structure of the cell row. 6 is a plan view showing the overall structure of an LSI chip based on the standard cell method, and FIG. 6 is a plan view showing the structure of a conventional feed cell. 13... Feed cell, 15A, 15B... Wiring layer, 16... N-type well region, 17A, 17B...
- P-type diffusion region, 18A, 18B...N-type diffusion region, 19...polycrystalline silicon layer. Applicant's agent Patent attorney Takehiko Suzue ＾ Mail rcl
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Claims (2)

[Claims] (1) A plurality of standard cells are formed on a semiconductor chip by an automatic layout design method using an electronic computer, and a standard cell row in which a plurality of standard cells are arranged in a row is used for positional alignment between each cell row or as a cell. In a semiconductor integrated circuit in which a feed cell is used as a unit cell for securing a passing wiring area on a column, a source/drain diffusion layer constituting at least one MOS transistor together with a wiring layer in the feed cell. and a gate wiring layer. (2) The semiconductor integrated circuit according to claim 1, wherein the feed cell is provided with a source, a drain diffusion layer, and a gate wiring layer constituting one P-channel MOS transistor and one N-channel MOS transistor, respectively. circuit.